CN103187494A - High voltage light-emitting diode and manufacturing method thereof - Google Patents

Abstract

A method for manufacturing a high-voltage light-emitting diode chip, comprising: forming an insulating buffer layer on a substrate; forming an n-type semiconductor layer, an active layer, and a p-type semiconductor layer on the insulating buffer layer; etching the n-type semiconductor layer after patterning , the active layer and the p-type semiconductor layer form a trench until the insulating buffer layer is exposed at the bottom of the trench, thereby forming a plurality of light-emitting units isolated by the trench; forming metal interconnection lines to connect adjacent light-emitting units in series; It is characterized in that: the depth of the groove is 2.5um-4um. The invention can reduce the damage to the LED active area caused by long-time plasma bombardment, and improve the luminous brightness of the LED.

Description

High-voltage light-emitting diode chip and manufacturing method thereof

technical field

The invention relates to a high-voltage flip-chip light-emitting diode chip. More specifically, the present invention relates to a high-voltage LED chip structure with an insulating buffer layer and a manufacturing method thereof. the

Background technique

Light-emitting diodes (LEDs) have the advantages of long life, energy saving, environmental protection, and rich colors. Therefore, with the development of technologies such as epitaxy, chips, and packaging, and the further improvement of luminous efficiency, LEDs have been gradually used in lighting, display, medical treatment, etc. each field. Traditional gallium nitride-based light-emitting diodes work under DC voltage, the voltage range is 2.9-3.5V, and the working current is usually 20mA. In order for light-emitting diodes to achieve the brightness required for general lighting, the operating current of the LED chip must generally be increased to more than 100mA. Currently, 100mA, 350mA and 700mA are commonly used. When LED is used for general lighting, it needs about 220V-380V AC mains drive. If a high-power LED chip with high current is used, a larger transformer is needed in the drive device, and the AC power needs to be converted into Direct current, resulting in a larger volume of the entire LED lamp, and its lifespan is greatly reduced due to the introduction of electrolytic capacitors (the lifespan is only 2000-5000 hours). In addition, the line loss caused by high current driving is also relatively high, resulting in increased wasteful energy consumption and increased heat dissipation burden on lamps. the

In US Pat. No. 6,787,999, many individually packaged single LEDs are mounted in series on a PCB substrate to form a high-voltage LED array, which is used in high-voltage applications. This solution can save a large transformer and can also reduce the operating current. However, this solution greatly increases the volume of the light-emitting module, and since each die is interconnected through wires, the heat dissipation performance and reliability are reduced. the

In the Chinese invention patent application CN102867837A, a LED array isolated by deep grooves on a sapphire substrate is disclosed, which realizes chip-level LED integration, reduces the packaging volume of the light-emitting module, and uses chip-level metal layer interconnection Instead of wire interconnects, the reliability of the LED array is improved. However, in this prior art solution, as shown in Figure 1, since the epitaxial layer is to be etched from the p-type layer 13 to the sapphire substrate 10, it is necessary to etch an isolation deep groove 101 with a depth of 4-7um, so that each LED The reliability of the interconnection 20 between the units 100 deteriorates due to climbing through such a deep isolation groove 101, resulting in a low yield of high-voltage LED chips, and a greatly reduced working life under high voltage, while the deep etching process And the thickened electrode process to achieve safe interconnection increases the manufacturing cost of high-voltage LEDs. These problems have greatly affected the industrialization and marketization process of high-voltage LEDs, resulting in the current market utilization rate of high-voltage LEDs. Etching takes a relatively long time. When ICP etching is used, long-term plasma bombardment will cause damage to the active area of the LED and reduce the luminous brightness of the LED. the

Contents of the invention

The purpose of the present invention is to provide a high-voltage LED chip with an insulating buffer layer and its manufacturing method, which can reduce the damage to the LED active area caused by long-time plasma bombardment, and improve the luminous brightness of the LED. the

The invention provides a method for manufacturing a high-voltage light-emitting diode chip, comprising:

Form an insulating buffer layer on the substrate;

Forming an n-type semiconductor layer, an active layer and a p-type semiconductor layer on the insulating buffer layer;

After patterning, etch the n-type semiconductor layer, active layer and p-type semiconductor layer to form a trench until the bottom of the trench exposes the insulating buffer layer, thereby forming a plurality of light-emitting units isolated by trenches;

Form metal interconnection lines to connect adjacent light-emitting units in series; it is characterized in that:

The depth of the groove is 2.5um-4um. the

The present invention also provides a high-voltage light-emitting diode chip, including:

a substrate and an epitaxial buffer layer on said substrate;

There are multiple light-emitting units on the epitaxial buffer layer, and the light-emitting units are separated by isolation trenches above the epitaxial buffer layer; each light-emitting unit includes an n-type semiconductor layer, an active layer and a p-type semiconductor layer;

A metal interconnection line connects adjacent light-emitting units in series; it is characterized in that:

The epitaxial buffer layer is an insulating buffer layer, and the total thickness of the n-type semiconductor layer, active layer and p-type semiconductor layer is 2.5um-4um. the

The beneficial effects of the present invention are: the high-voltage LED chip adopts an insulating buffer layer, and the thickness of the LED epitaxial layer above the substrate is about 2.5-4um, and the deep groove only needs to be etched to the insulating buffer layer instead of the substrate, thereby greatly Reduce the etching depth of the deep groove, and the interconnection layer between the chip units passing through the deep groove can be made thinner, and the reliability of the interconnection line is also greatly improved under the premise of reducing the manufacturing cost. Etching damage to the LED. the

Description of drawings

In order to make the purpose, technical solutions and advantages of the present invention clearer, below in conjunction with specific embodiment, and with reference to accompanying drawing, the present invention is described in further detail, wherein:

Fig. 1 is a schematic structural diagram of a high-voltage LED chip in the prior art;

Fig. 2-Fig. 5 is the schematic diagram of the technological process of preparing high-voltage LED chip according to the first embodiment of the present invention;

Detailed ways

The present invention will be further described below in conjunction with Fig. 2 to Fig. 5 and embodiments. the

The gallium nitride (GaN)-based LED epitaxial layer includes a substrate 20 , a buffer layer 21 formed on the surface of the substrate, and an n-type semiconductor layer 22 , an active layer 23 , and a p-type semiconductor layer 24 formed on the buffer layer 21 . The substrate 20 is a sapphire substrate, a SiC substrate, a Si substrate, a GaN substrate or an AlN substrate. The buffer layer 21 is an insulating buffer layer, which may be AlN, BN, or a superlattice structure of AlN/GaN, or an insulating GaN buffer layer formed by lightly doping p-type unintentionally doped GaN. the

Wherein, the AlN buffer layer includes an AlN nucleation layer and an AlN template layer on the surface of the sapphire substrate. In the MOCVD equipment, trimethylaluminum (TMAl), reaction gas NH ₃ and carrier gas H ₂ are fed. First raise the temperature to 1000°C, pass H ₂ into it, and pretreat the sapphire substrate at high temperature for a few minutes; then lower the temperature to 500-800°C, preferably about 550-600°C, and epitaxially grow a low-temperature AlN nucleation layer, The growth thickness is about 20-100 nm; then the temperature is raised to 1100-1600° C., preferably the temperature is 1200-1300° C., to grow the AlN template layer. During the growth of all AlN layers, the low pressure of the MOCVD reaction chamber is maintained, and the pressure is between 30 torr-150 torr, preferably 50-100 torr. The thickness of the AlN buffer layer is 200nm-10um, preferably 500nm-2um.

Since unintentionally doped GaN is generally an n-type semiconductor, doping a small amount of Mg to compensate the electrons in it can form an insulating GaN layer, and using the insulating GaN layer as a buffer layer can prevent current from passing through the buffer layer. The amount of light doping is determined according to the carrier concentration in the n-type semiconductor. The thickness of insulating GaN is 2um-5um. The growth process refers to the formation method of the low-temperature GaN buffer layer in the prior art. the

The p-type semiconductor layer 24 may be Mg-doped GaN, while the n-type semiconductor 22 is Si-doped GaN material, and the active region 23 includes a multi-quantum well structure composed of GaN/InGaN or AlGaN/InGaN. The total thickness of the p-type semiconductor layer 24 , the n-type semiconductor layer 22 and the active layer 23 is 2.5um-4um. the

As shown in FIG. 3 , the GaN-based LED epitaxial layer structure is patterned with photoresist, and then etched to the surface of the insulating buffer layer 21 to form a groove 241 , and the LED light-emitting unit 242 is isolated by the groove 241 . The etching process adopts ICP etching, or uses sulfuric acid and phosphoric acid to etch at a certain temperature. the

After or before etching to form the trench 241 , dry etching is used to form the mesa 243 to expose the n-type semiconductor layer 22 , as shown in FIG. 4 . the

其作为LED发光单元242侧壁的钝化层，防止漏电。  As shown in Figure 5, an insulating dielectric layer 26 is formed in the trench 241 and on the sidewalls of the adjacent LED light-emitting units 242. The insulating dielectric layer 26 can be silicon oxide, silicon nitride or aluminum nitride, etc., and can be processed by PECVD, sputtering, etc. Or spin coating and other methods to form. The thickness of the insulating dielectric layer 26 is

It acts as a passivation layer on the side wall of the LED light emitting unit 242 to prevent leakage.

A transparent electrode layer (not shown) is formed on the p-type semiconductor layer 24 as a current spreading layer. The transparent electrode layer can be ITO, Ni/Au alloy or ZnO, etc. The transparent electrode layer can be formed by sputtering or EB. The transparent electrode layer may be formed before or after etching the trenches 241 and the mesas. the

Then, a p-electrode pad 28 is formed on the transparent electrode layer of the p-type semiconductor layer 24 , and an n-electrode pad 29 is formed on the n-type semiconductor layer 22 . the

Finally, metal interconnection lines 27 are formed between the p-electrode pads 28 and n-electrode pads 29 of adjacent LED light-emitting units 242 , so that the LED light-emitting units 242 in the chip are connected in series. Metal interconnects 27 are formed and patterned simultaneously with p and n electrode pads 28,29. Since the depth of the groove 241 is only 2.5um-4um, the thickness of the metal interconnection 27 can be relatively thin, for example, the total thickness can be in As we all know, precious metals such as Pt and Au are mostly used for semiconductor metal electrodes, and the reduction of metal thickness can greatly reduce the production cost of chips.

Secondly, the groove depth in the prior art is generally at least 5um-8um. In order to reduce the loss of the active area, the groove width between the light-emitting units in the chip is between 10um-20um. Under the condition of this aspect ratio Therefore, it is difficult to guarantee the reliability of the metal interconnection on the side wall of the LED light-emitting unit. However, the special LED epitaxial structure in the present invention makes the groove depth only 2.5um-4um, and it is easy to form reliable electrode interconnection. the

In addition, when the etching depth is reduced by half, the etching time is correspondingly reduced by half, so that the damage caused by dry etching has a greatly reduced effect on the brightness of the LED. the

Example 1

Use MOCVD equipment to form an AlN buffer layer on the c-surface of the sapphire substrate. The thickness of the AlN buffer layer is 1.2um; on the AlN buffer layer, sequentially form an n-type GaN layer of about 3um and a GaN/InGaN multiple quantum well with a thickness of 100-200nm layer and a 100-300nm thick p-type GaN layer. the

After the epitaxial wafer is cleaned, an ITO transparent electrode layer is formed by electron beam evaporation on the p-type GaN layer. After patterning, ICP etches the mesa to expose the n-type GaN layer; PECVD silicon oxide can also be used as a masking layer for etching trenches. Mask the photoresist to form an isolation trench with a depth of about 3.5um between the LED light-emitting units; after removing the masking layer, photolithography forms the p and n electrode solder joint areas and metal interconnection areas, and uses electron beam evaporation of CrPtAu to form p , n-electrode solder joints and metal interconnection lines, the total thickness of CrPtAu is about Finally, the sapphire substrate is thinned and cut by laser, and the high-voltage LED chip is formed after splitting. The high-voltage LED chip is composed of 16 LED light-emitting units in series, and the working voltage is about 50V.

The above description is only illustrative of the present invention, rather than restrictive. Those of ordinary skill in the art understand that many modifications, changes, or Equivalent, but all will fall within the protection scope of the present invention. the

Claims (9)

1. the manufacture method of a baroluminescence diode chip for backlight unit comprises:

Form the buffer insulation layer at substrate;

Form n type semiconductor layer, active layer and p-type semiconductor layer at the buffer insulation layer;

The graphical described n type semiconductor layer of after etching, active layer and p-type semiconductor layer form groove, expose the buffer insulation layer until channel bottom, thereby form a plurality of luminescence units by trench isolations;

Form metal interconnecting wires, adjacent luminescence unit is together in series; It is characterized in that:

The degree of depth of described groove is 2.5um-4um.

2. the manufacture method of baroluminescence diode chip for backlight unit as claimed in claim 1, wherein said buffer insulation layer is AlN or AlN/GaN superlattice.

3. the manufacture method of baroluminescence diode chip for backlight unit as claimed in claim 1, wherein said buffer insulation layer carries out the formed insulation of p-type light dope GaN resilient coating for the GaN to involuntary doping.

4. the manufacture method of baroluminescence diode chip for backlight unit as claimed in claim 1, wherein the thickness of metal interconnecting wires is

5. the manufacture method of baroluminescence diode chip for backlight unit as claimed in claim 1, the degree of depth of wherein said groove is 2.5um-3um.

6. the manufacture method of baroluminescence diode chip for backlight unit as claimed in claim 5, wherein said groove forms by dry etching.

7. the manufacture method of baroluminescence diode chip for backlight unit as claimed in claim 1, wherein substrate is Sapphire Substrate, SiC or Si substrate.

8. the manufacture method of baroluminescence diode chip for backlight unit as claimed in claim 1, wherein the drive current of each luminescence unit is 20-40mA.

9. baroluminescence diode chip for backlight unit comprises:

Substrate and the epitaxial buffer layer on described substrate;

Have a plurality of luminescence units at epitaxial buffer layer, the isolated groove by the epitaxial buffer layer top between the luminescence unit separates; Each luminescence unit comprises n type semiconductor layer, active layer and p-type semiconductor layer;

Metal interconnecting wires is together in series adjacent luminescence unit; It is characterized in that:

Described epitaxial buffer layer is the buffer insulation layer, and the gross thickness of described n type semiconductor layer, active layer and p-type semiconductor layer is 2.5um-4um.

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