CN103219985B - The system and method that the power distribution of integrated circuit controls - Google Patents

Abstract

The present invention relates to a system and method for power distribution control of integrated circuits. The invention discloses a device, which comprises: a first pin used to supply power to a first power domain of an integrated circuit; a second pin used to supply power to a second power domain of the integrated circuit; a switching regulator devices; and controllers. The switching regulator is coupled to the first pin to provide a first regulated power supply to the first power domain and to the second pin to provide a second power supply to the second power domain. Regulated power supply. The controller is coupled to the first pin and the second pin to selectively reduce current flow to at least the second pin during a low power event.

Description

System and method for power distribution control of integrated circuits

This application is a PCT application with an international filing date of April 23, 2007, an international application number of PCT/US2007/067227, and a PCT application titled "System and Method for Power Distribution Control of Integrated Circuits", which entered the Chinese national phase application number of 200780016440.4 divisional application of the patent application.

Related applications

This application is related to Ser. No. 11/431,790, filed May 10, 2006, entitled "System and Method of Silicon Switched Power Delivery Using a Package."

technical field

The present invention generally relates to systems and methods of power distribution control.

Background technique

Advances in technology have resulted in smaller and more powerful personal computing devices. For example, many types of portable personal computing devices are small, lightweight, and easily carried by users, including wireless computing devices such as portable wireless telephones, personal digital assistants (PDAs), and paging devices. More specifically, portable wireless telephones, such as cellular (analog and digital) telephones and IP telephones, can communicate voice and data packets over wireless networks. In addition, many such wireless telephones include other types of devices that may be incorporated into them. For example, wireless telephones may also include digital cameras, digital video cameras, digital recorders, and audio file players. In addition, such wireless telephones can include a network interface that can be used to access the Internet. Accordingly, these wireless telephones contain significant computing capabilities.

As the demand for new high-performance features in portable systems increases, system-level power management becomes increasingly important in order to reduce power consumption and extend battery life. For example, reducing power consumption of digital processing in portable electronic devices can improve battery life and increase the available power budget for other features, such as color displays and backlights. To reduce power consumption, circuit designers have employed various power management techniques.

A typical integrated circuit includes a substrate, which may include multiple embedded circuit structures, and one or more integrated circuit devices electrically coupled to the substrate. To reduce the power consumption of such embedded circuit structures, one technique uses multiple power regulators to generate multiple power supplies that can be utilized to meet the power requirements of various embedded circuit structures. Since at least one of the embedded circuit structures may use less power than other structures, a lower power supply may be provided to that structure, saving power for other components in the overall power budget. However, high voltage regulators consume a lot of chip area.

Another technique to reduce power consumption involves switching power supplies when power is not needed to disable power to embedded circuit structures. However, high voltage switches can be difficult to scale down as semiconductor fabrication techniques enable smaller and smaller devices. Additionally, such switches cause layout and routing complexity.

Accordingly, it would be advantageous to provide an improved power distribution system and method that reduces power loss.

Contents of the invention

In certain embodiments, an apparatus is disclosed comprising: a first pin for supplying power to a first power domain of an integrated circuit; a second pin for supplying power to a second power domain of the integrated circuit; switching regulators; and controllers. The switching regulator is coupled to the first pin to provide a first regulated power supply to the first power domain and to the second pin to provide a second power supply to the second power domain. Regulated power supply. The controller is coupled to the first pin and the second pin to selectively reduce current flow during a low power event. In a particular embodiment, the controller is adapted to limit current flow to a current level below about 100 nanoamperes in response to a low power event.

In another specific embodiment, a power manager integrated circuit includes: a buck controller to generate a first regulated power supply; a first pin; a second pin; and a main controller. The first pin is coupled to a first power domain of the integrated circuit and is responsive to the buck controller to provide a first regulated power supply to the first power domain. The second pin is coupled to a second power domain of the integrated circuit to provide a second regulated power supply derived from the first regulated power supply to the second power domain. The master controller is adapted to determine a mode of operation and selectively substantially reduce current flow to the second pin when the mode of operation includes a low power mode.

In yet another particular embodiment, a method is provided that includes supplying a first regulated supply voltage to a first pin of a power manager integrated circuit and supplying a second regulated supply voltage to a second pin of the power manager integrated circuit. regulated supply voltage. The method further includes selectively disabling or substantially reducing current flow to the second pin in a particular mode of operation. The power manager integrated circuit is coupled to an integrated circuit device including a first power domain responsive to a first pin and a second power domain responsive to a second pin. In a particular embodiment, selectively disabling current flow includes deactivating a transistor to disable or reduce current flow to the second pin when the integrated circuit device is in a low power operating mode.

One particular advantage provided by embodiments of the power manager integrated circuit is that semiconductor fabrication processes can be utilized in conjunction with variable high voltage transistor devices in order to limit current leakage. In a particular embodiment, a power manager integrated circuit can be fabricated using older, lower-cost semiconductor fabrication technology and can be utilized to power a newer and/or more expensive semiconductor manufacturing technology. Circuit devices produced by state-of-the-art semiconductor manufacturing techniques supply power.

Another particular advantage provided by embodiments of the power manager integrated circuit is that the power manager integrated circuit substantially reduces the leakage current of the electronic device to a current of less than about 100 nanoamperes when the top switch is disabled. level.

Yet another particular advantage is that a single regulator can be utilized within a power manager integrated circuit to provide regulated power supply to multiple power domains of an integrated circuit device. A particular advantage of a single regulator is that the cost of the power manager integrated circuit is reduced. Furthermore, a single regulator of the power manager integrated circuit allows the state of the electronic device to be maintained via a single power domain.

Yet another advantage of certain embodiments of a power manager integrated circuit coupled to an integrated circuit device is that no leakage gating resources are required in the integrated circuit device to prevent current leakage. Since such gating resources are not required, the area and complexity of the power routing of the integrated circuit device can be reduced during the integrated circuit design process.

Other aspects, advantages and features of the present invention will be readily apparent upon review of the entire application, which consists of the following sections: Description of Drawings, Detailed Description and Claims.

Description of drawings

Aspects and attendant advantages of the embodiments described herein will be more readily appreciated by referring to the following detailed description when taken in conjunction with the accompanying drawings, in which:

1A is a diagram of an illustrative embodiment of an electronic device including a particular embodiment of a power manager integrated circuit in a top switch configuration;

1B is a diagram of an alternate embodiment of an electronic device that includes a particular embodiment of a power manager integrated circuit in a bottom switcher configuration;

2 is a diagram of an illustrative portion of a particular embodiment of a power manager integrated circuit;

3 is a diagram of an illustrative portion of a particular alternative embodiment of the power manager integrated circuit of FIG. 2;

4 is a diagram of an illustrative portion of another particular illustrative embodiment of a power manager integrated circuit;

5 is a block diagram of a particular illustrative embodiment of an integrated circuit device having multiple power domains and including a power manager integrated circuit according to FIGS. 1-4;

6 is a flowchart of a particular illustrative embodiment of a method of selectively disabling current flow to at least one pin of a power manager integrated circuit;

7 is a schematic diagram of an exemplary cellular telephone incorporating a processor and memory in which the systems and methods of FIGS. 1-6 may be used;

8 is a schematic diagram of an exemplary wireless internet protocol phone incorporating a processor and memory in which the systems and methods of FIGS. 1-6 may be used;

9 is a schematic diagram of an exemplary portable digital assistant incorporating a processor and memory in which the systems and methods of FIGS. 1-6 may be used; and

10 is a schematic diagram of an exemplary audio file player incorporating a processor and memory in which the systems and methods of FIGS. 1-6 may be used.

detailed description

1A is a block diagram of an illustrative embodiment of an electronic device 100 that includes a particular embodiment of a power manager integrated circuit (PMIC) 102 and an integrated circuit device 104 . The integrated circuit device 104 may include multiple power domains, such as a first power domain 106 and a second power domain 108 . The power manager integrated circuit 102 may include a switching regulator 110 , logic 112 , a transistor (switcher) 114 , a first pin 116 and a second pin 118 . Switching regulator 110 is coupled to first pin 116 and via switch 114 to second pin 118 . The switch 114 may be a metal oxide semiconductor field effect transistor (MOSFET), a field effect transistor (FET), a bipolar junction transistor, or a switch controllable by the logic 112 to selectively enable and disable the flow of current to the second pin 118 Another circuit arrangement. In general, switch 114 may be an n-channel MOSFET or a p-channel MOSFET device in PMIC technology. If switcher 114 is an n-channel MOSFET device, switching regulator 110 may have a greater voltage potential than integrated circuit device 104 .

Switcher 114 includes a first terminal 120 coupled to first pin 116 , a control terminal 122 coupled to logic 112 , and a second terminal 124 coupled to second pin 118 . The first pin 116 may be coupled to the first power domain 106 of the integrated circuit device 104 and the second pin 118 may be coupled to the second power domain 108 of the integrated circuit device 104 . The third pin 126 may provide a ground connection to the PMIC 102 for the first power domain and the second power domain.

In normal operating mode, switching regulator 110 provides a regulated power supply to first pin 116 . Logic 112 may activate switch 114 via control terminal 122 to provide at least a portion of the regulated power supply to second pin 118 . During shutdown events or low power events, or during other power saving modes of operation, logic 112 may selectively deactivate switch 114 to substantially reduce current flow to second pin 118 . By reducing the current flow to the second pin 118 , the logic 112 substantially reduces the current flow to the second power domain 108 of the integrated circuit device 104 . In certain embodiments, switching regulator 110 may continue to deliver power to first pin 116 and first power domain 106 after reducing current flow to second pin 118 . Accordingly, switching regulator 110 may be utilized to selectively provide power to second power domain 108 of integrated circuit device 104 .

In general, it should be appreciated that random access memory (RAM), such as synchronous dynamic random access memory (SDRAM), and other memory components account for a significant amount of static power consumption. For example, a 256-megabit SDRAM, such as that produced by Japan's Elpida Memory, Inc., can draw as much as 275 nanoamperes at 1.8 volts or approximately 1.844× per bit during normal operation. 10 ^-9 mW. SDRAM, which consumes 1.02pA per bit at 1.8 volts, consumes about 1.84 petawatts per bit. By utilizing the PMIC 102 to selectively turn off power to the second power domain 108 of the integrated circuit device 104, which may include SDRAM devices, the power consumption of the circuit device 100 may be reduced. By utilizing a single switching regulator (such as switching regulator 110 ) to generate a regulated power supply, it is possible to deliver a consistent power supply to one power domain (such as first power domain 106 ), allowing State information is maintained in memory locations of the integrated circuit device 104 while substantially reducing power to other power domains of the integrated circuit device 104 (eg, the second power domain 108 ).

FIG. 1B is a block diagram of an alternative illustrative embodiment of an electronic device 150 that includes a particular embodiment of a power manager integrated circuit (PMIC) 152 and an integrated circuit device 154 . Electronic device 150 includes PMIC 152 arranged in a bottom switch configuration. In particular, integrated circuit device 154 may include multiple power domains, such as first power domain 156 and second power domain 158 . Power manager integrated circuit 152 may include switching regulator 160 , logic 162 , transistor (switcher) 164 , first pin 166 , second pin 168 , and third pin 176 . Switching regulator 160 is coupled to first power domain 156 and second power domain 158 via a first pin 166 . Switcher 164 includes a first terminal 170 coupled to second power domain 158 via a second pin 168 . Switcher 164 also includes a control terminal 172 coupled to logic 162 , and a second terminal 174 coupled to logic 162 and a third pin 176 . First power domain 156 may be coupled to logic 162 via third pin 176 . In operation, PMIC 152 may selectively deactivate second power domain 158 by deactivating switch 164 to reduce current flow while providing power to first power domain 156 via switching regulator 160 .

In general, it should be appreciated that while PMIC 102 and PMIC 152 of FIGS. 1A and 1B may include more than one switch 114 , and integrated circuit device 104 may include multiple power domains. In certain embodiments, the switches may be selectively deactivated to disable power to selected ones of the plurality of power domains of the integrated circuit device 104 .

FIG. 2 is a diagram of an illustrative portion 200 of a particular embodiment of the power manager integrated circuit (PMIC) 102 . PMIC 102 includes switching regulators, such as switching regulator 110 and logic 112 . The switching regulator 110 may include a buck controller 204 , a first transistor 206 and a second transistor 208 . Logic 112 may include master controller 210 . The PMIC 102 may also include a third transistor 212 , a first pin 116 , a second pin 118 , a third pin 214 , and a fourth pin 218 . The fourth pin 218 may be coupled to a power supply terminal, such as V _DD in FIG. 1A .

In general, the first transistor 206 includes a first terminal 220 coupled to the fourth pin 218 , a control terminal 222 coupled to the buck regulator 204 , and a second terminal 224 coupled to the third pin 214 . The second transistor 208 includes a first terminal 226 coupled to the third pin 214, a control terminal 228 coupled to the buck controller 204, and a second terminal 230 coupled to a voltage supply terminal, which may be electrically grounded. The third transistor 212 includes a first terminal 232 coupled to the first pin 116 , a control terminal 234 coupled to the main controller 210 , and a second terminal 236 coupled to the second pin 118 .

An external inductor 238 may be coupled between the third pin 214 and the first pin 116 . A capacitor 240 may be coupled between the first pin 116 and a voltage supply terminal (which may be an electrical ground) for filtering the power supply to the first power domain. A capacitor 242 may be coupled between the second pin 118 and a voltage supply terminal (which may be an electrical ground) for filtering the power supply to the second power domain.

In a particular embodiment, switching regulator 110 is coupled to first pin 116 to provide a first regulated power supply to a first power domain, and via third transistor 212 to second pin 118 to provide a second power domain The domain provides a second regulated power supply. The master controller 210 is coupled to the control terminal 234 of the third transistor 212 and to the second pin 118 to selectively deactivate the third transistor 212, for example during a low power event. The third transistor 212 may be a high voltage transistor and may operate as a switch to selectively deactivate the second regulated power supply to the second power domain.

In operation, the main controller 210 may selectively activate the third transistor 212 to provide current flow to the second pin 118 during the normal operating mode. The main controller 210 can selectively deactivate the third transistor 212 to substantially reduce or shut down the flow of current to the second pin 118 during a low power event, such as a shutdown event, an idle event, a reduced power events or any combination thereof. In a particular embodiment, main controller 210 is operable to substantially reduce leakage current via third transistor 212 , for example, to a current level below about 100 nanoamperes.

In general, the third transistor 212 cooperates with the main controller 210 to supply the first Two pins 118 provide a switched power supply without the use of additional components such as additional voltage regulators. The first pin 116 receives the regulated output from the buck regulator 204 and the second pin 116 receives the unregulated output generated from the regulated output via the third transistor (top switch) 212 . In a particular embodiment, the third transistor 212 may be designed to provide a voltage drop of approximately 5 mV when a 100 mA load is coupled to the second pin 118 .

In general, the circuit design process often involves establishing and maintaining correct circuit behavior under a variety of operating conditions that include process, voltage, and temperature (PVT) variations. Therefore, modeling the behavior of analog circuits often involves extending the integrated circuit model to accurately represent the behavior of the integrated circuit at possible PVT values. For example, to meet the 5mV DC loss specification, the third transistor 212 should be designed to have an on-resistance small enough to maintain consistent performance at PVT values. For example, the total loss resistance (R_loss) of PMIC102 can be written as the sum of on-resistance (R_on), wiring resistance (R_routing) and package resistance (R_package), as follows:

R_loss=R_on+R_routing+R_package (equation 1)

If the maximum R_loss is about 50 Mohms, and if R_package and R_routing are about 10 Mohms and 20 Mohms respectively, then the maximum on-resistance (R_on) should be less than about 20 Mohms on all PVT corners. In a particular embodiment, the on-resistance is less than about 7 Mohms.

In a particular embodiment, the output voltage specification specifies a medium voltage n-channel field effect transistor (NFET) for the third transistor 212 . On-resistance data for medium-voltage NFETs in a proprietary 0.18nm high-voltage complementary metal-oxide-semiconductor (CMOS) process can be estimated according to the following equation:

R_on=3.5 Mohm*mm ² (equation 2)

If the on-resistance is about 7 Mohm, the layout area of the third transistor can be estimated to be 0.5 mm ² . In a particular embodiment, an estimated wafer price of approximately 2.4 cents per square millimeter indicates a silicon cost of 1.2 cents for the third switch 212 .

In a particular embodiment, PMIC 102 and associated integrated circuits including multiple power domains (eg, integrated circuit device 104 of FIG. 1A ) may be fabricated using different semiconductor fabrication techniques. For example, PMIC 102 may be fabricated using a 0.18nm high voltage CMOS process, while integrated circuit device 104 may be fabricated using a 45nm process. In another particular embodiment, the PMIC 102 may be fabricated using 45nm technology and the integrated circuit device may be fabricated using 100nm technology (e.g., the PMIC 102 may be fabricated using older fabrication technologies while the integrated circuit device (such as the Integrated circuit device 104 ) may be fabricated using newer fabrication techniques).

FIG. 3 is a diagram of a portion 300 of a particular illustrative embodiment of the power manager integrated circuit (PMIC) 102 of FIG. 2 . PMIC 102 may include switching regulator 110 , logic 112 and other elements of portion 200 of FIG. 2 , and fourth transistor 302 arranged in parallel with third transistor 212 . The fourth transistor 302 may include a first terminal 304 coupled to the first pin 116 , a control terminal 306 coupled to the control terminal 234 of the third transistor 212 , and a second terminal 306 coupled to the second pin 118 .

In operation, the fourth transistor 302 may reduce the voltage drop across the third transistor 212 during normal operation in part by dividing current flow between the third transistor 212 and the fourth transistor 214 . Furthermore, by activating the third transistor 212 and the fourth transistor 302 , more current can flow to the second pin 118 than would otherwise be possible without exceeding the current rating of the third transistor 212 . During a low power or shutdown event, the main controller 210 may deactivate the third transistor 212 and the fourth transistor 302 in order to disconnect current flow to the second pin 118 and reduce leakage. In certain embodiments, leakage current can be reduced to levels below about 100 nanoamperes.

FIG. 4 is an illustration of a particular illustrative embodiment of a portion 400 of another particular embodiment of a power manager integrated circuit (PMIC) 102 . PMIC 102 includes switching regulator 110 and logic 112 . In this particular illustrative embodiment, logic 112 includes first low dropout regulator 402 and second low dropout regulator 404 . As used herein, a low dropout regulator may include a voltage regulator that provides a regulated voltage supply with low voltage drop (eg, low power consumption). Line 406 couples low dropout regulators 402 and 404 to first pin 116 . The first low dropout regulator 402 is coupled to the second pin 118 to provide a second regulated power supply derived from the first regulated power supply provided by the switching regulator 110 to the first pin 116, And the second low dropout regulator 404 is coupled to the fifth pin 408 . In this embodiment, the first pin 116 may be coupled to a first power domain of a circuit device (eg, integrated circuit device 104 of FIG. 1A ) to provide a first regulated power supply to the first power domain. The second pin 118 may be coupled to a second power domain of the circuit arrangement to provide a second regulated power supply to the second power domain. The fifth pin 408 may be coupled to a third power domain of the circuit arrangement to provide a third regulated power supply to the third power domain. Logic 112 may include a plurality of low dropout regulators, and may be adapted to selectively control each low dropout regulator to activate and deactivate a regulated power supply to an associated power domain of the integrated circuit. A capacitor 410 may be coupled between the fifth pin 408 and a voltage supply terminal (which may be an electrical ground) to filter the power supply to the third power domain.

In this approach, switching regulator 110 provides a first regulated power supply to first pin 116, and low dropout regulators 402 and 404 generate second and third regulated power supplies, respectively, based on the first regulated power supply. power supply. Low dropout regulators 402 and 404 may be designed to provide power supplies that are approximately matched supplies (eg, within 5mV of each other). In a particular embodiment, the first low dropout (LDO) regulator 402 may be an approximately 300 mA LDO regulator and the second LDO regulator 404 may be an approximately 150 mA LDO regulator. The layout areas of the first LDO regulator 402 and the second LDO regulator 404 can be estimated to be approximately 0.17 mm ² and 0.11 mm ² , respectively. The total silicon cost of the two LDO regulators 402 and 404 may be approximately 0.67 cents.

In a particular embodiment, switching regulator 110 may be a high voltage power regulator. LDO regulators 402 and 404 may be low voltage regulators adapted to derive power from switching regulator 110 . Therefore, LDO regulators 402 and 404 can be produced using less silicon area than switching regulator 110 .

FIG. 5 is a block diagram of a system 500 including an integrated circuit device 104 having multiple power domains and including the power manager integrated circuit 102 according to FIGS. 1-4 . Integrated circuit device 104 may contain multiple power domains, including V _C1Z1 power domain 502, distributed power domain 504, V _C1Z3 power domain 506, distributed power domain 508, V _CC1 power domain 510, distributed power domains 512 and 514 , V _C1Z2 power domain 516 , V _C2Z1 power domain 518 and V _CC2 power domain 520 . A power manager integrated circuit (PMIC) 102 may be adapted to provide one or more regulated power supplies to one or more power domains using a single switching regulator, as shown in FIGS. 1-4 . PMIC 102 may provide a first regulated power supply V _REG to V _C1Z1 power domain 502 , eg, via line 522 . PMIC 102 can also provide a second power supply (V ₂ ) to V _C1Z2 power domain 516 via line 524 , a third power supply (V ₃ ) to V _C2Z1 power domain 518 via line 526 , and to V _C1Z3 power domain 518 via line 528 506 provides a fourth power supply (V ₄ ). The second, third and fourth power supplies (V ₂ , V ₃ and V ₄ ) may be unregulated if PMIC 102 incorporates the particular arrangement of FIGS. 1-3 , or if PMIC 102 incorporates the particular arrangement of FIG. Second, third and fourth power supplies (V ₂ , V ₃ and V ₄ ) are adjustable.

6 is a flowchart of a method of selectively disabling or substantially reducing current flow to at least one pin of a power manager integrated circuit of a system. A power supply may be received at a power manager integrated circuit from a voltage supply terminal (block 600). A first regulated supply voltage is supplied to a first pin of a power manager integrated circuit (block 602 ). When the system is in the normal operating mode (block 604), current flow is selectively enabled to a second pin coupled to a second power domain of an integrated circuit device comprising a response to A first power domain of the first pin and a second power domain responsive to the second pin (block 606 ). In general, current flow may be selectively enabled by activating a transistor (eg, third transistor 212 of FIGS. 2 and 3 ) to enable current flow to the second pin. Current flow to the second pin may be selectively disabled when the system is not in a normal mode of operation, eg, when the system is in a low power or power off mode of operation (block 608 ). The voltage level to one of the first power domain or the second power domain is optionally scaled (block 610 ). In certain embodiments, for example, the logic of the PMIC (such as logic 112 in FIG. 1A ) is operable to scale the voltage levels reaching one or more power domains of the integrated circuit device to scale or adjust for foldable power domain power supply.

In certain embodiments, the reach to the second pin (eg, the second pin of FIGS. pin 118) to selectively disable current flow. In certain embodiments, current flow to the second pin can be reduced to a current level of less than about 100 nanoamperes, thereby reducing power to the second power domain.

In a particular embodiment, the method may include providing a regulated power supply to a first pin during a low power mode to provide power to a first power domain, which may include memory, in order to maintain a state of the integrated circuit device. In certain embodiments, the first regulated power supply and the second regulated power supply may be at different power levels. For example, a power manager integrated circuit can provide a different regulated power supply to each of multiple power domains of the integrated circuit, and can selectively deactivate each power supply.

FIG. 7 illustrates an exemplary, non-limiting embodiment of a portable communication device, generally designated 700 . As illustrated in FIG. 7, the portable communication device includes a system-on-chip 722 that includes a processing unit 710, which may be a general purpose processor, a digital signal processor, an RISC machine processor, or any combination thereof. FIG. 7 also shows display controller 726 , which is coupled to processing unit 710 and display 728 . Furthermore, an input device 730 is coupled to the processing unit 710 . Memory 732 is coupled to processing unit 710 as shown. Additionally, an encoder/decoder (CODEC) 734 may be coupled to the processing unit 710 . A speaker 736 and a microphone 738 may be coupled to the codec 730 . In particular embodiments, the processing unit 710, display controller 726, memory 732, codec 734, other components, or any combination thereof may receive power via one or more pins of a power manager integrated circuit (PMIC) 757, As shown in Figures 1 to 6 and as described herein.

FIG. 7 also indicates that a wireless controller 740 may be coupled to the processing unit 710 and a wireless antenna 742 . In a particular embodiment, power supply 744 is coupled to system on chip 722 . Furthermore, in a particular embodiment, as illustrated in FIG. 7 , display 728 , input device 730 , speaker 736 , microphone 738 , wireless antenna 742 , and power supply 744 are external to system on chip 722 . However, each is coupled to components of system on chip 722 . PMIC 757 may be coupled to power supply 744 to receive an unregulated power supply, which PMIC 757 may utilize to generate a regulated power supply and selectively activate one or more power domains to the integrated circuit device The integrated circuit device may include one or more elements (eg, processing unit 710, wireless controller 740, memory 732, display controller 726, and codec 734).

In particular embodiments, processing unit 710 may process instructions associated with programs necessary to perform the required functionality and operation of the various components of portable communication device 700 . For example, a user may speak into microphone 738 when establishing a wireless communication session via a wireless antenna. An electronic signal representing the user's voice may be sent to codec 734 for encoding. The processing unit 710 may perform data processing of the codec 734 in order to encode the electronic signal from the microphone. Additionally, incoming signals received via wireless antenna 742 may be sent by wireless controller 740 to codec 734 for decoding and to speaker 736 . The processing unit 710 may also perform data processing of the codec 734 when decoding a signal received via the wireless antenna 742 .

Additionally, processing unit 710 may process input received from input device 730 before, during, or after a wireless communication session. For example, during a wireless communication session, a user may be using input device 730 and display 728 to surf the web via a web browser embedded within memory 732 of portable communication device 700 .

Referring to FIG. 8 , an exemplary non-limiting embodiment of a wireless telephone is shown and generally designated 800 . As shown, wireless telephone 800 includes a system-on-chip 822 that includes a digital baseband processor 810 and an analog baseband processor 826 coupled together. Wireless telephone 800 may alternatively contain a general-purpose processor adapted to execute processor-readable instructions for performing digital or analog signal processing, among other operations. In certain embodiments, a general purpose processor (not shown) may be included in addition to digital baseband processor 810 and analog baseband processor 826 for executing processor readable instructions. As illustrated in FIG. 8 , display controller 828 and touch screen controller 830 are coupled to digital baseband processor 810 . Also, a touch screen display 832 external to system on chip 822 is coupled to display controller 828 and touch screen controller 830 . In particular embodiments, digital baseband processor 810, analog baseband processor 826, display controller 828, touch screen controller 830, other components, or any combination thereof may receive power from a power manager integrated circuit (PMIC) 857, which PMIC 857 is, for example, the PMIC device shown in FIGS. 1-6 and described herein.

FIG. 8 further indicates that a video encoder 834 (e.g., a Phase Alternating Line (PAL) encoder, a Sequential Transfer and Stored Color Television System (SECAM) encoder, or a National Television Systems Committee (NTSC) encoder) is coupled to a digital baseband processor 810. Additionally, video amplifier 836 is coupled to video encoder 834 and touch screen display 832 . Additionally, video port 838 is coupled to video amplifier 836 . As depicted in FIG. 8 , a universal serial bus (USB) controller 840 is coupled to the digital baseband processor 810 . Additionally, USB port 842 is coupled to USB controller 840 . A memory 844 and a Subscriber Identity Module (SIM) card 846 may also be coupled to the digital baseband processor 810 . Additionally, as shown in FIG. 8 , a digital camera 848 may be coupled to a digital baseband processor 810 . In the exemplary embodiment, digital camera 848 is a charge coupled device (CCD) camera or a complementary metal oxide semiconductor (CMOS) camera.

As further illustrated in FIG. 8 , a stereo audio codec 850 may be coupled to an analog baseband processor 826 . Additionally, audio amplifier 852 may be coupled to stereo audio codec 880 . In the exemplary embodiment, first stereo speakers 854 and second stereo speakers 856 are coupled to audio amplifier 852 . FIG. 8 shows that a microphone amplifier 858 may also be coupled to a stereo audio codec 850 . Additionally, a microphone 860 may be coupled to a microphone amplifier 858 . In a particular embodiment, a frequency modulation (FM) radio tuner 862 may be coupled to the stereo audio codec 850 . Additionally, an FM antenna 864 is coupled to an FM radio tuner 862 . Additionally, stereo headphones 866 may be coupled to stereo audio codec 850 .

FIG. 8 further indicates that a radio frequency (RF) transceiver 868 may be coupled to the analog baseband processor 826 . RF switch 870 may be coupled to RF transceiver 868 and RF antenna 872 . As shown in FIG. 8 , keypad 874 may be coupled to analog baseband processor 826 . Additionally, a mono headset with a microphone 876 may be coupled to the analog baseband processor 826 . Additionally, a vibrator device 878 may be coupled to the analog baseband processor 826 . FIG. 8 also shows that a power supply 880 can be coupled to the system on chip 822 . In particular embodiments, the power supply 880 is a direct current (DC) power supply that provides power to the various components of the radiotelephone 800 that require power. Furthermore, in certain embodiments, the power supply is a rechargeable DC battery or a DC power supply derived from an AC to DC converter connected to an alternating current (AC) power source. PMIC 857 may be coupled to power supply 880 to receive an unregulated power supply, which PMIC 857 may utilize to generate a regulated power supply. PMIC 857 may provide a regulated power supply to one or more power domains of an integrated circuit device, which may include one or more elements (e.g., display controller 828, digital signal processor 810, USB controller 840, Touch screen controller 830, video amplifier 836, PAL/SECAM/NTSC encoder 834, memory 844, SIM card 846, audio amplifier 852, microphone amplifier 858, FM radio tuner 862, stereo audio codec 850, analog baseband processor 826 and RF Transceiver 868). A power domain of an integrated circuit device may include one or more of these elements. The power control unit 857 may selectively activate power to one or more of the power domains, as described above with respect to FIGS. 1-6.

In a particular embodiment, as depicted in FIG. 8, touch screen display 832, video port 838, USB port 842, camera 848, first stereo speaker 854, second stereo speaker 856, microphone 860, FM antenna 864, stereo headset Headphone 866 , RF switch 870 , RF antenna 872 , keypad 874 , mono headset 876 , vibrator 878 , and power supply 880 are external to system on chip 822 .

Referring to FIG. 9 , an exemplary, non-limiting embodiment of a wireless Internet Protocol (IP) phone is shown and generally designated 900 . As shown, a wireless IP phone 900 includes a system-on-chip 902 that includes a processing unit 904 . The processing unit 904 may be a digital signal processor, a general purpose processor, an Advanced Reduced Instruction Set Computing machine processor, an analog signal processor, a processor for executing a set of processor-readable instructions, or any combination thereof. As illustrated in FIG. 9 , display controller 906 is coupled to processing unit 904 and display 908 is coupled to display controller 906 . In a particular embodiment, display 908 is a liquid crystal display (LCD). A keypad 910 may be coupled to the processing unit 904 . In particular embodiments, the processing unit 904, the display controller 906, other components, or any combination thereof may receive power via a power manager integrated circuit (PMIC) 957 (such as the PMIC shown in FIGS. 1-6 and described herein). .

As further depicted in FIG. 9 , flash memory 912 may be coupled to processing unit 904 . Synchronous Dynamic Random Access Memory (SDRAM) 914 , Static Random Access Memory (SRAM) 916 , and Electrically Erasable Programmable Read Only Memory (EEPROM) 918 are also coupled to processing unit 904 . FIG. 9 also shows that light emitting diodes (LEDs) 920 may be coupled to processing unit 904 . Additionally, in particular embodiments, a speech codec 922 may be coupled to the processing unit 904 . Amplifier 924 may be coupled to speech codec 922 and mono speaker 926 may be coupled to amplifier 924 . FIG. 9 further indicates that a mono headset 928 may also be coupled to the speech codec 922 . In a particular embodiment, mono headset 928 includes a microphone.

FIG. 9 also illustrates that a wireless local area network (WLAN) baseband processor 930 may be coupled to the processing unit 904 . RF transceiver 932 may be coupled to WLAN baseband processor 930 and RF antenna 934 may be coupled to RF transceiver 932 . In a particular embodiment, a Bluetooth controller 936 may also be coupled to the processing unit 904 and a Bluetooth antenna 938 may be coupled to the controller 936 . A USB port 940 may be coupled to the processing unit 904 . Additionally, a power supply 942 is coupled to the system on chip 902 and provides power to the various components of the wireless IP phone 900 via the PMIC 957 .

In a particular embodiment, as indicated in FIG. 9 , display 908, keypad 910, LED 920, mono speaker 926, mono headset 928, RF antenna 934, Bluetooth antenna 938, USB port 940, and power supply 942 is external to system on chip 902 . However, each of these components is coupled to one or more components of system on chip 902 . Wireless VoIP device 900 includes PMIC 957, which can be coupled to power supply 942 to receive an unregulated power supply, which PMIC 957 can utilize to generate a regulated power supply. If the system on chip 902 includes multiple power domains, the PMIC 957 may selectively provide a regulated power supply to one or more of the multiple power domains of the system on chip. The power domain of system on chip 902 may include one or more elements such as display controller 906, amplifier 924, voice codec 922, processing unit 904, flash memory 912, SDRAM 914, SRAM 916, EEPROM 918, RF transceiver 932, WLAN MAC baseband processor 930 and Bluetooth controller 936 . The power control unit 957 may selectively activate power to one or more of the power domains, as described above with respect to FIGS. 1-6 .

FIG. 10 illustrates an exemplary, non-limiting embodiment of a portable digital assistant (PDA), generally designated 1000 . As shown, PDA 1000 includes a system on chip 1002 that includes a processing unit 1004 . As depicted in FIG. 10 , touch screen controller 1006 and display controller 1008 are coupled to processing unit 1004 . Additionally, touch screen display 1010 is coupled to touch screen controller 1006 and display controller 1008 . FIG. 10 also indicates that a keypad 1012 may be coupled to the processing unit 1004 . In particular embodiments, the processing unit 1004, touch screen controller 1006, display controller 1008, other components, or any combination thereof may receive power via a power manager integrated circuit (PMIC) 1057, as shown in FIGS. as described in this article.

As further depicted in FIG. 10 , flash memory 1014 may be coupled to processing unit 1004 . The processing unit 1004 may be a digital signal processor (DSP), a general purpose processor, an advanced RISC computing machine, an analog signal processor, a processor adapted to execute a set of processor-readable instructions, or any combination thereof. Furthermore, a read only memory (ROM) 1016 , a dynamic random access memory (DRAM) 1018 , and an electrically erasable programmable read only memory (EEPROM) 1020 may be coupled to the processing unit 1004 . FIG. 10 also shows that an Infrared Data Association (IrDA) port 1022 may be coupled to processing unit 1004 . Additionally, in particular embodiments, a digital camera 1024 may be coupled to the processing unit 1004 .

As shown in FIG. 10 , in a particular embodiment, a stereo audio codec 1026 may be coupled to the processing unit 1004 . A first stereo amplifier 1028 may be coupled to the stereo audio codec 1026 and a first stereo speaker 1030 may be coupled to the first stereo amplifier 1028 . Additionally, a microphone amplifier 1032 may be coupled to the stereo audio codec 1026 and a microphone 1034 may be coupled to the microphone amplifier 1032 . FIG. 10 further shows that the second stereo amplifier 1036 can be coupled to the stereo audio codec 1026 and the second stereo speaker 1038 . In particular embodiments, stereo headphones 1040 may also be coupled to stereo audio codec 1026 .

10 also illustrates that an 802.11 controller 1042 can be coupled to the processing unit 1004 and that an 802.11 antenna 1044 can be coupled to the 802.11 controller 1042 . Additionally, a Bluetooth controller 1046 may be coupled to the processing unit 1004 and a Bluetooth antenna 1048 may be coupled to the Bluetooth controller 1046 . As depicted in FIG. 10 , a USB controller 1050 may be coupled to the processing unit 1004 and a USB port 1052 may be coupled to the USB controller 1050 . Additionally, a smart card 1054 (eg, Multimedia Card (MMC) or Secure Digital Card (SD)) may be coupled to the processing unit 1004 . Additionally, as shown in FIG. 10 , a power supply 1056 may be coupled to the PMIC 1057 of the system on chip 1002 to provide power to the various components of the PDA 1000 .

In a particular embodiment, as indicated in FIG. 10 , display 1010, keypad 1012, IrDA port 1022, digital camera 1024, first stereo speaker 1030, microphone 1034, second stereo speaker 1038, stereo headset 1040, 802.11 antenna 1044 , Bluetooth antenna 1048 , USB port 1052 , and power supply 1056 are all external to SoC 1002 . However, each of these components is coupled to one or more components on the system-on-chip 1002 . PMIC 1057 may be coupled to power supply 1056 to receive an unregulated power supply, which PMIC 1057 may utilize to generate a regulated power supply. PMIC 1057 can provide power to one or more power domains of system-on-chip 1002, which can include one or more components (e.g., display controller 1008, touch screen controller 1006, stereo amplifier 1028, microphone amplifier 1032, stereo amplifier 1036, Processing Unit 1004, Stereo Audio Codec 1026, Flash Memory 1014, ROM 1016, DRAM 1018, EEPROM 1020, 802.11 Controller 1042, Bluetooth Controller 1046, USB Controller 1050, and Smart Card MMC SD 1054). The power domains of the system on chip 1002 may contain one or more of these elements, and the power control unit 1057 may selectively activate power to one or more of the power domains, as described above with respect to FIGS. 6 described.

The various illustrative logical blocks, configurations, modules, circuits, and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, configurations, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.

The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein may be directly implemented in hardware, implemented in a software module executed by a processor, or implemented in a combination of the two. A software module may reside in RAM memory, flash memory, ROM memory, PROM memory, EPROM memory, EEPROM memory, registers, hard disk, removable disk, CD-ROM, or any other form of storage known in the art in the media. An exemplary storage medium may be coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral with the processor. The processor and storage medium may reside in the ASIC. An ASIC may reside in a computing device or a user terminal. In the alternative, the processor and storage medium may reside as discrete components in a computing device or user terminal.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the invention. Various modifications to these disclosed embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features defined by the appended claims.

Claims (13)

1. A power manager integrated circuit comprising: a buck controller for generating a first regulated power supply; a first pin coupled to a first power domain of an integrated circuit and responsive to the buck controller to provide the first regulated power supply to the first power domain; a second pin coupled to a second power domain of the integrated circuit to provide a second regulated power supply derived from the first regulated power supply to the second power domain; a master controller to determine a mode of operation and selectively reduce or disable current flow to the second pin without reducing current to the first pin when the mode of operation includes a low power mode flow; a third pin, which is coupled to an external inductor; a first transistor comprising a first terminal of the first transistor coupled to a first voltage supply terminal, a control terminal of the first transistor coupled to the buck controller, and a third pin coupled to the second terminal of the first transistor; and a second transistor comprising a first terminal of the second transistor coupled to the third pin, a control terminal of the second transistor coupled to the buck controller, and a second voltage supply terminal coupled to the second terminal of the second transistor; Wherein the first transistor and the second transistor are responsive to the buck controller to provide power supply to the external inductor via the third pin. 2. The power manager integrated circuit of claim 1, further comprising: a third transistor comprising a first terminal of the third transistor coupled to the first pin, a control terminal of the third transistor coupled to the main controller, and a second pin coupled to The second terminal of the third transistor is responsive to the main controller to reduce current flow to the second pin in the low power mode. 3. The power manager integrated circuit of claim 2, further comprising: a fourth transistor comprising a first terminal of the fourth transistor coupled to the first pin, a control terminal of the fourth transistor coupled to the control terminal of the third transistor, and a control terminal of the fourth transistor coupled to the The second terminal of the fourth transistor is connected to the second pin, the fourth transistor is responsive to the master controller to reduce current flow to the second pin. 4. The power manager integrated circuit of claim 1, wherein the main controller reduces current flow to the second pin to a current level of less than about 100 nanoamperes. 5. The power manager integrated circuit of claim 1 , wherein the buck controller provides a first regulated power supply to the first power domain via the first pin, and a first regulated power supply via the first pin. Two pins provide a second regulated power supply to the second power domain. 6. The power manager integrated circuit of claim 1 , wherein the integrated circuit includes a plurality of power domains, and wherein the buck controller is adapted to supply power to the first power domain via the first pin providing the first regulated power supply, and the master controller being adapted to provide the second regulated power supply to the second power domain and to one or more of the plurality of power domains The other power domains provide at least one additional regulated power supply. 7. The power manager integrated circuit of claim 1, wherein the main controller is adapted to scale at least one of a current level or a voltage level to the second pin to control the The second regulated power supply of a second power domain. 8. An apparatus for power distribution control of integrated circuits, comprising: a controller coupled to a first pin of the integrated circuit to supply power to a first power domain of the integrated circuit and to a second pin of the integrated circuit to supply power to a second power domain of the integrated circuit A power domain supplies power, wherein the controller includes: A logic circuit for determining a mode of operation, wherein the logic circuit includes: A first low dropout regulator comprising an input coupled to the first pin and an output coupled to the second pin, the first low dropout regulator responding to the logic circuit to operate at a low selectively reducing current flow to the second pin without reducing current flow to the first pin during a power event, and a second low dropout regulator for providing a regulated power supply to a third power domain of the integrated circuit. 9. The apparatus of claim 8, wherein the controller limits the current flow to the second pin to a current level of less than about 100 nanoamperes during the low power event. 10. A power manager integrated circuit comprising: a buck controller to generate a first regulated power supply to a first power domain coupled to a first pin of the power manager integrated circuit and to generate a a second regulated power supply to a second power domain of a second pin; and main controller, which includes: A logic circuit for determining a mode of operation, wherein the logic circuit includes: a first low dropout regulator including an input coupled to the first pin and an output coupled to the second pin, the low dropout regulator responding to the logic circuit to operate during a low power event selectively reducing current flow from the buck controller to the second pin during the low power event without reducing current flow to the first pin, and A second low dropout regulator for providing a third regulated power supply to a third power domain coupled to the power manager integrated circuit. 11. The power manager integrated circuit of claim 10, wherein said main controller limits said current flow from said buck controller to said second pin during said low power event to A current level of less than about 100 nanoamperes. 12. A system for power distribution control of an integrated circuit comprising: means for selectively reducing current flow to a second pin of said integrated circuit without reducing current flow to a first pin of said integrated circuit depending on a mode of operation, wherein said means for selectively Devices that reduce the flow of electricity include: A logic circuit for determining an operation mode, wherein the logic circuit includes: a first low dropout regulator including an input coupled to the first pin and an output coupled to the second pin, the said first low dropout regulator is responsive to said logic circuit to selectively reduce said current flow to said second pin during a low power event, and A second low dropout regulator for providing a regulated power supply to a third power domain of the integrated circuit, wherein a first pin is coupled to the first power domain of the integrated circuit and a second pin is coupled to to the second power domain of the integrated circuit. 13. The system of claim 12, further comprising a buck regulator to supply a first regulated power supply to the first pin and to provide pin, wherein the current flow to the second pin is derived from the first regulated power supply.