CN103235631A

CN103235631A - Voltage stabilizer circuit

Info

Publication number: CN103235631A
Application number: CN2013101290736A
Authority: CN
Inventors: 李兆桂
Original assignee: WUXI PUYA SEMICONDUCTOR CO Ltd
Current assignee: Praran semiconductor (Shanghai) Co., Ltd
Priority date: 2013-04-15
Filing date: 2013-04-15
Publication date: 2013-08-07
Anticipated expiration: 2033-04-15
Also published as: CN103235631B

Abstract

The invention relates to the technical field of simulation power supplies, in particular to a voltage stabilizer circuit which is simple in structure and small in area and greatly reduces cost. The voltage stabilizer circuit comprises a power supply Voltage Drain Drain (VDD) and a resistor R1 and is characterized by further comprising a first clamping circuit, a second clamping circuit and a first N-channel Metal Oxide Semiconductor (NMOS) tube. The first clamping circuit comprises a second NMOS tube and a resistor R2. The drain end of the second NMOS tube is connected with the grid end of the first NMOS tube and one end of the resistor R2 respectively, and the grid end of the second NMOS tube is connected with the other end of the resistor R2 and one end of the resistor R1 respectively. The other end of the resistor R1 is connected with the power supply VDD and the drain end of the first NMOS tube. The source end of the first NMOS tube is connected with the voltage output end. The second clamping circuit comprises an NMOS tube with the grid end connected with the drain end. The source end of the second NMOS tube is connected with the drain end of the NMOS tube, and the source end of the NMOS tube is grounded.

Description

A kind of voltage-stabiliser circuit

Technical field

The present invention relates to the analog power technical field, be specially a kind of voltage-stabiliser circuit.

Background technology

In general open-loop voltage stabilizing circuit, often adopt the PMOS pipe as driving circuit, as shown in Figure 1, under the situation that drives same current, its circuit area is more than 2.5 times of NMOS pipe, simultaneously in surpassing the high-voltage applications more than the 12V, must need to use device and the technology of back grid sample, thereby cause further increase and the workpiece of area more complicated, simultaneously, when adopting the PMOS pipe, also need to include reference voltage source and error amplifier in the circuit, the entire circuit area is big, complex structure, cost of manufacture height.

Summary of the invention

In order to address the above problem, the invention provides a kind of voltage-stabiliser circuit, its circuit structure is simple, and area is little, and cost reduces greatly.

Its technical scheme is such: a kind of voltage-stabiliser circuit, it comprises power vd D, resistance R 1, it is characterized in that, it also comprises first clamping circuit, second clamping circuit, the one NMOS pipe, described first clamping circuit comprises the 2nd NMOS pipe and resistance R 2, the drain terminal of described the 2nd NMOS pipe connects grid end and described resistance R 2 one ends of a NMOS pipe respectively, the grid end connects described resistance R 2 other ends and described resistance R 1 one ends respectively, described resistance R 1 other end connects the drain terminal of described power vd D and a described NMOS pipe respectively, the source end of a described NMOS pipe connects voltage output end, described second clamping circuit comprises the NMOS pipe that the grid end links to each other with drain terminal, the source end of described the 2nd NMOS pipe connects the drain terminal of described NMOS pipe, the source end ground connection of described NMOS pipe.

It is further characterized in that, also comprise the PMOS pipe between the NMOS pipe of described second clamping circuit and the 2nd NMOS pipe of described first clamping circuit, the grid end of described PMOS pipe links to each other with drain terminal, the source end of described PMOS pipe links to each other with the source end of described the 2nd NMOS pipe, the drain terminal of the NMOS pipe in drain terminal and described second clamping circuit links to each other the source end ground connection of described NMOS pipe; Can comprise the series connection of a plurality of described PMOS pipe in described second clamping circuit; Can comprise the series connection of a plurality of described NMOS pipe in described second clamping circuit; Described second clamping circuit comprises the 3rd, the 4th PMOS pipe of two series connection, the the 5th, the 6th, the 7th, the 8th NMOS pipe of four series connection, the source end of described the 3rd PMOS pipe links to each other with the source end of described the 2nd NMOS pipe, the drain terminal of described the 4th PMOS pipe links to each other with the drain terminal of described the 5th NMOS pipe, the source end ground connection of described the 8th NMOS pipe; NMOS pipe, the PMOS pipe of described second clamping circuit mostly are ten series connection respectively most.

After adopting structure of the present invention, include only NMOS pipe, first clamping circuit and second clamping circuit in the circuit, need not reference voltage source and error amplifier after adopting the NMOS pipe, reduced the area of circuit, circuit of the present invention can be used in a wideer voltage range simultaneously, and when surpassing the high-voltage applications of 12V, having overcome needs to use the device of back grid sample and the defective of technology in the prior art, further reduced area and simplified circuit structure simultaneously, cost reduces greatly.

Description of drawings

Fig. 1 is prior art circuits figure;

Fig. 2 is the first embodiment of the invention circuit diagram;

Fig. 3 is the second embodiment of the invention circuit diagram.

Embodiment

See shown in Figure 2, a kind of voltage-stabiliser circuit, it comprises power vd D, resistance R 1, it also comprises first clamping circuit, second clamping circuit, the one NMOS manages MN1, first clamping circuit comprises the 2nd NMOS pipe MN2 and resistance R 2, the drain terminal of the 2nd NMOS pipe MN2 connects grid end and resistance R 2 one ends of NMOS pipe MN1 respectively, the grid end connects resistance R 2 other ends and resistance R 1 one ends respectively, resistance R 1 other end connects the drain terminal of power vd D and NMOS pipe MN1 respectively, the source end of the one NMOS pipe MN1 connects voltage output end Vout, second clamping circuit comprises the 5th NMOS pipe MN5 that the grid end links to each other with drain terminal, the source end of the 2nd NMOS pipe MN2 connects the drain terminal of the 5th NMOS pipe MN5, the source end ground connection GND of the 5th NMOS pipe MN5.

Also comprise the PMOS pipe between the 2nd NMOS pipe MN2 of the 5th NMOS pipe MN5 of second clamping circuit and first clamping circuit, the grid end of PMOS pipe links to each other with drain terminal, the source end of the source end of PMOS pipe and the 2nd NMOS pipe MN2 links to each other, drain terminal links to each other with the drain terminal that the 5th NMOS in second clamping circuit manages MN5, the series connection of a plurality of PMOS pipe can be comprised in second clamping circuit, the series connection of a plurality of NMOS pipe can be comprised in second clamping circuit.See shown in Figure 3, also comprise between the 2nd NMOS pipe MN2 of the 5th NMOS of second clamping circuit pipe MN5 and first clamping circuit be connected in series the 3rd, the 4th PMOS manages MP3, MP4, the 3rd, the 4th PMOS manages MP3, the grid end of MP4 links to each other with drain terminal, the source end of the 3rd PMOS pipe MP3 links to each other with the source end of the 2nd NMOS pipe MN2, the drain terminal of the 4th PMOS pipe MP4 links to each other with the drain terminal of the 5th NMOS pipe MN5, the drain terminal series connection of the 5th NMOS pipe MN5 is connected in series the 6th successively, the 7th, the 8th NMOS manages MN6, MN7, MN8, the source end ground connection GND of the 8th NMOS pipe MN8, can obtain more stable output voltage this moment; The NMOS of second clamping circuit pipe, PMOS pipe mostly are ten series connection respectively most, and a plurality of NMOS pipes of series connection or PMOS pipe can increase the stability of circuit in second clamping circuit, make circuit area excessive but connect easily when too much, and circuit structure is complicated.

Claims

1. voltage-stabiliser circuit, it comprises power vd D, resistance R 1, it is characterized in that, it also comprises first clamping circuit, second clamping circuit, the one NMOS pipe, described first clamping circuit comprises the 2nd NMOS pipe and resistance R 2, the drain terminal of described the 2nd NMOS pipe connects grid end and described resistance R 2 one ends of a NMOS pipe respectively, the grid end connects described resistance R 2 other ends and described resistance R 1 one ends respectively, described resistance R 1 other end connects the drain terminal of described power vd D and a described NMOS pipe respectively, the source end of a described NMOS pipe connects voltage output end, described second clamping circuit comprises the NMOS pipe that the grid end links to each other with drain terminal, the source end of described the 2nd NMOS pipe connects the drain terminal of described NMOS pipe, the source end ground connection of described NMOS pipe.

2. a kind of voltage-stabiliser circuit according to claim 1, it is characterized in that, also comprise the PMOS pipe between the NMOS pipe of described second clamping circuit and the 2nd NMOS pipe of described first clamping circuit, the grid end of described PMOS pipe links to each other with drain terminal, the source end of described PMOS pipe links to each other with the source end of described the 2nd NMOS pipe, the drain terminal of the NMOS pipe in drain terminal and described second clamping circuit links to each other the source end ground connection of described NMOS pipe.

3. a kind of voltage-stabiliser circuit according to claim 2 is characterized in that, can comprise the series connection of a plurality of described PMOS pipe in described second clamping circuit.

4. a kind of voltage-stabiliser circuit according to claim 3 is characterized in that, can comprise the series connection of a plurality of described NMOS pipe in described second clamping circuit.

5. a kind of voltage-stabiliser circuit according to claim 4, it is characterized in that, described second clamping circuit comprises the 3rd, the 4th PMOS pipe of two series connection, the the 5th, the 6th, the 7th, the 8th NMOS pipe of four series connection, the source end of described the 3rd PMOS pipe links to each other with the source end of described the 2nd NMOS pipe, the drain terminal of described the 4th PMOS pipe links to each other with the drain terminal of described the 5th NMOS pipe, the source end ground connection of described the 8th NMOS pipe.

6. a kind of voltage-stabiliser circuit according to claim 4 is characterized in that, NMOS pipe, the PMOS pipe of described second clamping circuit mostly are ten series connection respectively most.