CN103258495B - Shifting deposit unit, shift register and display device - Google Patents

Abstract

The present invention provides a shift register unit, which includes a drive signal input terminal, a drive signal output terminal, a first clock signal input terminal, a second clock signal input terminal, a drive transistor and an output pull-down transistor, wherein the The gate of the output pull-down transistor is connected to the second clock signal input end, the low level input by the drive signal input end is the first low level, and the source electrode of the output pull-down transistor is connected to the first low level The output terminal is connected, the low levels input by the first clock signal input terminal and the second clock signal input terminal are both the second low level, and the difference between the first low level and the second low level The value is greater than the absolute value of the threshold voltage of the output pull-down transistor, enabling the pull-down transistor to be turned off during the evaluation phase. The invention also provides a shift register and a display device. A depletion-type thin film transistor can be used in the shift register unit provided by the present invention.

Description

Shift register unit, shift register and display device

technical field

The present invention relates to the field of organic light-emitting display, in particular to a shift register unit, a shift register including the shift register unit, and a display device including the shift register.

Background technique

With the development of flat panel display, high resolution and narrow bezel have become the trend of development, and integrating gate drive circuits on the display panel is the most important solution to realize high resolution and narrow bezel display.

What shown in Fig. 1 is the circuit diagram of existing basic shift register unit, as shown in Fig. 1, this basic shift register unit comprises drive transistor T1, output pull-down transistor T2, reset transistor T9, bootstrap capacitor 20 , a storage capacitor 30 , a first clock signal input terminal CK, a second clock signal input terminal CKB, a drive signal input terminal OUT(n−1), a reset terminal Reset and a drive signal output terminal OUT(n).

In FIG. 1 , the pull-up node PU is a node connected to the gate of the drive transistor T1 , and the pull-down node PD is a node connected to the gate of the output pull-down transistor T2 . The start signal STV is input from the drive signal input terminal OUT(n-1), and VGL is at low level. What is shown in FIG. 2 is the timing diagram of each signal when the shift register unit in FIG. 1 is working, and VGH is high level.

Thin film transistors made of a-si (amorphous silicon) and p-si (polysilicon) are enhancement-type thin-film transistors. The bit register unit can work normally (shown by the solid line in Figure 2).

In recent years, oxide thin film transistors, as a very potential semiconductor technology, are simpler and cheaper than p-si processes, and have higher mobility than a-si, so they are getting more and more attention. In the future It is likely to be OLED, the mainstream backplane driving technology for flexible displays. However, the oxide thin film transistor has the characteristics of depletion mode (see Figure 3 and Figure 4 for the difference with the enhancement mode thin film transistor, and Figure 3 is the characteristic curve of the enhancement mode thin film transistor). The vertical axis is the current of the drain of the thin film transistor, and the horizontal axis is is the gate-source voltage. It can be seen from the characteristic curve of the enhanced thin film transistor shown in Figure 3 that when the Vgs (gate-source voltage) voltage is zero, id (drain current) is zero, indicating that Vgs When it is zero, the enhancement mode thin film transistor is completely turned off; as can be seen from the characteristic curve diagram of the depletion mode thin film transistor in Figure 4, the vertical axis is also the drain current, and the horizontal axis is the gate-source voltage, but When Vgs is zero, id is much greater than zero, and only when the gate-source voltage is a certain negative voltage, id is zero.

As shown by the dotted line in FIG. 2, when the depletion-type thin film transistor is applied to the circuit shown in FIG. 1, it cannot work normally.

Contents of the invention

The purpose of the present invention is to provide a shift register unit, a shift register comprising the shift register unit and a display device comprising the shift register, in which a depletion-type thin film can be used transistor.

In order to achieve the above object, as an aspect of the present invention, a shift register unit is provided, the shift register unit includes a drive signal input terminal, a drive signal output terminal, a first clock signal input terminal, a second clock signal input terminal, A drive transistor and an output pull-down transistor, wherein the gate of the output pull-down transistor is connected to the second clock signal input end, the low level input by the drive signal input end is the first low level, and the output pull-down The source of the transistor is connected to the first low level output terminal, the low levels input by the first clock signal input terminal and the second clock signal input terminal are both the second low level, and the first low level The difference from the second low level is greater than the absolute value of the threshold voltage of the pull-down transistor, so that the pull-down transistor can be turned off during the evaluation phase.

Preferably, the gate of the driving transistor is formed as a pull-up node, and the shift register unit further includes a switch unit connected to the pull-up node, and the switch unit can connect the pull-up node to Conducting with the drive signal input terminal to charge a capacitor connected in parallel with the drive transistor, and the switch unit can disconnect the pull-up node from the drive signal input terminal during the evaluation phase to prevent The pull-up node leaks current.

Preferably, the switch unit includes a first switch transistor and a second switch transistor, the gate of the first switch transistor is connected to the second clock signal input terminal, and the drain of the first switch transistor is connected to the The drive signal input terminal is connected, the source of the first switch transistor is connected to the drain of the second switch transistor, the gate of the second switch transistor is connected to the drive signal input terminal, and the second switch transistor The source of the transistor is connected to the pull-up node.

Preferably, the shift register unit includes a pull-down unit and a pull-down transistor, the gate of the pull-down transistor is connected to the pull-down unit, the source of the pull-down transistor is connected to the second low-level output terminal, and the pull-down transistor The unit can turn off the pull-down transistor during the evaluation phase, and turn on the pull-down transistor during the reset phase and the non-operation phase, so that the pull-down transistor can turn the pull-up transistor on during the reset phase and the non-operation phase The level of the node is pulled down to the second low level.

Preferably, the pull-down unit includes a first pull-down control transistor and a second pull-down control transistor, the gate of the first pull-down control transistor is connected to the pull-up node, and the source of the first pull-down control transistor The pole is connected to the third low level output end, the gate of the second pull-down control transistor is connected to the second clock signal input end, the drain of the first pull-down control transistor is connected to the gate of the pull-down transistor The drain of the second pull-down control transistor is connected to the high-level output terminal, the source of the second pull-down control transistor is connected to the gate of the pull-down transistor, and the second low level is connected to the gate of the pull-down transistor. The difference of the third low level is greater than the threshold voltage of the pull-down transistor.

Preferably, the pull-down unit further includes a third pull-down control transistor, the gate of the third pull-down control transistor is connected to the first clock signal input terminal, and the source of the third pull-down control transistor is connected to the third The low level output terminals are connected, and the drain of the third pull-down control transistor is connected with the source of the second pull-down control transistor.

Preferably, the drive transistor, the output pull-down transistor, the first switch transistor, the second switch transistor, the pull-down transistor, the first pull-down control transistor, the second pull-down control transistor and At least one of the third pull-down control transistors is a depletion transistor.

As another aspect of the present invention, a shift register is provided, which includes a multi-stage shift register unit, wherein the shift register unit is the above-mentioned shift register unit provided by the present invention, and the next stage The drive signal input end of the shift register unit is connected to the drive signal output end of the upper stage shift register unit.

As yet another aspect of the present invention, a display device is provided, wherein the display device includes the above-mentioned shift register provided by the present invention.

In the shift register unit provided by the present invention, the second clock signal input terminal is connected to the gate of the output pull-down transistor, and the source of the output pull-down transistor is connected to the first low-level input terminal that can output the first low level connected. Since the low level input by the second clock signal input terminal in the evaluation phase is the second low level, and the difference between the second low level and the first low level is greater than the threshold voltage of the pull-down transistor, the first low level can be used The second clock signal input directly controls the pull-down transistor to be fully turned off during the evaluation phase. Since the difference between the second low level and the first low level is greater than the critical voltage of the pull-down transistor, even if the pull-down transistor is a depletion transistor, the pull-down transistor can still be completely turned off during the evaluation phase.

Description of drawings

The accompanying drawings are used to provide a further understanding of the present invention, and constitute a part of the description, together with the following specific embodiments, are used to explain the present invention, but do not constitute a limitation to the present invention. In the attached picture:

Fig. 1 is the circuit diagram of existing basic shift register unit;

Fig. 2 is the timing diagram of each signal when the shift register unit shown in Fig. 1 works;

Fig. 3 is a characteristic curve diagram of an enhancement transistor;

Fig. 4 is a characteristic curve diagram of a depletion mode transistor;

Fig. 5 is a circuit diagram of an embodiment of the shift register unit provided by the present invention;

Fig. 6 is a circuit diagram of another embodiment of the shift register unit provided by the present invention;

FIG. 7 is a timing diagram of various signals during operation of the shift register unit shown in FIG. 6 .

Explanation of reference signs

T1: Drive transistor T2: Output pull-down transistor

T3: The second pull-down control transistor T4: The third pull-down control transistor

T5: the first pull-down control transistor T6: pull-down transistor

T7: Second switching transistor T8: First switching transistor

CK: first clock signal input terminal PU: pull-up node

PD: pull-down node 11: switch unit

12: Pull-down unit 20: Bootstrap capacitor

30: storage capacitor CKB: second clock signal input terminal

VGH: High level VGL: Low level

VGL1: the first low level VGL2: the second low level

VGL3: third low level T9: reset transistor

OUT(n-1): drive signal input terminal

OUT(n): drive signal output terminal

Detailed ways

Specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings. It should be understood that the specific embodiments described here are only used to illustrate and explain the present invention, and are not intended to limit the present invention.

As shown in FIG. 5 and FIG. 6, as an aspect of the present invention, a shift register unit is provided, and the shift register unit includes a drive signal input terminal OUT(n-1), a drive signal output terminal OUT(n), The first clock signal input terminal CK, the second clock signal input terminal CKB, the drive transistor T1 and the output pull-down transistor T2, wherein the gate of the output pull-down transistor T2 is connected to the second clock signal input terminal CKB, and the drive signal input terminal OUT( n-1) The input low level is the first low level VGL1, and the source of the output pull-down transistor T2 is connected to the first low-level output terminal (the first low-level output terminal can be output to the source of the output pull-down transistor T2 The first low level VGL1) is connected, the low levels input by the first clock signal input terminal CK and the second clock signal input terminal CKB are both the second low level VGL2, the first low level VGL1 and the second low level VGL2 The difference of V is greater than the absolute value of the threshold voltage (ie, threshold voltage) of the output pull-down transistor T2 (ie, VGL1-VGL2>|Vtht2|), so that the output pull-down transistor T2 can be turned off during the evaluation phase.

It should be understood that, in the present invention, as shown in FIG. 7, the high-level signal input from the drive signal input terminal OUT(n-1) is a high-level VGH, and the input terminal OUT(n-1) from the drive signal The input low-level signal is the first low-level VGL1; the high-level first clock signal input from the first clock signal input terminal CK is high-level VGH, and the low-level input from the first clock signal input terminal CK is the second low level VGL2; the high level input from the second clock signal input terminal CKB is VGH, and the low level input from the second clock signal input terminal CKB is the second low level VGL2.

In the present invention, since the second clock signal input terminal CKB is directly connected to the gate of the output pull-down transistor T2, the second clock signal input from the second clock signal input terminal CKB can be used to directly control the opening and closing of the output pull-down transistor T2. closure.

In the evaluation stage of the shift register unit (that is, stage ② in Figure 7), the first clock signal input terminal CK inputs the first clock signal with a high level VGH, and the second clock signal input terminal CKB inputs the second clock signal is the second low level VGL2, the signal input by the drive signal input terminal OUT(n-1) is the first low level VGL1, the gate level of the output pull-down transistor T2 is the second low level VGL2, and the output pull-down transistor T2 The source level of VGL1 is the first low level VGL1, because VGL1-VGL2>|V _thT2 |, therefore, in the evaluation stage, even if the output pull-down transistor T2 is a depletion transistor, the output pull-down transistor T2 can still be normally turned off , no leakage will occur.

Generally, the node connected to the gate of the drive transistor T1 is called a pull-up node (that is, the gate of the drive transistor T1 is formed as a pull-up node PU), and the potential of the pull-up node PU is the same as that of the gate of the drive transistor T1. Potential is the same.

In order to ensure that the shift register unit provided by the present invention can output a square wave with sufficient pulse width, preferably, as shown in Figure 5 and Figure 6, the shift register unit can also include a switch connected to the pull-up node PU Unit 11, the switch unit 11 can conduct the pull-up node PU and the driving signal input terminal OUT(n-1) in the pre-charging phase (that is, phase ① in FIG. charging, and the switch unit 11 can disconnect the pull-up node PU from the drive signal input terminal OUT(n-1) during the evaluation stage (ie, stage ② in FIG. 7 ), so as to prevent the pull-up node PU from leakage.

In the pre-charging stage, the switch unit 11 conducts the pull-up node PU and the drive signal input terminal OUT(n-1), so that the drive signal input terminal OUT(n-1) can charge the capacitor C normally, so that the pull-up node PU The voltage of PU rises rapidly; and in the evaluation phase, the second clock signal input terminal CKB inputs the second low level VGL2 to turn off the output pull-down transistor T2, and the first clock signal input terminal CK inputs high level VGH, the high level The level VGH drives the transistor T1 to couple the pull-up node PU to a higher potential through the capacitor C, and the switch unit 11 disconnects the pull-up node PU from the drive signal input terminal OUT(n-1) to prevent the pull-up node PU from leaking , so that an output signal with sufficient pulse width can be obtained at the drive signal output terminal OUT(n).

In the present invention, the switch unit 11 can have various forms, as long as the pull-up node PU and the drive signal input terminal OUT(n-1) can be turned on during the pre-charging stage, so that the capacitor C connected in parallel with the drive transistor T1 Charging, and the switch unit 11 may disconnect the pull-up node PU from the drive signal input terminal OUT(n-1) in the evaluation stage to prevent the pull-up node PU from leaking.

As a preferred embodiment of the present invention, as shown in Figure 5 and Figure 6, the switch unit 11 may include a first switch transistor T8 and a second switch transistor T7, the gate of the first switch transistor T8 is connected to the second clock signal input Terminal CKB is connected, the drain of the first switching transistor T8 is connected with the drive signal input terminal OUT (n-1), the source of the first switching transistor T8 is connected with the drain of the second switching transistor T7, and the drain of the second switching transistor T7 The gate is connected to the driving signal input terminal OUT(n-1), and the source of the second switching transistor T7 is connected to the pull-up node PU.

In the pre-charging stage (that is, stage ① in Figure 7), the signal input to the drive signal input terminal OUT(n-1) is a high level VGH, and the first clock signal input to the first clock signal input terminal CK is the second Low level VGL2, the second clock signal input from the second clock signal input terminal CKB is high level VGH. Since the gate of the first switch transistor T8 is connected to the second clock signal input terminal CKB, and the gate of the second switch transistor T7 is connected to the drive signal input terminal OUT(n-1), therefore, the first switch transistor T8 and the second The open transistors T7 are all turned on, the driving signal input terminal OUT(n-1) can charge the capacitor C through the first switching transistor T8 and the second switching transistor T7, and the voltage at the pull-up node PU will rise rapidly.

In the evaluation stage (that is, stage ② in Figure 7), the signal input to the drive signal input terminal OUT(n-1) is the first low level VGL1, and the second clock signal input to the second clock signal input terminal CKB is The second low level VGL2, therefore, both the first switching transistor T8 and the second switching transistor T7 are turned off. Since the first switch transistor T8 and the second switch transistor T7 are turned off, the first clock signal input to the first clock signal input terminal CK is a high level VGH, at this time the first clock signal can pull up the node PU The potential is coupled to a higher potential through capacitance C without leakage.

It should be noted that, if the first switching transistor T8 and the second switching transistor T7 are depletion transistors, the difference between the first low level VGL1 and the second low level VGL2 is greater than the threshold voltage of the first switching transistor T8 The absolute value (ie, VGL1 - VGL2 > |V _tht8 |) to ensure that the first switching transistor T8 can be normally turned off during the evaluation stage.

In order to make the signal output by the shift register unit more stable, preferably, the shift control unit may further include a pull-down unit 12 and a pull-down transistor T6, the gate of the pull-down transistor T6 is connected to the pull-down unit 12, and the gate of the pull-down transistor T6 The source is connected to the second low-level output terminal (the second low-level output terminal can output the second low-level VGL2 to the source of the pull-down transistor T6), and the pull-down unit 12 can be in the evaluation stage (that is, in FIG. 7 The pull-down transistor T6 is turned off in the stage ②, and the pull-down transistor T6 is turned on in the reset stage (that is, the stage ③ in Figure 7) and the non-working stage (that is, the part on the right side of the stage ③ in Figure 7), so that the pull-down transistor T6 T6 can pull down the level of the pull-up node PU to the second low level during the reset phase and the non-working phase.

In the evaluation stage, the pull-down transistor T6 is turned off, which can prevent the pull-up node PU from leaking. During the reset phase and the non-working phase, the pull-down transistor T6 is turned on to discharge the pull-up node PU, thereby ensuring that the driving signal output terminal OUT(n) outputs a low level during the reset phase and the non-working phase.

In the present invention, there is no special requirement on the specific structure of the pull-down unit 12, as long as the pull-down transistor T6 can be turned off during the evaluation phase, and the pull-down transistor T6 can be turned on during the reset phase and the non-working phase.

As a preferred embodiment of the present invention, as shown in FIG. 6, the pull-down unit 12 includes a first pull-down control transistor T5 and a second pull-down control transistor T3, the gate of the first pull-down control transistor T5 is connected to the pull-up node PU, The source of the first pull-down control transistor T5 is connected to the third low-level output terminal (the third low-level output terminal can output the third low-level VGL3 to the source of the first pull-down control transistor T5), and the first The drain of the pull-down transistor T5 is connected to the gate of the pull-down transistor T6, the gate of the second pull-down control transistor T3 is connected to the second clock signal input terminal CKB, and the drain of the second pull-down control transistor T3 is connected to the high-level output terminal (the high-level output terminal can output a high-level VGH to the drain of the second pull-down control transistor T3), the source of the second pull-down control transistor T3 is connected to the gate of the pull-down transistor T6, and the second low-level VGL2 is connected to the gate of the pull-down transistor T6. The difference of the third low level VGL3 is greater than the threshold voltage of the pull-down transistor T6 (ie, VGL2−VGL3>|V _thT6 |).

In the evaluation phase, the signal input by the drive signal input terminal OUT(n-1) is the first low level VGL1, the second clock signal input by the second clock signal input terminal CKB jumps to the second low level VGL2, and the second A first clock signal input from a clock signal input terminal CK jumps to a high level VGH. The output pull-down transistor T2 is turned off. Since the pull-up node PU is coupled to a higher level, the first pull-down control transistor T5 is turned on, and the second pull-down control transistor T3 is turned off, thereby pulling down the gate voltage of the pull-down transistor T6 to the third low level VGL3, Make pull-down transistor T6 completely off.

In the present invention, the gate of the pull-down transistor T6 may be referred to as a pull-down node PD. In the present invention, the second clock signal input terminal CKB directly controls the output pull-down transistor T2, so the pull-down node PD has no influence on the driving signal output terminal OUT(n).

In the reset phase, the second clock signal input by the second clock signal input terminal CKB jumps to a high level VGH, the drive signal input terminal OUT(n-1) maintains the first low level VGL1, and the first clock signal input terminal CK The input first clock signal transitions to the second low level VGL2. The output pull-down transistor T2 is turned on, the drive signal output terminal OUT(n) is pulled down to the first low level VGL1, and the voltage jump of the drive signal output terminal OUT(n) quickly pulls up the potential of the node PU through the coupling effect of the capacitor C Pull down to a potential lower than that of the evaluation stage, of course, the potential is still enough to turn on the drive transistor T1, but at this time the first clock signal input by the first clock signal input terminal CK is the second low level VGL2, and the drive signal output terminal OUT(n) has no pull-up function. As the potential of the pull-up node PU decreases, the gate potential of the first pull-down control transistor T5 also decreases, but it is still in a certain open state, but the current passing through this opening is small, and the pull-down effect on the pull-down node PD is weak. . The gate of the second pull-down control transistor T3 is the high level VGH input by the second clock signal input terminal CKB, so the second pull-down control transistor T3 is fully turned on, although the first pull-down control transistor T5 is not turned off, but due to the weakened pull-down effect , therefore, the pull-down node PD will still be pulled up to open by the high level of the second pull-down control transistor T3, so the pull-down transistor T6 is turned on, so that the potential of the pull-up node PU is quickly pulled down, and the potential of the pull-down node PD is quickly pulled down It will further turn off the first pull-down control transistor T5, and this interaction will make the potential of the pull-up node PU drop faster, so that the driving transistor T1 will be before the next high level input of the first clock signal input terminal CK, so that The potential of the pull-up node PU drops to the second low level VGL2, thereby completely turning off the driving transistor T1.

In the non-working stage, for the pull-down node PD, in addition to the pull-up level controlled by the second clock signal input terminal CKB, there is also a pull-down level controlled by the first clock signal input terminal CK. From a functional point of view, in the non-working phase of the shift register unit, the pull-down of the pull-down node PD has no meaning. In addition to increasing the pull-down capability to quickly turn off the pull-down transistor T6 during the working phase, the pull-down level is used here. Another function is that, The gate of the pull-down transistor T6, that is, the pull-down node PD, can be in an alternating voltage state, avoiding the long-term DC bias that causes the transmission curve of the pull-down transistor T6 to shift to the right and aging failure, thereby improving the use of the entire shift register unit life.

In order to ensure that the pull-down transistor T6 can be turned off more quickly during the evaluation phase, preferably, the pull-down unit 12 can also include a third pull-down control transistor T4, the gate of the third pull-down control transistor T4 is connected to the first clock signal input terminal CK , the source of the third pull-down control transistor T4 is connected to the third low-level output terminal, and the drain of the third pull-down control transistor T4 is connected to the source of the second pull-down control transistor T3.

In the shift register unit of the present invention, the driving transistor T1, the output pull-down transistor T2, the first switch transistor T8, the second switch transistor T7, the pull-down transistor T6, the first pull-down control At least one of the transistor T5, the second pull-down control transistor T3 and the third pull-down control transistor T4 is a depletion transistor.

In the following, referring to the specific implementation in FIG. 6, it will be introduced when the drive transistor T1, the output pull-down transistor T2, the first switch transistor T8, the second switch transistor T7, the pull-down transistor T6, the first pull-down control When the transistor T5 , the second pull-down control transistor T3 and the third pull-down control transistor T4 are all depletion transistors, and the threshold voltages of the transistors are equal, what are the working principles of the above transistors. Preferably, the drive transistor T1, the output pull-down transistor T2, the first switch transistor T8, the second switch transistor T7, the pull-down transistor T6, the first pull-down control transistor T5, the second pull-down control transistor T3 and the third pull-down control transistor T4 are all oxide transistors.

Pre-charging stage (that is, stage ① in Figure 7): the second clock signal input by the second clock signal input terminal CKB and the signal input by the drive signal input terminal OUT(n-1) are high level VGH, the first clock The first clock signal input to the signal input terminal CK is the second low level VGL2, so the output pull-down transistor T2, the second pull-down control transistor T3, the second switch transistor T7 and the first switch transistor T8 are turned on.

Since the source voltage of the third pull-down control transistor T4 is the third low level VGL3, and the gate voltage of the third pull-down control transistor T4 is the second low level VGL2 input from the first clock signal input terminal CK, the third The pull-down control transistor T4 is not completely turned off but has a certain leakage current.

The second switching transistor T7 and the first switching transistor T8 are turned on, the driving signal input terminal OUT(n-1) charges the capacitor C through the second switching transistor T7 and the first switching transistor T8, and the voltage of the pull-up node PU will rise rapidly , so that the first pull-down control transistor T5 is turned on, although the second pull-down control transistor T3 is also turned on, so that the high-level VGH input from the high-level input terminal has a certain pull-up effect on the pull-down node PD, but due to the third pull-down control The leakage of the transistor T4 and the turn-on of the first pull-down control transistor T5 will rapidly pull down the potential of the pull-down node PD by the third low level VGL3 .

Although the gate potential of the pull-down transistor T6 will not completely drop to the third low level VGL3 due to the joint action of the second pull-down control transistor T3, the third pull-down control transistor T4, and the second pull-down control transistor T5, it will make The leakage current of the pull-down transistor T6 is greatly reduced, so that the potential of the pull-up node PU is not pulled down excessively, so the driving transistor T1 in the pre-charging stage can still obtain sufficient turn-on potential. Therefore, in the pre-charging stage, the drive signal output terminal OUT(n) will be pulled down by the low level of the first clock signal input from the first clock signal input terminal CK, and at the same time, the turn-on of the output pull-down transistor T2 will also pull the output terminal OUT( n) potential pull-down.

Evaluation stage (that is, stage ② in Figure 7): the signal input to the drive signal input terminal OUT(n-1) is the first low level VGL1, and the second clock signal input to the second clock signal input terminal CKB jumps is the second low level VGL2, the first clock signal input from the first clock signal input terminal CK jumps to a high level VGH.

The source of the output pull-down transistor T2 is the first low level VGL1, and the gate of the output pull-down transistor T2 is the second low level VGL2 input from the second clock signal input terminal CKB, so the output pull-down transistor T2 is turned off. The source potential of the first switch transistor T8 is the first low level VGL1 input from the drive signal input terminal OUT(n-1), and the gate potential of the first switch transistor T8 is the second level of the second clock signal input terminal CKB. clock signal (ie, the second low level VGL2 ), so the first switching transistor T8 is turned off. Although the second clock signal input from the second clock signal input terminal CKB is the second low level VGL2, the second pull-down control transistor T3 is not completely turned off, but a small leakage current flows through it.

Since the first clock signal (high level VGH) output by the first clock signal input terminal CK passes through the drive transistor T1, the potential of the pull-up node PU is coupled to a higher potential through the capacitor C, so the first pull-down control transistor T5 is fully turned on, and the third pull-down control transistor T4 is also turned on at the same time. Although the second pull-down control transistor T3 is not completely turned off, the potential of the pull-down node PD will still be pulled down to the third low level VGL3, so the pull-down transistor T6 is completely turned off. This further creates conditions for the pull-up node PU to keep a high potential, and the driving transistor T1 is fully turned on so that the driving signal output terminal OUT(n) outputs a high level VGH.

Reset stage: the second clock signal input from the second clock signal input terminal CKB transitions to a high level VGH, and the signal input from the driving signal input terminal OUT(n-1) maintains the first low level VGL1. The first clock signal input to the first clock signal input terminal CK is the second low level VGL2. Thus the output pull-down transistor T2, the second pull-down control transistor T3, the second switch transistor T7 and the first switch transistor T8 are turned on.

Since the source level of the third pull-down control transistor T4 is the third low level VGL3, and the gate of the third pull-down control transistor T4 is the first clock signal input from the first clock signal input terminal CK (that is, the second low level Level VGL2), so the third pull-down control transistor T4 is not completely turned off but there is a certain leakage. Due to the turn-on of the output pull-down transistor T2, the drive signal output terminal OUT(n) is pulled down to the first low level VGL1, and the voltage jump of the drive signal output terminal OUT(n) will pull up the node PU through the coupling effect of the capacitor C. The potential is quickly pulled down to a potential lower than that in the evaluation stage. Of course, this potential is still enough to turn on the driving transistor T1, but at this time the first clock signal input terminal CK is also at a low potential, and the driving signal output terminal OUT(n) is not pulled up. effect.

Due to the decrease in the potential of the pull-up node PU, the gate potential of the first pull-down control transistor T5 also decreases, but it is still in a certain open state, but the current passing through this open is small, and the pull-down effect on the pull-down node PD is weakened. . Due to the high level VGH of the second clock signal input terminal CKB, the second pull-down control transistor T3 is fully turned on. Although the first pull-down control transistor T5 is not turned off, because the pull-down effect is weakened, the pull-down node PD will still be pulled up to open by the high level of the second pull-down control transistor T3, so that the pull-down transistor T6 is turned on, and the pull-up node PD The potential of PU is quickly pulled down, and the rapid pull-down of the pull-up node PU will further turn off the first pull-down control transistor T5. This interaction will make the potential of the pull-up node PU drop faster, so that the drive transistor T1 is in the first Before the next high level of the clock signal input terminal CK comes, the potential of the pull-up node PU drops to the second low level VGL2, thereby completely turning off the driving transistor T1.

In the shift register unit shown in Figure 6, three different low levels (the first low level VGL1, the second low level VGL2 and the third low level VGL3) are used, which can make the output pull-down transistor T2 The gate-source voltage of is negative, so that the output pull-down transistor T2 can be completely turned off during the evaluation phase. Moreover, the shift register unit can well maintain the potential of the pull-up node PU, so that the driving transistor T1 is completely turned off in the non-working stage, so that a signal with a required pulse width and a required voltage can be output.

As another aspect of the present invention, a shift register is provided, which includes a multi-stage shift register unit, wherein the shift register unit is the above-mentioned shift register unit provided by the present invention, and the next stage The drive signal input end of the shift register unit is connected to the drive signal output end of the upper stage shift register unit. In the present invention, n is a positive integer.

As yet another aspect of the present invention, a display device is also provided, wherein the display device includes the above-mentioned shift register provided by the present invention. The display device may include a liquid crystal display device, for example, a liquid crystal panel, a liquid crystal television, a mobile phone, a liquid crystal display, and the like. In addition to the liquid crystal display device, the display device may also include an organic light-emitting display or other types of display devices, such as an electronic reader. The shift register can be used as a scanning circuit or a gate driving circuit of a display device to provide a progressive scanning function and transmit scanning signals to a display area.

It can be understood that, the above embodiments are only exemplary embodiments adopted for illustrating the principle of the present invention, but the present invention is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and essence of the present invention, and these modifications and improvements are also regarded as the protection scope of the present invention.

Claims (13)

1. a shifting deposit unit, this shifting deposit unit comprises driving signal input, drive singal output terminal, first clock signal input terminal, second clock signal input part, driving transistors and output pull-down transistor, it is characterized in that, the grid of described output pull-down transistor is connected with described second clock signal input part, the low level of described driving signal input input is the first low level, the source electrode of described output pull-down transistor is connected with the first low level output end, the low level of described first clock signal input terminal and the input of described second clock signal input part is the second low level, described first low level and described second low level difference are greater than the absolute value of the critical voltage of described output pull-down transistor, described pull-down transistor can be closed in evaluate phase.

2. shifting deposit unit according to claim 1, it is characterized in that, the grid of described driving transistors is formed as pull-up node, described shifting deposit unit also comprises the switch element be connected with described pull-up node, described switch element can in pre-charging stage by described pull-up node and described driving signal input conducting, with to the capacitor charging in parallel with described driving transistors, and described pull-up node and described driving signal input can disconnect in evaluate phase by described switch element, leak electricity to prevent described pull-up node.

3. shifting deposit unit according to claim 2, it is characterized in that, described switch element comprises the first switching transistor and second switch transistor, the grid of described first switching transistor is connected with described second clock signal input part, the drain electrode of described first switching transistor is connected with described driving signal input, the source electrode of described first switching transistor is connected with the drain electrode of described second switch transistor, the grid of described second switch transistor is connected with described driving signal input, and the source electrode of described second switch transistor is connected with described pull-up node.

4. shifting deposit unit according to claim 3, it is characterized in that, described shifting deposit unit comprises drop-down unit and pull-down transistor, the grid of described pull-down transistor is connected with described drop-down unit, the source electrode of described pull-down transistor is connected with the second low level output end, described pull-down transistor can be closed in evaluate phase by described drop-down unit, and at reseting stage and non-operational phase, described pull-down transistor is opened, make described pull-down transistor at described reseting stage and described non-operational phase, the level of described pull-up node can be pulled low to described second low level.

5. shifting deposit unit according to claim 4, it is characterized in that, described drop-down unit comprises the first drop-down control transistor and the second drop-down control transistor, the grid of described first drop-down control transistor is connected with described pull-up node, the source electrode of described first drop-down control transistor is connected with the 3rd low level output end, the drain electrode of described first drop-down control transistor is connected with the grid of described pull-down transistor, the grid of described second drop-down control transistor is connected with described second clock signal input part, the drain electrode of described second drop-down control transistor is connected with high level output end, the source electrode of described second drop-down control transistor is connected with the grid of described pull-down transistor, described second low level and described 3rd low level difference are greater than the critical voltage of described pull-down transistor.

6. shifting deposit unit according to claim 5, it is characterized in that, described drop-down unit also comprises the 3rd drop-down control transistor, the grid of the 3rd drop-down control transistor is connected with described first clock signal input terminal, the source electrode of described 3rd drop-down control transistor is connected with described 3rd low level output end, and the drain electrode of described 3rd drop-down control transistor is connected with the source electrode of described second drop-down control transistor.

7. shifting deposit unit according to claim 6, it is characterized in that, at least one in described driving transistors, described output pull-down transistor, described first switching transistor, described second switch transistor, described pull-down transistor, described first drop-down control transistor, described second drop-down control transistor and described 3rd drop-down control transistor is depletion mode transistor.

8. shifting deposit unit according to claim 2, it is characterized in that, described shifting deposit unit comprises drop-down unit and pull-down transistor, the grid of described pull-down transistor is connected with described drop-down unit, the source electrode of described pull-down transistor is connected with the second low level output end, described pull-down transistor can be closed in evaluate phase by described drop-down unit, and at reseting stage and non-operational phase, described pull-down transistor is opened, make described pull-down transistor at described reseting stage and described non-operational phase, the level of described pull-up node can be pulled low to described second low level.

9. shifting deposit unit according to claim 8, it is characterized in that, described drop-down unit comprises the first drop-down control transistor and the second drop-down control transistor, the grid of described first drop-down control transistor is connected with described pull-up node, the source electrode of described first drop-down control transistor is connected with the 3rd low level output end, the drain electrode of described first drop-down control transistor is connected with the grid of described pull-down transistor, the grid of described second drop-down control transistor is connected with described second clock signal input part, the drain electrode of described second drop-down control transistor is connected with high level output end, the source electrode of described second drop-down control transistor is connected with the grid of described pull-down transistor, described second low level and described 3rd low level difference are greater than the critical voltage of described pull-down transistor.

10. shifting deposit unit according to claim 9, it is characterized in that, described drop-down unit also comprises the 3rd drop-down control transistor, the grid of the 3rd drop-down control transistor is connected with described first clock signal input terminal, the source electrode of described 3rd drop-down control transistor is connected with described 3rd low level output end, and the drain electrode of described 3rd drop-down control transistor is connected with the source electrode of described second drop-down control transistor.

11. shifting deposit units according to claim 10, it is characterized in that, at least one in described driving transistors, described output pull-down transistor, described pull-down transistor, described first drop-down control transistor, described second drop-down control transistor and described 3rd drop-down control transistor is depletion mode transistor.

12. 1 kinds of shift registers, this shift register comprises stages shift deposit unit, it is characterized in that, described shifting deposit unit is the shifting deposit unit in claim 1 to 11 described in any one, and the driving signal input of shifting deposit unit described in next stage is connected with the drive singal output terminal of shifting deposit unit described in upper level.

13. 1 kinds of display device, is characterized in that, this display device comprises shift register according to claim 12.