CN103258741A - Nanowire field effect transistor and forming method thereof - Google Patents
Nanowire field effect transistor and forming method thereof Download PDFInfo
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- CN103258741A CN103258741A CN2012100393355A CN201210039335A CN103258741A CN 103258741 A CN103258741 A CN 103258741A CN 2012100393355 A CN2012100393355 A CN 2012100393355A CN 201210039335 A CN201210039335 A CN 201210039335A CN 103258741 A CN103258741 A CN 103258741A
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Abstract
The invention provides a nanowire field effect transistor and a forming method thereof. The nanowire field effect transistor forming method includes a first step of providing an SOI substrate, wherein the SOI substrate comprises a first semiconductor substrate, a buried layer located on the first semiconductor substrate, and a second semiconductor substrate located on the buried layer, a second step of enabling the second semiconductor substrate to be graphic to form a source electrode region, a drain electrode region and nanowires, a third step of removing a part of buried layer with a certain thickness under the nanowires to form a groove and enabling the nanowires to be suspended in the groove, a fourth step of forming sidewalls on side faces of an area defined by the graphic second semiconductor substrate and the remaining buried layer, a fifth step of forming a gate structure between the sidewall of the side face of the source electrode region and the sidewall of the side face of the drain electrode region, wherein the gate structure comprises grids and a gate medium layer, and the sum of the width of the grids and the widths of the sidewalls is equal to the length of the nanowires, and a sixth step of carrying out ion doping on the source electrode region and the drain electrode region to form an source electrode and a drain electrode. Through adoption of the nanowire field effect transistor forming method, the length of the nanowires is shortened, and series resistance between the source electrode and the drain electrode can be reduced.
Description
Technical field
The present invention relates to technical field of semiconductors, relate in particular to nano-wire field effect transistor and forming method thereof.
Background technology
Integrated circuit from the single chip integrated dozens of device develop into integrated millions of device.The performance of traditional integrated circuit and complexity are considerably beyond the initial imagination.In order to be implemented in the raising aspect complexity and the current densities (quantity of the device that can hold) on certain chip area, the characteristic size of device is also referred to as " physical dimension (geometry) ", and more change is more little along with the integrated circuit in each generation.Improve integrated circuit density and not only can improve complexity and the performance of integrated circuit, and also can reduce consumption for consumers.Based on the demand to integrated circuit (IC) chip high density, high-speed, low-power consumption, integrated circuit more and more develops to high density, high-speed, low-power consumption direction.
When the characteristic size of the field-effect transistor in the integrated circuit is reduced to 32nm when following, the formation method of traditional field-effect transistor is incompatible, has proposed nano-wire field effect transistor (Nanowire FET).Wherein nano-wire field effect transistor refers to that channel length is the field-effect transistor of nanometer (nm) order of magnitude, in fact, and the field-effect transistor when just the length of raceway groove is short to and intends with the thickness comparability of raceway groove.Nano-wire field effect transistor has high current on/off ratio, and it is less to be subjected to short-channel effect and leakage to cause potential barrier reduction effects simultaneously.
Fig. 1～Fig. 5 is the cross-sectional view of method of the manufacturing nano-wire field effect transistor of prior art, and the method for the manufacturing nano-wire field effect transistor of prior art is:
With reference to figure 1, SOI is provided substrate, wherein the SOI substrate comprises: first Semiconductor substrate 11, be positioned at buried regions 12 on first Semiconductor substrate 11, be positioned at second Semiconductor substrate 13 on the buried regions 12.
With reference to figure 2, utilize photoetching, graphical second Semiconductor substrate 13 of etching technics to form nano wire 131, the source region 132 that is positioned at nano wire 131 two ends, drain region 133.
With reference to figure 3, buried regions 12 is carried out wet etching, in buried regions 12, form groove 121, nano wire 131 is suspended in groove 121 tops, and nano wire 131 is annealed, and makes nano wire 131 cylindrical or oval.
With reference to figure 4, depositing conducting layer and hard mask layer, conductive layer and hard mask layer are carried out photoetching, etching technics form grid 14 and be positioned at hard mask layer 15 on the grid 14, this grid 14 surrounds nano wire 131 around it, and the length of nano wire 131 is greater than the thickness of grid 14.
With reference to figure 5, metallization medium layer is returned dielectric layer and to be formed side wall 16 quarter (etch back) around grid 14.In the thickness d 2 sum d1+d1+d2 of the thickness d 1 of the side wall 16 of nano wire 131 bearing of trends and grid 14 length d less than nano wire 131, so nano wire 131 stretches out side wall, has to be exposed to extraneous part.
Afterwards, can carry out ion to source region 132, drain region 133 and inject formation source electrode and drain electrode.
The method of the formation nano-wire field effect transistor of the above prior art, the length that forms nano wire is bigger, greater than the thickness sum of thickness and the grid 14 of side wall 16, like this source electrode and drain between resistance bigger, can influence the performance of device.
In the prior art, many patent and patent applications about nanometer field wire effect transistor are arranged, for example publication number is disclosed " Nanowire FET with Trapezoid gate structure (nano-wire field effect transistor with trapezoidal grid structure) " in the U.S. Patent application of US2011315950A1, yet, all do not solve above technical problem.
Summary of the invention
The problem that the present invention solves is the method that prior art forms nano-wire field effect transistor, and the length of the nano wire of formation is bigger, and the thickness sum greater than thickness and the grid of side wall on the nano wire bearing of trend causes the resistance between source electrode and the drain electrode bigger.
For addressing the above problem, the invention provides a kind of method that forms nano-wire field effect transistor, comprising:
SOI is provided substrate, and described SOI substrate comprises first Semiconductor substrate, be positioned at buried regions on described first Semiconductor substrate, be positioned at second Semiconductor substrate on the described buried regions;
Graphical described second Semiconductor substrate forms source region, drain region and nano wire;
Remove the buried regions of described nano wire below segment thickness, to form groove, nano wire is suspended in the groove;
The side in the zone that second Semiconductor substrate after graphically and residue buried regions surround forms side wall;
Between the side wall of the side wall of side, described source region and side, drain region, form grid structure, described grid structure comprises grid and the gate dielectric layer between described grid and nano wire, and the width sum of grid and side wall equals the length of described nano wire on the nano wire bearing of trend;
Ion doping is carried out in described source region and drain region, form source electrode and drain electrode.
Alternatively, graphical described second Semiconductor substrate forms source region, drain region and nano wire, and the buried regions of removing described nano wire below segment thickness comprises:
Form patterned mask layer in described second Semiconductor substrate, define the position of source region, drain region and nano wire;
Be mask with described patterned mask layer, described second Semiconductor substrate of etching forms the buried regions that source region, drain region and nano wire and etching are removed described nano wire below segment thickness;
Removal is positioned at the patterned mask layer on the described nano wire;
Described side wall also is positioned at the side of described patterned mask layer.
Alternatively, form patterned mask layer in described second Semiconductor substrate, the position that defines source region, drain region and nano wire comprises:
Form hard mask layer in described second Semiconductor substrate;
Graphical described hard mask layer defines the position of nano wire;
Form dielectric layer, cover described patterned hard mask layer and described second Semiconductor substrate;
Graphical described dielectric layer defines the position of source region and drain region.
Alternatively, described hard mask layer is silicon nitride layer.
Alternatively, described dielectric layer is silicon oxide layer.
Alternatively, remove after the patterned mask layer that is positioned on the described nano wire, form side wall and also comprise before: in hydrogen atmosphere, described nano wire is carried out annealing process.
Alternatively, the formation method of described side wall comprises:
Form dielectric layer, cover described patterned mask layer, remaining buried regions;
The described dielectric layer of dry etching forms side wall;
Remove the dielectric layer under the described nano wire.
Alternatively, utilize isotropism dry method or wet etching to remove dielectric layer under the described nano wire
Alternatively, described dielectric layer is single layer structure or laminated construction.
Alternatively, the dielectric layer of described single layer structure is silicon oxide layer or silicon nitride layer.
Alternatively, after forming grid structure, described source region and drain region are carried out also comprising before the ion doping:
Remove on the described source region, patterned mask layer on the drain region.
Alternatively, utilize that wet etching is removed on the described source region, the patterned mask layer on the drain region.
Alternatively, the method for formation grid structure comprises:
Form gate dielectric layer and conductive layer successively, cover patterned mask layer on described side wall, source region and the drain region, remaining buried regions and nano wire;
Described conductive layer and gate dielectric layer are carried out planarization formation grid structure, and the end face of described grid structure is equal with the end face of described side wall.
Alternatively, described flattening method is chemical mechanical milling tech.
Alternatively, the material of described conductive layer is metal or polysilicon.
Alternatively, described first Semiconductor substrate is silicon substrate.
Alternatively, described second Semiconductor substrate is silicon substrate.
Alternatively, described buried regions is silicon oxide layer.
The present invention also provides a kind of nano-wire field effect transistor, comprising:
First Semiconductor substrate;
Be positioned at the buried regions on described first Semiconductor substrate, described buried regions has groove;
Be positioned at source electrode and the drain electrode on the buried regions of described groove both sides, the nano wire that is suspended in described groove and is connected with source electrode and drain electrode;
Grid structure and be positioned at side wall around the described grid structure, described grid structure and side wall are between described source electrode, drain electrode and surround described nano wire, described grid structure comprises grid and the gate dielectric layer between described grid and nano wire, and the width sum of described grid and side wall equals the length of described nano wire.
Alternatively, the material of described grid is metal or polysilicon.
Alternatively, described first Semiconductor substrate is silicon substrate.
Alternatively, the material of described source electrode, drain electrode and nano wire is silicon, and has the doping ion in described source electrode and the drain electrode.
Alternatively, described buried regions is silicon oxide layer.
Compared with prior art, the present invention has the following advantages:
The technical program forms the method for nano-wire field effect transistor, provides to comprise first Semiconductor substrate, be positioned at buried regions on described first Semiconductor substrate, be positioned at the SOI substrate of second Semiconductor substrate on the buried regions; Afterwards, earlier graphical second Semiconductor substrate forms source region, drain region and nano wire, removes the buried regions of described nano wire below segment thickness, forms groove below nano wire, and nano wire is suspended in the groove; Then, form side wall in the side of described source region, the side of drain region, the side of residue buried regions; Form the grid structure that comprises grid and gate dielectric layer between the side wall of the side wall of side, described source region and side, drain region, the width sum of grid and side wall equals the length of described nano wire on the nano wire bearing of trend; Ion doping is carried out in described source region and drain region, form source electrode and drain electrode.That is to say, the technical program forms side wall earlier, between side wall, form grid structure then, utilize self-registered technology when forming grid structure, can utilize depositing operation to form gate dielectric layer and conductive layer, afterwards conductive layer and gate dielectric layer are carried out flatening process formation grid structure, do not need to utilize photoetching, etching technics to form grid structure, therefore the width sum of grid and side wall equals the length of nano wire, shortened the length of nano wire with respect to prior art, can reduce the series resistance between source electrode and the drain electrode, improve the performance of device.
Description of drawings
Fig. 1～Fig. 5 is the cross-sectional view of method of the manufacturing nano-wire field effect transistor of prior art;
Fig. 6 is the schematic flow sheet of method of the formation nano-wire field effect transistor of the specific embodiment of the invention;
Fig. 7～Figure 17 is the cross-sectional view of method of the formation nano-wire field effect transistor of the specific embodiment of the invention.
Embodiment
In the prior art, utilize photoetching earlier, etching technics forms grid, around grid, form side wall then, because photoetching, the resolution of etching technics and lithographic accuracy all have certain limit, in photoetching, in the etching process, the map migration phenomenon can appear, for fear of grid to source electrode or drain directions skew, cause grid across in source electrode or drain electrode, therefore the length with nano wire increases, and nano wire is had be exposed to extraneous part, even grid is to source electrode or drain directions skew, grid also only is to be offset at nano wire, and can be across in source electrode or drain electrode, still, this kind method has caused the length of nano wire longer, thereby increased the series resistance between source electrode and the drain electrode, and then the performance of device reduces.In order to reduce the length of nano wire, to reduce the resistance between source electrode and the drain electrode, the technical program forms side wall earlier, between side wall, form the grid structure that comprises grid and gate dielectric layer then, utilize self-registered technology when forming grid structure, do not need to utilize photoetching, etching technics, therefore the width sum of grid and side wall equals the length of nano wire, shorten the length of nano wire with respect to prior art, can reduce the series resistance between source electrode and the drain electrode, improved the performance of device.
For above-mentioned purpose of the present invention, feature and advantage can more be become apparent, below in conjunction with accompanying drawing the specific embodiment of the present invention is described in detail.
Set forth detail in the following description so that fully understand the present invention.But the present invention can be different from alternate manner described here and implements with multiple, and those skilled in the art can do similar popularization under the situation of intension of the present invention.Therefore the present invention is not subjected to the restriction of following public embodiment.
Fig. 6 is the schematic flow sheet of method of the formation nano-wire field effect transistor of the specific embodiment of the invention, and with reference to figure 6, the method for the formation nano-wire field effect transistor of the specific embodiment of the invention comprises:
Step S61 provides SOI substrate, and described SOI substrate comprises first Semiconductor substrate, be positioned at buried regions on described first Semiconductor substrate, be positioned at second Semiconductor substrate on the described buried regions;
Step S62, graphical described second Semiconductor substrate forms source region, drain region and nano wire;
Step S63 removes the buried regions of described nano wire below segment thickness, to form groove, nano wire is suspended in the groove;
Step S64, the side in the zone that second Semiconductor substrate after graphically and residue buried regions surround forms side wall;
Step S65, between the side wall of the side wall of side, described source region and side, drain region, form grid structure, described grid structure comprises grid and the gate dielectric layer between described grid and nano wire, and the width sum of grid and side wall equals the length of described nano wire on the nano wire bearing of trend;
Step S66 carries out ion doping to described source region and drain region, forms source electrode and drain electrode.
Fig. 7～Figure 17 is the cross-sectional view of method of the formation nano-wire field effect transistor of the specific embodiment of the invention, below in conjunction with the method that describes the formation nano-wire field effect transistor of the specific embodiment of the invention with reference to figure 6 and Fig. 7～Figure 17 in detail.
In conjunction with reference to figure 6 and Fig. 7, execution in step S61 provides SOI substrate, and described SOI substrate comprises first Semiconductor substrate 71, be positioned at buried regions 72 on described first Semiconductor substrate 71, be positioned at second Semiconductor substrate 73 on the described buried regions 72.The material of first Semiconductor substrate 71 is monocrystalline silicon, monocrystalline germanium or monocrystalline germanium silicon, III-V group element compound, monocrystalline silicon carbide; The material of second Semiconductor substrate 73 is monocrystalline silicon, monocrystalline germanium or monocrystalline germanium silicon, III-V group element compound, monocrystalline silicon carbide; Buried regions 72 is silicon oxide layer, but is not limited to silicon oxide layer, also can be for well known to a person skilled in the art other dielectric layers.
In conjunction with reference to figure 6 and Figure 11, execution in step S62, graphical described second Semiconductor substrate 73 forms source region 731, drain region 732 and nano wires 733; Execution in step S63 removes the buried regions 72 of described nano wire 733 below segment thicknesses, to form groove 74, nano wire 733 is suspended in the groove 74.Graphical described second Semiconductor substrate 73 forms source region 731, drain region 732 and nano wire 733, the buried regions 72 of removing described nano wire 733 below segment thicknesses comprises: with reference to Figure 10, form patterned mask layer 83 in described second Semiconductor substrate 73, define the position of source region, drain region and nano wire; With reference to Figure 11, be mask with described patterned mask layer 83, described second Semiconductor substrate of etching 73 formation source regions 731, drain region 732 and nano wire 733 and etching are removed the buried regions 72 of described nano wire 733 below segment thicknesses; With reference to Figure 12, remove the patterned mask layer that is positioned on the described nano wire 733.Wherein, form patterned mask layer in described second Semiconductor substrate 73, the position that defines source region, drain region and nano wire comprises: with reference to figure 7, form hard mask layer 81 in described second Semiconductor substrate; With reference to figure 8, graphical described hard mask layer forms patterned hard mask layer 811, defines the position of nano wire; With reference to figure 9, form dielectric layer 82, cover described patterned hard mask layer 811 and described second Semiconductor substrate 73; With reference to Figure 10, graphical described dielectric layer forms patterned dielectric layer 821, defines the position of source region and drain region.Wherein, patterned dielectric layer 821 and patterned hard mask layer 811 have constituted patterned mask layer 83 jointly.
The concrete method of step S62 and step S63 is:
With reference to figure 7, form hard mask layer 81 in second Semiconductor substrate 73, the material of hard mask layer 81 is silicon nitride in the specific embodiment of the invention, but the material of hard mask layer is not limited to silicon nitride, also can be used as the dielectric material that hard mask uses for well known to a person skilled in the art other.The thickness of hard mask layer 81 needs to determine according to the actual requirements.
With reference to figure 8, in the specific embodiment of the invention, utilize photoetching, the graphical hard mask layer 81 of etching technics, form patterned hard mask layer 811, concrete patterned hard mask layer 811 is the hard mask layer of many strips that are arranged in parallel, the hard mask layer of this strip defines the position of nano wire, and also extends outside the position of nano wire, and the hard mask layer of same strip defines the position of a plurality of nano wires point-blank.In other embodiments, also can be and utilize photoetching, the graphical hard mask layer of etching technics, formation is the hard mask layer of the strip of arrayed, the hard mask layer of each strip defines the position of nano wire, the hard mask layer of corresponding strip does not extend outside the position of nano wire, and the position of a plurality of nano wires is point-blank defined by the hard mask layer of a plurality of strips that are located along the same line respectively.
Only illustrate the hard mask layer of two strips among Fig. 8, play explanation purpose of the present invention.The quantity of the hard mask layer of the concrete strip that forms is determined according to actual needs.
With reference to figure 9, form dielectric layer 82, the hard mask layer 811 after the cover graphicsization and second Semiconductor substrate 73, in the embodiment of the invention, dielectric layer 82 is silicon oxide layer, but is not limited to silicon oxide layer, also can be for well known to a person skilled in the art other dielectric layers.Afterwards, with reference to Figure 10, utilize photoetching, etching technics patterned media layer to form patterned dielectric layer 821, patterned dielectric layer 821 defines source region, drain region.Wherein, patterned hard mask layer 811 and the patterned dielectric layer 821 common patterned mask layers 83 that constitute in the embodiment of the invention.
Need to prove that among the present invention, patterned mask layer 83 is not limited to be made of patterned hard mask layer 811 and patterned dielectric layer 821.Form the method for patterned mask layer 83 for forming patterned hard mask layer 811 earlier, define the position of nano wire, form patterned dielectric layer then, define the position of source region and drain region.Among the present invention, the formation method of patterned mask layer 83 is not limited to specific embodiment described above, also can for, form mask layer, pattern mask layer then defines the position of nano wire, source region, drain region.Also can be for well known to a person skilled in the art, other can define the method for the position of nano wire, source region, drain region.
With reference to Figure 11, be mask with patterned mask layer 83, etching second Semiconductor substrate 73 forms source region 731, drain region 732 and nano wire 733; Afterwards, etching buried regions 72, remove the buried regions of nano wire below segment thickness, in buried regions 72, form groove 74, make nano wire 733 be suspended in groove 74, that is to say, be mask etching second Semiconductor substrate 73 and buried regions 72 successively with patterned mask layer 83, but when etching buried regions 72, the buried regions of etched portions thickness only, concrete etch thicknesses is determined according to the actual process needs.The method of etching second Semiconductor substrate 73 and buried regions 72 is dry etching.
Afterwards, with reference to Figure 12, remove the patterned hard mask layer 811 that is positioned on the described nano wire, the method for removing hard mask layer 811 is wet etching.Remove after the patterned hard mask layer 811, described nano wire 733 is carried out annealing process in hydrogen atmosphere, the shape of nano wire 733 becomes the shape of edge-smoothing clearly by original corner angle, is for example become cylindrical by square column type.Annealing process improves the surface roughness of nano wire, and the carrier scattering phenomenon is reduced, and mobility improves, thereby can improve the performance of device.
In conjunction with reference to figure 6 and Figure 14, execution in step S64, the side in the zone that second Semiconductor substrate after graphically and residue buried regions surround forms side wall 75, namely form side wall 75 in the side of groove, just the side of the side of second Semiconductor substrate after graphically and residue buried regions forms side wall 75, Semiconductor substrate after wherein graphical comprises source region and drain region, and therefore 731 side, the side of drain region 732 have formed side wall 75 in the source region.Because patterned mask layer is not also removed on source region and the drain region, so side wall 75 also is positioned on the described source region, patterned mask layer is the side of patterned dielectric layer 821 on the drain region.The method of concrete formation side wall comprises: with reference to Figure 13, form dielectric layer, covering remaining patterned mask layer is patterned dielectric layer 821, remaining buried regions 72, specific embodiment of the invention medium layer is silicon oxide layer, but be not limited to silicon oxide layer, also can be for well known to a person skilled in the art other dielectric layers; Then, the described dielectric layer of dry etching forms side wall 75; The method that forms dielectric layer is CVD (Chemical Vapor Deposition) method, also is formed with dielectric layer below nano wire 733, but when the etching dielectric layer formed side wall 75, because the effect of the mask of nano wire 733, the dielectric layer of nano wire below can not etching be removed; Therefore, afterwards, with reference to Figure 14, remove the dielectric layer under the described nano wire 733, be specially and utilize isotropism dry method or wet etching to remove dielectric layer under the described nano wire 733.
In conjunction with reference to figure 6 and Figure 15, execution in step S65, between the side wall of the side wall of 731 sides, described source region and 732 sides, source region, form grid structure, described grid structure comprises grid 76 and the gate dielectric layer (not shown) between described grid 76 and nano wire 733, and the width 2d2 sum of the width d1 of grid 73 and side wall equals the length d of described nano wire on nano wire 733 bearing of trends.Concrete, the method that forms grid structure comprises: form gate dielectric layer and conductive layer successively, cover patterned mask layer, remaining buried regions 72 and nano wire 733 on described side wall 75, source region 731 and the drain region 732, patterned mask layer is patterned dielectric layer 821 on source region 731 and the drain region 732 in this embodiment; Afterwards, described conductive layer and gate dielectric layer are carried out the grid structure that planarization formation comprises grid 76 and gate dielectric layer, the end face of described grid structure is equal with the end face of described side wall 75, and just the end face of described grid 76 is equal with the end face of described side wall 75.Flattening method is chemical mechanical milling tech.The material of conductive layer is metal or polysilicon.Need to prove that the end face of grid is equal with the end face of side wall and do not mean that both strictnesses are equal, allow under certain process conditions, to exist certain error between the two.
In conjunction with reference to figure 6 and Figure 16, execution in step S66 carries out ion doping to described source region 731 and drain region 732, forms source electrode 734 and drain electrode 735.Concrete formation method is: after forming grid 76, described source region 731 and drain region 732 are carried out before the ion doping, remove on the described source region 731, patterned mask layer on the drain region 732, namely remove patterned dielectric layer 821, be specially and utilize that wet etching is removed on the described source region, the patterned mask layer on the drain region.Then, ion doping is carried out in described source region 731 and drain region 732, form source electrode 734 and drain electrode 735.Wherein, the ionic type, dosage, energy etc. that ion doping is carried out in described source region 731 and drain region 732 need to determine according to the actual requirements.
Afterwards, with reference to Figure 17, form metal silicide layer 77 at source electrode 734, drain electrode 735, grid 76.Then, form interlayer dielectric layer, then in interlayer dielectric layer, form contact hole, be electrically connected with source electrode 734, drain electrode 735, grid 76.The method of concrete formation metal silicide layer 77, formation contact hole is the art technology known technology, does not do at this and gives unnecessary details.
The technical program forms side wall earlier, between side wall, form grid structure then, utilize self-registered technology when forming grid structure, can utilize depositing operation to form gate dielectric layer and conductive layer, afterwards conductive layer and gate dielectric layer are carried out the grid structure that flatening process formation comprises grid and gate dielectric layer, do not need to utilize photoetching, etching technics to form grid, therefore the width sum of grid and side wall equals the length of nano wire, shortened the length of nano wire with respect to prior art, can reduce the series resistance between source electrode and the drain electrode, improve the performance of device.
Based on the method for formation nano-wire field effect transistor described above, with reference to Figure 16, the specific embodiment of the invention also provides a kind of nano-wire field effect transistor, comprising: first Semiconductor substrate 71; Be positioned at the buried regions 72 on described first Semiconductor substrate 71, described buried regions 72 has groove; Be positioned on the described groove both sides buried regions 72 source electrode 734 with the drain electrode 735, be suspended in described groove and with source electrode 734 and 735 nano wires that are connected 733 that drain; Grid structure and be positioned at side wall 75 around the described grid structure, described grid structure and side wall 75 are between described source electrode 734, drain electrode 735 and surround described nano wire 733, described grid structure comprises grid 76 and the gate dielectric layer (not shown) between described grid 76 and nano wire 733, and the width sum of described grid 76 and side wall 75 equals the length of described nano wire 733.The material of described grid is metal or polysilicon.Described first Semiconductor substrate is silicon substrate.The material silicon of source electrode, drain electrode and nano wire, and have the doping ion in described source electrode and the drain electrode.Buried regions is silicon oxide layer.
The related content of relevant structure and material can be incorporated herein in the method for formation nano-wire field effect transistor, does not do at this and gives unnecessary details.
The nano-wire field effect transistor of the technical program has shortened the length of nano wire with respect to prior art, can reduce the series resistance between source electrode and the drain electrode, improves the performance of device.
Though the present invention with preferred embodiment openly as above; but it is not to limit the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can utilize method and the technology contents of above-mentioned announcement that technical solution of the present invention is made possible change and modification; therefore; every content that does not break away from technical solution of the present invention; to any simple modification, equivalent variations and modification that above embodiment does, all belong to the protection range of technical solution of the present invention according to technical spirit of the present invention.
Claims (23)
1. a method that forms nano-wire field effect transistor is characterized in that, comprising:
SOI is provided substrate, and described SOI substrate comprises first Semiconductor substrate, be positioned at buried regions on described first Semiconductor substrate, be positioned at second Semiconductor substrate on the described buried regions;
Graphical described second Semiconductor substrate forms source region, drain region and nano wire;
Remove the buried regions of described nano wire below segment thickness, to form groove, nano wire is suspended in the groove;
The side in the zone that second Semiconductor substrate after graphically and residue buried regions surround forms side wall;
Between the side wall of the side wall of side, described source region and side, drain region, form grid structure, described grid structure comprises grid and the gate dielectric layer between described grid and nano wire, and the width sum of grid and side wall equals the length of described nano wire on the nano wire bearing of trend;
Ion doping is carried out in described source region and drain region, form source electrode and drain electrode.
2. the method for formation nano-wire field effect transistor as claimed in claim 1 is characterized in that, graphical described second Semiconductor substrate forms source region, drain region and nano wire, and the buried regions of removing described nano wire below segment thickness comprises:
Form patterned mask layer in described second Semiconductor substrate, define the position of source region, drain region and nano wire;
Be mask with described patterned mask layer, described second Semiconductor substrate of etching forms the buried regions that source region, drain region and nano wire and etching are removed described nano wire below segment thickness;
Removal is positioned at the patterned mask layer on the described nano wire;
Described side wall also is positioned at the side of described patterned mask layer.
3. the method for formation nano-wire field effect transistor as claimed in claim 2 is characterized in that, forms patterned mask layer in described second Semiconductor substrate, and the position that defines source region, drain region and nano wire comprises:
Form hard mask layer in described second Semiconductor substrate;
Graphical described hard mask layer defines the position of nano wire;
Form dielectric layer, cover described patterned hard mask layer and described second Semiconductor substrate;
Graphical described dielectric layer defines the position of source region and drain region.
4. the method for formation nano-wire field effect transistor as claimed in claim 3 is characterized in that, described hard mask layer is silicon nitride layer.
5. the method for formation nano-wire field effect transistor as claimed in claim 3 is characterized in that, described dielectric layer is silicon oxide layer.
6. the method for formation nano-wire field effect transistor as claimed in claim 2 is characterized in that, removes after the patterned mask layer that is positioned on the described nano wire, forms side wall and also comprises before: in hydrogen atmosphere described nano wire is carried out annealing process.
7. the method for formation nano-wire field effect transistor as claimed in claim 2 is characterized in that, the formation method of described side wall comprises:
Form dielectric layer, cover described patterned mask layer, remaining buried regions;
The described dielectric layer of dry etching forms side wall;
Remove the dielectric layer under the described nano wire.
8. the method for formation nano-wire field effect transistor as claimed in claim 7 is characterized in that, utilizes isotropic dry etch or wet etching to remove dielectric layer under the described nano wire.
9. the method for formation nano-wire field effect transistor as claimed in claim 7 is characterized in that, described dielectric layer is single layer structure or laminated construction.
10. the method for formation nano-wire field effect transistor as claimed in claim 9 is characterized in that, the dielectric layer of described single layer structure is silicon oxide layer or silicon nitride layer.
11. the method for formation nano-wire field effect transistor as claimed in claim 2 is characterized in that, after forming grid structure, described source region and drain region is carried out also comprising before the ion doping:
Remove on the described source region, patterned mask layer on the drain region.
12. the method for formation nano-wire field effect transistor as claimed in claim 11 is characterized in that, utilizes that wet etching is removed on the described source region, the patterned mask layer on the drain region.
13. the method for formation nano-wire field effect transistor as claimed in claim 2 is characterized in that, the method that forms grid structure comprises:
Form gate dielectric layer and conductive layer successively, cover patterned mask layer on described side wall, source region and the drain region, remaining buried regions and nano wire;
Described conductive layer and gate dielectric layer are carried out planarization formation grid structure, and the end face of described grid structure is equal with the end face of described side wall.
14. the method for formation nano-wire field effect transistor as claimed in claim 13 is characterized in that, described flattening method is chemical mechanical milling tech.
15. the method for formation nano-wire field effect transistor as claimed in claim 13 is characterized in that, the material of described conductive layer is metal or polysilicon.
16. the method for formation nano-wire field effect transistor as claimed in claim 1 is characterized in that, described first Semiconductor substrate is silicon substrate.
17. the method for formation nano-wire field effect transistor as claimed in claim 1 is characterized in that, described second Semiconductor substrate is silicon substrate.
18. the method for formation nano-wire field effect transistor as claimed in claim 1 is characterized in that, described buried regions is silicon oxide layer.
19. a nano-wire field effect transistor is characterized in that, comprising:
First Semiconductor substrate;
Be positioned at the buried regions on described first Semiconductor substrate, described buried regions has groove;
Be positioned at source electrode and the drain electrode on the buried regions of described groove both sides, the nano wire that is suspended in described groove and is connected with source electrode and drain electrode;
Grid structure and be positioned at side wall around the described grid structure, described grid structure and side wall are between described source electrode, drain electrode and surround described nano wire, described grid structure comprises grid and the gate dielectric layer between described grid and nano wire, and the width sum of described grid and side wall equals the length of described nano wire.
20. nano-wire field effect transistor as claimed in claim 19 is characterized in that, the material of described grid is metal or polysilicon.
21. nano-wire field effect transistor as claimed in claim 19 is characterized in that, described first Semiconductor substrate is silicon substrate.
22. nano-wire field effect transistor as claimed in claim 19 is characterized in that, the material of described source electrode, drain electrode and nano wire is silicon, and has the doping ion in described source electrode and the drain electrode.
23. nano-wire field effect transistor as claimed in claim 19 is characterized in that, described buried regions is silicon oxide layer.
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| CN104658897A (en) * | 2013-11-19 | 2015-05-27 | 中芯国际集成电路制造(上海)有限公司 | Forming method of semiconductor device |
| CN104752200A (en) * | 2013-12-27 | 2015-07-01 | 中芯国际集成电路制造(上海)有限公司 | Transistor and manufacturing method thereof |
| CN106711214A (en) * | 2015-11-12 | 2017-05-24 | 联华电子股份有限公司 | Gate-all-wrapped nanowire field effect transistor device |
| CN111415902A (en) * | 2020-03-05 | 2020-07-14 | 中国科学院微电子研究所 | A kind of metal nanostructure and its production method, electronic device, electronic equipment |
| CN113594006A (en) * | 2021-07-29 | 2021-11-02 | 中国科学院上海微系统与信息技术研究所 | Vacuum channel transistor and manufacturing method thereof |
| WO2021227290A1 (en) * | 2020-05-11 | 2021-11-18 | Beijing Hua Tan Yuan Xin Electronics Technology Co., Ltd. | Transistor and method for fabricating the same |
| CN114023648A (en) * | 2021-10-18 | 2022-02-08 | 上海华虹宏力半导体制造有限公司 | Manufacturing method of trench gate semiconductor device |
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| WO2021227290A1 (en) * | 2020-05-11 | 2021-11-18 | Beijing Hua Tan Yuan Xin Electronics Technology Co., Ltd. | Transistor and method for fabricating the same |
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| CN114023648A (en) * | 2021-10-18 | 2022-02-08 | 上海华虹宏力半导体制造有限公司 | Manufacturing method of trench gate semiconductor device |
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