CN103258851A - Isolation element and manufacturing method thereof - Google Patents

Abstract

The invention provides an isolation element and a manufacturing method thereof. The isolation element includes: an isolation well region formed in the substrate by using a photolithography process and an ion implantation process for forming a high voltage device; a gate formed on the surface of the substrate; the source electrode and the drain electrode are respectively positioned in the isolation well regions at two sides of the grid electrode, and the drain electrode and the source electrode are isolated by the grid electrode; a drift drain region formed below the surface of the substrate, wherein the gate and the drain are separated by the drift drain region, part of the drift drain region is positioned below the gate, and the drain is positioned in the drift drain region; and a buffer region formed in the substrate below the drift drain region, wherein the shallowest part of the buffer region is below 90% of the depth of the drift drain region, and the buffer region and the drift drain region share a photolithography process.

Description

Isolation element and its manufacturing method

technical field

The invention relates to an isolation element and a manufacturing method thereof, in particular to an isolation element and a manufacturing method thereof which improve tunneling effect to enhance breakdown protection voltage.

Background technique

FIG. 1 shows a cross-sectional view of a P-type isolated metal oxide semiconductor (MOS) device 1 in the prior art. As shown in FIG. 1, a P-type isolation MOS element 1 is formed in a P-type substrate 11 having a field oxide region 12, including a gate 13, an N-type well region 14, a P-type drain 15, a P-type source 16, a read The electrode 17 and the P-type drift drain region 18 are taken. Wherein, the P-type drain 15, the source 16, and the drift drain region 18 are shielded by lithography technology and/or with part or all of the gate 13 to define each region, and respectively use ion implantation technology to place P-type impurities, in the form of accelerated ions, are implanted into defined regions. Wherein, the drain 15 and the source 16 are respectively located under two sides of the gate 13 . The N-type well region 14 and the reading electrode 17 are respectively shielded by lithography technology to define each region, and respectively use ion implantation technology to implant N-type impurities in the form of accelerated ions into the defined regions. formed.

When the isolation MOS element 1 shown in FIG. 1 needs to be integrated with a high-voltage element on the same substrate, in order to cooperate with the high-voltage element manufacturing process with a higher operating voltage, it is necessary to manufacture the high-voltage element and the isolation element 1 with the same ion implantation parameters. , so that the ion implantation parameters of the isolation element 1 are limited, thereby reducing the breakdown protection voltage of the isolation element 1 and limiting the application range of the isolation element 1 . Especially in the N-type well region 14 as shown in Figure 1, because of the tunneling effect between the P-type drift drain region 18 and the P-type substrate 11, the breakdown protection voltage is reduced. To prevent the above-mentioned tunneling effect, the N The N-type impurity concentration of the N-type well region 14, but in this way, the breakdown protection voltage of the high-voltage element will be reduced. If the crash protection voltage of the high voltage device is not sacrificed, it is necessary to increase the process steps or increase the area of the device to manufacture the high voltage device, but this will increase the manufacturing cost in order to achieve the desired crash protection voltage.

In view of this, the present invention aims at the deficiencies of the above-mentioned prior art, and proposes an isolation element and its manufacturing method, without increasing the element area and excessive process steps, improving the breakdown protection voltage of the element operation, increasing the element's range of applications, and can be integrated into the manufacturing process of high-voltage components.

Contents of the invention

The purpose of the present invention is to overcome the deficiencies and defects of the prior art, and propose an isolation element and a manufacturing method thereof.

To achieve the above object, the present invention provides an isolation element, comprising: a substrate, which is a first conductivity type or includes a first conductivity type well region, the substrate has an upper surface; a second conductivity type isolation element A well area is formed in the substrate below the upper surface; a grid is formed on the upper surface, and viewed from the top view, the grid is located in the second conductivity type isolated well area; the first conductivity type source pole, and the drain of the first conductivity type are respectively located in the isolation well region of the second conductivity type below the upper surface on both sides of the gate, and the drain and the source are separated by the gate; a first conductivity type type drift drain region, formed in the second conductivity type isolation well region below the upper surface, and the gate and the drain are separated by the drift drain region, part of the drift drain region is located at the gate below, the drain is located in the drift drain region; and a relaxation region, the shallowest part of which is located below 90% of the depth of the drift drain region from the upper surface, the relaxation region sharing a common area with the drift drain region The first lithography process, and the relaxation area is formed by the second conductivity type ion implantation.

From yet another point of view, the present invention also provides a method for manufacturing an isolation element, comprising: forming an isolation well region of a second conductivity type in a region of a first conductivity type of a substrate, the substrate being of the first conductivity type , or it includes a well region of the first conductivity type as the first conductivity type region, the substrate has an upper surface; a grid is formed on the upper surface, and viewed from the top view, the grid is located at the first In the isolation well region of the second conductivity type; a source electrode of the first conductivity type and a drain electrode of the first conductivity type are formed, which are respectively located in the isolation well region of the second conductivity type below the upper surfaces on both sides of the gate, and the drain electrode and the drain electrode The source is separated by the gate; a first conductivity type drift drain region is formed in the second conductivity type isolation well region below the upper surface, and the gate and the drain are formed by the drift drain region Part of the drift drain region is located under the gate, the drain is located in the drift drain region; and a relaxation region is formed, the shallowest part of which is located at a depth of 90 from the upper surface of the drift drain region % or less, the relaxation region and the drift drain region share a first lithography process, and the relaxation region is formed by ion implantation of the second conductivity type.

In one preferred embodiment, a high voltage element is further formed on the substrate, and the isolation well region of the second conductivity type shares a second lithography process and a second ion implantation process with the high voltage element.

In the above embodiment, the isolation element preferably further includes a deep well region of the second conductivity type formed under the isolation well region in the substrate.

In the aforementioned embodiments, the relaxation region and the drift drain region may have an overlapping region, which is the overlapped portion of the relaxation region and the drift drain region, and the conductivity type of the overlap region has a higher impurity concentration than other drift drain regions. The pole region is of the first low conductivity type.

The following will be described in detail through specific embodiments, so that it is easier to understand the purpose, technical content, characteristics and effects of the present invention.

Description of drawings

FIG. 1 shows a cross-sectional view of a P-type isolated MOS element in the prior art;

2A-2D show a first embodiment of the present invention;

3A and 3B respectively show the schematic diagrams of the breakdown protection voltage characteristic curves of the isolation elements using the prior art and the present invention;

Figure 4 shows a second embodiment of the present invention;

Fig. 5 shows a third embodiment of the present invention.

Explanation of symbols in the figure

1, 2, 3, 4 isolation elements

11 substrate

12 Field Oxidation Zones

13 grid

14, 24 isolation well area

15, 25 drain

16, 26 source

17, 27 read pole

18, 28 drift drain region

18a shielding

19, 29 mitigation zone

20, 21 Sham Tseng District

100 component area

Detailed ways

The drawings in the present invention are all schematic, mainly intended to represent the manufacturing process steps and the upper and lower sequence relationship between each layer, as for the shape, thickness and width, they are not drawn to scale.

Referring to Figures 2A-2D, a first embodiment of the present invention is shown. This embodiment shows a schematic cross-sectional view of the present invention applied to the manufacturing method of the P-type isolation MOS device 2 . As shown in FIG. 2A , in the P-type substrate 11 , a field oxide region 12 is formed to define a device region 100 . Wherein, the P-type substrate 11 may also be any type of substrate including the P-type well region 11 . Furthermore, the field oxide region 12 is, for example, a shallow trench isolation (STI) structure or a local oxidation of silicon (LOCOS) structure as shown in the figure. And an N-type isolation well region 14 is formed under the upper surface of the P-type substrate 11 . The isolated well region 14 is formed by a lithography process and an ion implantation process, which are also used to form another high voltage device (not shown) in the substrate 11 . In order to save manufacturing cost, the isolation well region 14 mainly considers the breakdown protection voltage of the high-voltage device to set the parameters of the ion implantation process, so generally speaking, its impurity concentration is lower than that required to isolate the MOS device. Next, please refer to FIG. 2B, in the isolation well region 14 below the upper surface of the substrate 11, a P-type drift drain region 18 is formed, and a shield 18a is formed by lithography to define the region of the drift drain region 18, and implanted with ions technology, implanting P-type impurities in the form of accelerated ions (as indicated by the dotted arrow in the figure) into a defined region. Next, please refer to FIG. 2C. Using the region defined by the shield 18a, the N-type impurity is implanted in the defined region in the form of accelerated ions (as indicated by the dotted arrow in the figure) by ion implantation technology to form a relaxation region. 19. The shallowest part of the relaxation region 19 is located below 90% of the depth of the drift drain region 18 from the upper surface. The ion implantation process steps for forming the drift drain region 18 and the relaxation region 19 can be interchanged, and are not limited to forming the drift drain region 18 first, generally speaking, the deeper relaxation region 19 is formed first. Referring to FIG. 2D , on the surface of the substrate 11 , a gate 13 , a P-type drain 15 , a P-type drain 16 , and an N-type reading electrode 17 are formed. Wherein, viewed from a top view (not shown), the gate 13 is located in the isolation well region 14 . The source 16 and the drain 15 are respectively located in the isolation well region 14 below the surface of the substrate 11 on both sides of the gate 13 , and the drain 15 and the source 16 are separated by the gate 13 . The gate 13 and the drain 15 are separated by a drift drain region 18 , part of the drift drain region 18 is located below the gate 13 , and the drain 15 is located in the drift drain region 18 .

It should be noted that the relaxation region 19 and the drift drain region 18 may or may not overlap. Overlap means that the shallowest part of the mitigation region 19 is located above 100% of the depth of the drift drain region 18 from the upper surface; non-overlap means that the shallowest part of the mitigation region 19 is located above the upper surface of the drift drain region 18. Below 100% of the depth from the surface. FIG. 2D shows an overlapping embodiment. In this embodiment, the conductivity type of the overlapping region is P-type with a lower impurity concentration than other drift drain regions 18 . In other embodiments where the drift drain region is N-type, the conductivity type of the overlapping region is N-type with a lower impurity concentration than the other drift drain regions.

3A and 3B respectively show the schematic diagrams of the breakdown protection voltage characteristic curves of the isolation element using the prior art and the present invention, and further explain how to use the present invention to enhance the breakdown protection voltage of the isolation element. Please also refer to Figure 3A, a schematic diagram of the breakdown protection voltage of the isolation element in the prior art, and Figure 3B, a schematic diagram of the breakdown protection voltage of the isolation element of the present invention. It can be seen that the breakdown protection voltage of the isolation element of the present invention, compared with the prior art, When the isolation element is not conducting, the breakdown protection voltage is significantly higher than that of the isolation element in the prior art.

Fig. 4 shows a second embodiment of the present invention. Different from the first embodiment, the isolation element 3 of this embodiment further includes an N-type deep well region 20 formed in the substrate 11 below the isolation well region 14 . The purpose of this embodiment is to illustrate, except that the relief region 19 is formed by using the same shield as the drift drain region 18, and the shallowest part of the relief region 19 is located within 90% of the depth of the drift drain region 18 from the upper surface. Except for the following, there are no other limitations on the isolation element, and the relaxation region 19 can even be connected to the deep well region 20 or the P-type substrate 11, without affecting the intended effect of the present invention.

Fig. 5 shows a third embodiment of the present invention. This embodiment illustrates that the present invention can also be applied to the N-type isolation element 4 . As shown in the figure, the isolation element 4 and the high-voltage element (not shown) are jointly formed in the P-type substrate 11, including an N-type deep well region 21, a P-type isolation well region 24, an N-type source electrode 26, and an N-type drain electrode 25. , P-type reading electrode 27 , N-type drift drain region 28 , and relaxation region 29 . Wherein, the N-type deep well region 21 is formed in the substrate 11 below the surface of the substrate 11 . The P-type isolated well region 24 is formed in the deep well region 21 , and the isolated well region 24 is formed by a lithography process and an ion implantation process, which are also used to form high-voltage components in the substrate 11 . The gate 13 is formed on the surface of the substrate 11 , and viewed from a top view (not shown), the gate 13 is located in the isolation well region 24 . The N-type source 26 and the N-type drain 25 are respectively located in the isolation well region 24 below the surface of the substrate 11 on both sides of the gate 13 , and the drain 25 and the source 26 are separated by the gate 13 . The N-type drift drain region 28 is formed in the isolation well region 24 below the surface of the substrate 11, and the gate 13 and the drain 25 are separated by the drift drain region 28, part of the drift drain region 28 is located below the gate 13, and the drain The pole 25 is located in the drift drain region 28 . Similar to the first embodiment, the shallowest part of the relief region 29 is located below 90% of the depth of the drift drain region 28 from the upper surface, and the relief region 29 uses the same lithography process used to form the drift drain region 28, The ion implantation process utilizes an accelerated P-type ion beam to implant into the substrate 11 under the same shield as that used to form the drift drain region 28 .

Similar to the first embodiment, the mitigation region 29 and the drift drain region 28 may or may not overlap. For example, there may be an overlapping region between the relaxation region 29 and the drift drain region 28, which is the overlapping portion of the relaxation region 29 and the drift drain region 28. The drift drain region 28 is low N-type.

It should be noted that the P-type substrate 11 can be, for example, a P-type bare substrate, that is, a P-type wafer is directly used as the P-type substrate 11; the P-type substrate 11 can also be a P-type epitaxial layer formed by epitaxial technology.

The present invention has been described above with reference to preferred embodiments, but the above description is only for those skilled in the art to easily understand the content of the present invention, and is not intended to limit the scope of rights of the present invention. Under the same spirit of the present invention, various equivalent changes can be conceived by those skilled in the art. For example, without affecting the main characteristics of the device, other process steps or structures can be added, such as threshold voltage adjustment regions, etc.; as another example, lithography is not limited to photomask technology, and can also include electron beam lithography. The scope of the present invention is intended to cover the above and all other equivalent variations.

Claims (8)

1. an isolated component is characterized in that, comprises:

One substrate, it is that first conductivity type or its comprise one first conductivity type wellblock, this substrate has a upper surface;

One second conductivity type is isolated the wellblock, is formed in this this substrate of upper surface below;

One grid is formed on this upper surface, and looks it by top view, and this grid is arranged in this second conductivity type and isolates the wellblock;

The first conductivity type source electrode, with first conductivity type drain electrode, this second conductivity type that lays respectively at this upper surface below, grid both sides is isolated in wellblock, and this drain electrode and this source electrode are separated by this grid;

One first conductivity type drift drain region, this second conductivity type that is formed at this upper surface below is isolated in wellblock, and this grid separates by this drift drain region with this drain electrode, and partly this drift drain region is positioned at below this grid, and this drain electrode is arranged in this drift drain region; And

One relaxes the district, and its shallow portion is positioned at the degree of depth of starting at from this upper surface this drift drain region below 90%, and this relaxes the district and shares one first micro-photographing process with this drift drain region, and should relax the district and formed by the implantation of second conduction type ion.

2. isolated component as claimed in claim 1 wherein, more is formed with a high voltage device on this substrate, and this second conductivity type is isolated the wellblock and this high voltage device is shared one second micro-photographing process and one second ion implantation manufacture process.

3. isolated component as claimed in claim 2 wherein, also comprises the second conduction type deep well area, is formed at this below, isolation wellblock in this substrate.

4. isolated component as claimed in claim 2, wherein, having the district that overlaps between this mitigation district and this drift drain region, is that this relaxes part that district and this drift drain region overlap, and the conductivity type in this overlappings district is that to have impurity concentration be the first low conductivity type than other drain region that drifts about.

5. an isolated component manufacture method is characterized in that, comprises:

Form one second conductivity type and isolate the wellblock in one first conductive area of a substrate, this substrate is that first conductivity type or its comprise one first conductivity type wellblock with as this first conductive area, and this substrate has a upper surface;

Form a grid on this upper surface, and look it by top view, this grid is arranged in this second conductivity type and isolates the wellblock;

Form the first conductivity type source electrode, with first conductivity type drain electrode, this second conductivity type that lays respectively at this upper surface below, grid both sides is isolated in wellblock, and this drain electrode and this source electrode are separated by this grid;

Form one first conductivity type drift drain region and isolate in wellblock in this second conductivity type of this upper surface below, and this grid separates by this drift drain region with this drain electrode, partly this drift drain region is positioned at below this grid, and this drain electrode is arranged in this drift drain region; And

Form one and relax the district, its shallow portion is positioned at the degree of depth of starting at from this upper surface this drift drain region below 90%, and this relaxes the district and shares one first micro-photographing process with this drift drain region, and should relax the district and formed by the implantation of second conduction type ion.

6. isolated component manufacture method as claimed in claim 5 wherein, more is formed with a high voltage device on this substrate, and this second conductivity type is isolated the wellblock and this high voltage device is shared one second micro-photographing process and one second ion implantation manufacture process.

7. isolated component manufacture method as claimed in claim 6 wherein, also comprises the formation second conduction type deep well area this below, isolation wellblock in this substrate.

8. isolated component manufacture method as claimed in claim 6, wherein, having the district that overlaps between this mitigation district and this drift drain region, is that this relaxes part that district and this drift drain region overlap, and the conductivity type in this overlappings district is that to have impurity concentration be the first low conductivity type than other drain region that drifts about.

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