CN103268080A

CN103268080A - Power quality monitoring device

Info

Publication number: CN103268080A
Application number: CN2013102234818A
Authority: CN
Inventors: 丁建义; 林峰平; 陈宜彬; 梁启权; 乔冠梁; 王包东; 董金发; 葛庆光
Original assignee: SHENZHEN KANGBIDA ZHONGCHUANG TECHNOLOGY Co Ltd
Current assignee: SHENZHEN KANGBIDA ZHONGCHUANG TECHNOLOGY Co Ltd
Priority date: 2013-06-03
Filing date: 2013-06-03
Publication date: 2013-08-28

Abstract

The invention discloses a power quality monitoring device. An FPGA (field programmable gate array) is used for precisely controlling a high-speed ADC (analogue-to-digital converter) to perform the dense sampling, and the real-time sampling data is transmitted to a high-speed floating-point type DSP (digital signal processor) to be computed, the algorithm comprises analyzing and processing voltage flicker, harmonic analysis, harmonic distortion, and voltage temporary fluctuation about the power quality, and the computed result is transmitted to an in-place or remote human-computer interface to perform the imaging demonstration; and the system DSP is capable of automatically sampling through an internal EMDA unit, and notifying the DSP processor in an interrupting mode after sampling the semi-cycle, and the DSP is used for managing and processing the data, the whole process is circulated, the DSP is used for analyzing various algorithms of the sampling data, and the processed data is transferred to a system main CPU (central processing unit) through a dual-port Ram (random-access memory), the main CPU is responsible for processing the man-machine event, and displaying the DSP data on the interface, and meanwhile, the data is transferred to a remote terminal or a control centre through the Ethernet.

Description

A kind of equipment for monitoring power quality

Technical field

The present invention relates to intelligent grid control field, be specifically related to a kind of equipment for monitoring power quality.

Background technology

Progress along with science and technology, use electrical load conditions that great variation has taken place in the modern power systems, such as developing rapidly of semiconductor rectifier, thyristor voltage regulation and loads such as frequency converter adjusting gear, electric furnace arrangement for producing steel, electric railway and household electrical appliance, because it is non-linear, impact and the unbalanced electrical characteristics of using, make the voltage waveform generation distortion of electrical network cause voltage fluctuation and flickering and three-phase imbalance, even causing system frequency fluctuation etc., the quality of power supply causes serious disturbance to powering.Just facing to increasing power quality problem, this makes that the research of the quality of power supply is very urgent in the electrical network.

Electric energy quality monitoring is the direct approach that obtains the electric energy related data, has only the quality of power supply is correctly monitored, and could grasp quality of power supply level and the actual state of electrical network, and the understanding operating load causes rule and the characteristic of quality of power supply decline.

This electric energy quality monitor namely is based on such one and uses prerequisite, and the development project that proposes.Its target is to carry out advanced power quality analysis, the quality of power supply is monitored in high-precision measurement in real time, makes power consumer can obtain every service data of electric energy in the very first time, thereby the quality of power supply is assessed fully and monitored, propose to improve countermeasure and the scheme of power index.

Summary of the invention

The technical problem to be solved in the present invention is to provide the Power Quality Monitor Device of a kind of high-level efficiency, high precision and real-time monitoring.

For solving the problems of the technologies described above, the present invention is achieved through the following technical solutions: a kind of equipment for monitoring power quality, it adopts FPGA accurately to control high-speed ADC to carry out intensive sampling, and the real-time sampling data are sent among the high-speed floating point type DSP carry out computing, comprise in the algorithm for the analyzing and processing about the quality of power supply such as voltage flicker, frequency analysis, harmonic distortion, the temporary lifting of voltage, and calculated result transferred on the spot or long-range man-machine interface is graphically demonstrated; This apparatus system comprises PT/CT interception unit, fpga logic control module, DSP algorithm process unit, HPI bus, PowerPC issued transaction unit, main CPU unit, human and machine interface unit, Ethernet; PT/CT in the device is responsible for three-phase voltage, electric current are carried out the signal intercepting, sends at a high speed that 16 A/D carry out AC sampling, accurately control the sampling period with at interval, be responsible for finishing steering logic for the A/D sampling by FPGA; System DSP samples automatically by its inner EMDA unit, and after the sampling half cycles, notify dsp processor by the mode of interrupting, the data of DSP manage and handle, the circulation that whole process is gone round and begun again is carried out, the sampled data of DSP is carried out various Algorithm Analysis, and the data after will handling are forwarded to system's host CPU via dual port RAM, and host CPU is responsible for man-machine issued transaction, the DSP data are shown to the interface, forward the data to remote terminal or control center by Ethernet simultaneously.

Further, described fpga logic control module internal register is controlled the operation of the ADC of FPGA, realizes equal interval sampling, the each sampling of ADC is finished and is produced a look-at-me, the EDMA module of notice DSP reads, and when reading the data of full half cycle, the data of notice DSP are handled.Simultaneously the gps signal of FPGA is resolved, and the result is passed to PowerPC, as system to the time, FPGA also manages and operates DI DO.

Further, DSP starts ADC and begins to exchange data sampling after arranging of FPGA finished in initialization, and the EDMA passage that starts DSP inside simultaneously begins to prepare to receive data, and these work are realized by the DSP inner control logic; The analysis computing to sampled data is responsible for finishing in the algorithm process unit of DSP, calculated result transfers to system's host CPU by dual port RAM, increase one deck two-port RAM as data buffering between DSP and system's host CPU, dual port RAM is wherein realized by FPGA is inner.

Further, main CPU unit is carried out interface with external data by inner LOCAL BUS bus, and by the steering logic unit of inside data are carried out following processing, the one, data directly are forwarded to the upper strata image library, be responsible for that data are converted into various curves, pie chart etc. and the online man-machine interface of transferring to shows by image library, simultaneously the data packing is forwarded to the ICP/IP protocol layer, carries out remote transmission by Ethernet and handle.The present invention has following advantage

(1) adopt the DSP+PowerPC based on dual-CPU architecture, take full advantage of the managerial ability at storage, demonstration and the interface of the processing power of DSP and PowerPC,

(2) adopt FPGA control sampling, increase precision and the dirigibility of controlling of sampling.

(3) develop dual port RAM by FPGA, the independent dual port RAM chip that uses, more reliable, cost is lower.

Description of drawings

Fig. 1 is system architecture logic diagram of the present invention;

Fig. 2 is FPGA system logic block diagram of the present invention;

Fig. 3 is dsp system logic diagram of the present invention;

Fig. 4 is main CPU system logic diagram of the present invention.

Embodiment

Shown in Figure 1, the entire product design is divided into following link: be responsible for three-phase voltage, electric current are carried out the signal intercepting by the PT/CT in the device, sending at a high speed, 16 A/D carry out AC sampling.

According to designing requirement, accurately control sampling period and interval, be responsible for finishing the steering logic of sampling for A/D by FPGA.Be responsible for controlling the logic of FPGA by the DSP of system, start, stop A/D, and read data by the EDMA module of DSP.The circulation that whole process is gone round and begun again is carried out.The sampled data of DSP is carried out various Algorithm Analysis, and the data after will handling are forwarded to system's host CPU via dual port RAM.System's host CPU is responsible for man-machine issued transaction, and the DSP data are shown to the interface, forwards the data to remote terminal or control center by Ethernet simultaneously.

As shown in Figure 2, DSP control operation FPGA internal register is controlled the operation of the ADC of FPGA.After FPGA starts, the AC sampling of 2 powers of output electrical network fundamental frequency square wave control ADC doubly, sampled data enters DSP by the EDMA module of DSP, the gps signal of FPGA is resolved simultaneously, be used for system to the time, FPGA also utilizes its very strong logical capability that DI DO is handled, and opens up address control as dual port RAM, because mutual between DSP and the PowerPC.

By shown in Figure 3, DSP starts ADC and begins to exchange data sampling after arranging of FPGA finished in initialization.And the EDMA passage that starts DSP inside simultaneously reads sampled data, and the internal processor of Periodic Notice DSP.These work are realized by the DSP inner control logic.

The analysis computing to sampled data is responsible for finishing in the algorithm process unit of DSP.Calculated result transfers to system's host CPU by 16 dual port RAMs.Shown in Figure 4, main CPU system is carried out interface with external data by inner LOCAL BUS bus, and by the steering logic unit of inside data is carried out following processing:

The one, data directly are forwarded to the upper strata image library, be responsible for that data are converted into various curves, pie chart etc. and the online man-machine interface of transferring to shows by image library.Simultaneously the data packing is forwarded to the ICP/IP protocol layer, carries out remote transmission by Ethernet and handle.Main CPU unit is mainly finished the work of above two aspects, owing to the requirement of real-time is finished at FPGA and DSP end, so for host CPU, the requirement of relevant real-time.

Claims

1. equipment for monitoring power quality, it is characterized in that: adopt FPGA accurately to control high-speed ADC and carry out intensive sampling, and the real-time sampling data are sent among the high-speed floating point type DSP carry out computing, comprise in the algorithm for the analyzing and processing about the quality of power supply such as voltage flicker, frequency analysis, harmonic distortion, the temporary lifting of voltage, and calculated result is transferred to the Local or Remote man-machine interface graphically demonstrate; This apparatus system comprises PT/CT interception unit, fpga logic control module, DSP algorithm unit, dual port RAM, Power PC issued transaction unit, main CPU unit, human and machine interface unit, Ethernet; PT/CT in the device is responsible for three-phase voltage, electric current are carried out the signal intercepting, sends at a high speed that 16 A/D carry out AC sampling, accurately control the sampling period with at interval, be responsible for finishing steering logic for the A/D sampling by FPGA; System DSP samples automatically by its inner EMDA unit, and notifies dsp processor by the mode of interrupting after the sampling half cycles, and the data of DSP manage and handle, and the circulation that whole process is gone round and begun again is carried out; The sampled data of DSP is carried out various Algorithm Analysis, and the data after will handling are forwarded to system's host CPU through dual port RAM, host CPU is responsible for man-machine issued transaction, the DSP data are shown to the interface and store, and forwards the data to remote terminal or control center by Ethernet simultaneously.

2. equipment for monitoring power quality according to claim 1, it is characterized in that: described fpga logic control module internal register is controlled the operation of the ADC of FPGA, realize equal interval sampling, the each sampling of ADC is finished and is produced a look-at-me, the EDMA module of notice DSP reads, when reading the data of full half cycle, the data of notice DSP are handled.Simultaneously the gps signal of FPGA is resolved, and the result is passed to PowerPC, as system to the time, FPGA also manages and operates DI DO.

3. equipment for monitoring power quality according to claim 1 and 2, it is characterized in that: DSP is after arranging of FPGA finished in initialization, start ADC and begin to exchange data sampling, and the EDMA passage that starts DSP inside simultaneously begins prepare to receive data, and these work are realized by the DSP inner control logic; The analysis computing to sampled data is responsible for finishing in the algorithm process unit of DSP, calculated result transfers to system's host CPU by dual port RAM, increase one deck two-port RAM as data buffering between DSP and system's host CPU, dual port RAM is wherein realized by FPGA is inner.

4. according to claim 1 or 3 described equipment for monitoring power quality, it is characterized in that: main CPU unit is carried out interface with external data by inner LOCAL BUS bus, and by the steering logic unit of inside data are carried out following processing, the one, data directly are forwarded to the upper strata image library, be responsible for that data are converted into various curves, pie chart etc. and the online man-machine interface of transferring to shows by image library, simultaneously the data packing is forwarded to the ICP/IP protocol layer, carries out remote transmission by Ethernet and handle.