CN103311131A - Method for preventing lateral undercutting of micro-convex points in manufacturing process of micro-convex points - Google Patents
Method for preventing lateral undercutting of micro-convex points in manufacturing process of micro-convex points Download PDFInfo
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- CN103311131A CN103311131A CN2013101822051A CN201310182205A CN103311131A CN 103311131 A CN103311131 A CN 103311131A CN 2013101822051 A CN2013101822051 A CN 2013101822051A CN 201310182205 A CN201310182205 A CN 201310182205A CN 103311131 A CN103311131 A CN 103311131A
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- 238000000034 method Methods 0.000 title claims abstract description 44
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 18
- 238000005530 etching Methods 0.000 claims abstract description 42
- 239000004065 semiconductor Substances 0.000 claims abstract description 23
- 238000009713 electroplating Methods 0.000 claims abstract description 7
- 230000004888 barrier function Effects 0.000 claims description 77
- 239000000463 material Substances 0.000 claims description 37
- 239000002184 metal Substances 0.000 claims description 21
- 229910052751 metal Inorganic materials 0.000 claims description 21
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 12
- 238000001259 photo etching Methods 0.000 claims description 9
- 238000001312 dry etching Methods 0.000 claims description 6
- 239000000377 silicon dioxide Substances 0.000 claims description 6
- 238000010992 reflux Methods 0.000 claims description 5
- 229910000679 solder Inorganic materials 0.000 claims description 5
- 238000002360 preparation method Methods 0.000 claims description 4
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 4
- KUNSUQLRTQLHQQ-UHFFFAOYSA-N copper tin Chemical group [Cu].[Sn] KUNSUQLRTQLHQQ-UHFFFAOYSA-N 0.000 claims description 2
- 239000000758 substrate Substances 0.000 abstract description 4
- 238000003466 welding Methods 0.000 abstract 5
- 230000000903 blocking effect Effects 0.000 abstract 4
- 230000004907 flux Effects 0.000 abstract 1
- 230000015572 biosynthetic process Effects 0.000 description 11
- 241000208340 Araliaceae Species 0.000 description 10
- 235000005035 Panax pseudoginseng ssp. pseudoginseng Nutrition 0.000 description 10
- 235000003140 Panax quinquefolius Nutrition 0.000 description 10
- 235000008434 ginseng Nutrition 0.000 description 10
- 239000010949 copper Substances 0.000 description 8
- 239000004642 Polyimide Substances 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 230000000694 effects Effects 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 6
- 229920001721 polyimide Polymers 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 4
- 239000011810 insulating material Substances 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 238000005538 encapsulation Methods 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 239000004411 aluminium Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 150000003851 azoles Chemical class 0.000 description 2
- 230000008020 evaporation Effects 0.000 description 2
- 238000001704 evaporation Methods 0.000 description 2
- 239000003292 glue Substances 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 229920000620 organic polymer Polymers 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229920006389 polyphenyl polymer Polymers 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 238000013459 approach Methods 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/03—Manufacturing methods
- H01L2224/036—Manufacturing methods by patterning a pre-deposited material
- H01L2224/03622—Manufacturing methods by patterning a pre-deposited material using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/1012—Auxiliary members for bump connectors, e.g. spacers
- H01L2224/10122—Auxiliary members for bump connectors, e.g. spacers being formed on the semiconductor or solid-state body to be connected
- H01L2224/10125—Reinforcing structures
- H01L2224/10126—Bump collar
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/11001—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate
- H01L2224/11009—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate for protecting parts during manufacture
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Abstract
The invention discloses a forming method of micro-convex points. The forming method comprises the following steps of s1, forming a welding disc on a semiconductor substrate; s2, forming a medium layer on the surfaces of the welding disc and the semiconductor substrate, wherein the medium layer is provided with a window which corresponds to the welding disc; s3, forming a seed layer on the surfaces of the medium layer and the welding disc; s4, forming the micro-convex points on the surface of the seed layer in an electroplating manner; s5, forming a blocking layer on the seed layer around the micro-convex points within a certain distance; s6, etching the seed layer which is not covered by the blocking layer; and s7, returning welding flux. The method disclosed by the invention has the advantages that since an etching blocking layer covers the seed layer around the micro-convex points, when the seed layer is etched, the seed layer under the etching blocking layer can be protected from being etched, so that the phenomenon of lateral undercutting is prevented; and the reliability and the yield of processing and manufacturing of the micro-convex points are improved.
Description
Technical field
The invention belongs to technical field of manufacturing semiconductors, particularly prevent dimpling point side direction undercutting method in a kind of dimpling point manufacture process.
Background technology
Traditionally, IC chip and outside being electrically connected are in the mode of bonding the I/O on the chip to be connected to package carrier and to realize through packaging pin with metal lead wire.Along with the expansion with integrated scale dwindled of IC chip features size, I/O ask apart from constantly reduce, quantity is on the increase.When the I/O spacing narrows down to 70 μ m when following, Wire Bonding Technology is just no longer suitable, must seek new technological approaches.
Wafer-Level Packaging Technology utilizes the film technology that distributes again, I/O can be distributed on the whole surface of IC, and no longer only be confined to the neighboring area of narrow IC chip, thereby solved the problem that is electrically connected of high density, thin space I/O chip.
In the existing encapsulation technology, when electroplating dimpling point, side direction undercutting (undercutting) is very serious, when dimpling point pitch more and more hour, the reliability of dimpling point will go wrong, self intensity and the yield of dimpling point will descend.Owing to side direction undercutting problem can occur, so when carrying out the Seed Layer etching, the selection of etching liquid and the control of etching technics will be restricted.
Summary of the invention
At the deficiencies in the prior art, the technical problem that the present invention solves provides and prevents dimpling point side direction undercutting method in a kind of dimpling point manufacture process, to improve reliability and the yields of the processing and manufacturing of dimpling point.
For solving above-mentioned technical problem, technical scheme of the present invention is achieved in that
A kind of formation method of dimpling point comprises:
S1, form pad at the semiconductor-based end;
S2, form dielectric layer at pad and semiconductor-based basal surface, offer window on the described dielectric layer, described window is corresponding with pad;
S3, form Seed Layer on the surface of dielectric layer and pad;
S4, form the dimpling point at described Seed Layer electroplating surface;
S5, the Seed Layer around the dimpling point in the certain distance form the barrier layer, and described certain distance satisfies: after the etching of step s6, the end of Seed Layer just and the justified margin of dimpling point or be positioned at the outside of dimpling point;
S6, etching are not blocked the Seed Layer that layer covers;
S7, reflux solder.
Preferably, in the formation method of above-mentioned dimpling point, described step s5 specifically comprises: form the barrier layer on the surface of dimpling point and Seed Layer, and graphical described barrier layer, and make the barrier layer that stays be covered at least on the interior Seed Layer of certain distance around the dimpling point.
Preferably, in the formation method of above-mentioned dimpling point, described graphical barrier layer adopts photoetching process to carry out, by the barrier layer in the certain distance around the barrier layer above the photoetching reservation dimpling point and the dimpling point, this moment, the material on described barrier layer was light-sensitive material, among the described step s7, also comprise the step of removing the barrier layer.
Preferably, in the formation method of above-mentioned dimpling point, described graphical barrier layer adopts dry etch process to carry out, and only keeps the barrier layer in the certain distance around the dimpling point by dry etching, and the material on described barrier layer is polymeric material at this moment.
Preferably, in the formation method of above-mentioned dimpling point, described polymeric material is the PI(polyimides) or the PBO(polyphenyl and chew azoles).
Preferably, in the formation method of above-mentioned dimpling point, also be formed with a layer insulating, described pad is positioned on this insulating barrier at described the semiconductor-based end.
Preferably, in the formation method of above-mentioned dimpling point, described insulating barrier material is selected from silica or carborundum.
Preferably, in the formation method of above-mentioned dimpling point, described dimpling point is copper tin dimpling point.
Correspondingly, the invention also discloses the encapsulating structure that prevents the undercutting of dimpling point side direction in a kind of dimpling point manufacture process, one layer insulating is arranged at semiconductor-based the end, preparation has metal pad on the insulating barrier, electroplate one deck Seed Layer on the metal pad, preparation has a dimpling point on the Seed Layer, covers etching barrier layer on the Seed Layer around the dimpling point, the justified margin of the Seed Layer that is covered by described etching barrier layer and dimpling point lucky in its end behind over etching or be positioned at the outside of dimpling point.
Compared with prior art, the present invention proposes by the covering of the Seed Layer around dimpling point one deck etching barrier layer, like this when carrying out the Seed Layer etching, can protect the Seed Layer below it to avoid etching, thereby prevent the phenomenon of side direction undercutting.Improve reliability and the yields of the processing and manufacturing of dimpling point.
Description of drawings
In order to be illustrated more clearly in the embodiment of the invention or technical scheme of the prior art, to do to introduce simply to the accompanying drawing of required use in embodiment or the description of the Prior Art below, apparently, accompanying drawing in describing below only is some embodiments of the present invention, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 a～Fig. 1 l is depicted as the structural representation that forms dimpling point in the first embodiment of the invention;
Figure 2 shows that the schematic flow sheet that forms dimpling point in the specific embodiment of the invention;
Figure 3 shows that in the second embodiment of the invention by the structural representation of dry etching after to barrier etch;
Figure 4 shows that in the second embodiment of the invention the structural representation after the Seed Layer etching;
Fig. 5 is the structural representation that is depicted as the barrier layer that forms in the third embodiment of the invention;
Figure 6 shows that the structural representation after the barrier layer is etched in the third embodiment of the invention.
Embodiment
The present invention proposes by the covering of the Seed Layer around dimpling point one deck etching barrier layer, like this when carrying out the Seed Layer etching, can protect the Seed Layer below it to avoid etching, thereby prevent the phenomenon of side direction undercutting.
Particularly, the embodiment of the invention discloses a kind of formation method of dimpling point, comprising:
S1, form pad at the semiconductor-based end;
S2, form dielectric layer at pad and semiconductor-based basal surface, offer window on the described dielectric layer, described window is corresponding with pad;
S3, form Seed Layer on the surface of dielectric layer and pad;
S4, form the dimpling point at described Seed Layer electroplating surface;
S5, the Seed Layer around the dimpling point in the certain distance form the barrier layer, and described certain distance satisfies: after the etching of step s6, the end of Seed Layer just and the justified margin of dimpling point or be positioned at the outside of dimpling point;
S6, etching are not blocked the Seed Layer that layer covers;
S7, reflux solder.
Below in conjunction with the accompanying drawing in the embodiment of the invention, the technical scheme in the embodiment of the invention is described in detail, obviously, described embodiment only is the present invention's part embodiment, rather than whole embodiment.Based on the embodiment among the present invention, the every other embodiment that those of ordinary skills obtain under the prerequisite of not making creative work belongs to the scope of protection of the invention.
Join illustrated in figures 1 and 2ly, in first embodiment of the invention, the formation method of dimpling point comprises:
1) provides the semiconductor-based end 101 that is formed with insulating barrier 102 on the surface, shown in ginseng Fig. 1 a.
Material can be various semi-conducting materials such as silicon, SiGe and silicon-on-insulator in order to be formed with some semiconductor device and required wire structures at the semiconductor-based end 101.
The insulating barrier material can be silica, carborundum etc., and its effect is conducting of barrier metal pad and substrate.
2) make metal pad 201 at insulating barrier, shown in ginseng Fig. 1 b.
Metal pad 201 is tie point, can be materials such as aluminium or copper.
3) form dielectric layer 301 at metal pad and surface of insulating layer, and make window by the dielectric layer of photoetching above metal pad, window is positioned at the top of metal pad, shown in ginseng Fig. 1 c.
4) form Seed Layer 401 on the surface of dielectric layer and metal pad, shown in ginseng Fig. 1 d.
Seed Layer 401 is made by sputtering method or evaporation technology, and the material of Seed Layer is Ti/Cu preferably, and the effect of Ti is that its adhesive attraction and barrier metal copper enter silicon base, and the effect of Cu is the electrode when electroplating.
5) make photoresist material 501, and carry out the dimpling dot patternization by photoetching, electro-coppering tin dimpling point 601 is shown in ginseng Fig. 1 e and Fig. 1 f.
6) the stripping photolithography glue material 501, shown in ginseng Fig. 1 g.
7) form barrier layer 701 on the surface of dimpling point and Seed Layer, the material on barrier layer 701 is light-sensitive material, shown in ginseng Fig. 1 h.Light-sensitive material can be positive photoresist or negative photoresist.
8) by photoetching barrier material is carried out graphically, with the barrier layer in the certain distance around the barrier material above the reservation dimpling point and the dimpling point, the certain distance at this place refers to can avoid the size of side direction undercutting when Seed Layer is carried out etching, that is satisfy: after the etching of step 9), join shown in Fig. 1 i just with the justified margin of dimpling point or be positioned at the outside of dimpling point the end of Seed Layer.
9) etching is not blocked the Seed Layer that layer covers, and the Seed Layer that is blocked layer covering is positioned at the outside of dimpling point in its end behind over etching, shown in ginseng Fig. 1 j.
10) peel off the barrier material that is not etched, shown in ginseng Fig. 1 k.
11) reflux solder is shown in ginseng Fig. 1 l.
In second embodiment of the invention, the formation method of dimpling point comprises:
1) provides the semiconductor-based end that is formed with insulating barrier on the surface.
Material can be various semi-conducting materials such as silicon, SiGe and silicon-on-insulator in order to be formed with some semiconductor device and required wire structures at the semiconductor-based end.
The insulating barrier material can be silica, carborundum etc., and its effect is conducting of barrier metal pad and substrate.
2) make metal pad at insulating barrier.
Metal pad is tie point, can be materials such as aluminium or copper.
3) form dielectric layer at metal pad and surface of insulating layer, and make window by the dielectric layer of photoetching above metal pad, window is positioned at the top of metal pad.
Dielectric layer was not damaged in encapsulation process for the protection of the semiconductor-based end; the material of dielectric layer can be insulating material or benzocyclobutane olefine resin (Benzocyclobutene such as silica, silicon nitride, silicon oxynitride; BCB), polyimides (polyimide, various organic polymer insulating material such as PI).
4) form Seed Layer on the surface of dielectric layer and metal pad.
Seed Layer is made by sputtering method or evaporation technology, and the material of Seed Layer is Ti/Cu preferably, and the effect of Ti is that its adhesive attraction and barrier metal copper enter silicon base, and the effect of Cu is the electrode when electroplating.
5) make the photoresist material, and carry out the dimpling dot patternization, electro-coppering tin dimpling point by photoetching.
6) stripping photolithography glue material.
7) form the barrier layer on the surface of dimpling point and Seed Layer, in the present embodiment, the material on barrier layer only needs common polymeric material.Such as the PI(polyimides), the PBO(polyphenyl and chew azoles) etc., can certainly be the light-sensitive material in the execution mode one.
8) by dry etching barrier material is carried out etching, only keep the etching barrier layer material on the Seed Layer in the certain distance around the dimpling point, the certain distance at this place refers to can avoid the size of side direction undercutting when Seed Layer is carried out etching, that is satisfy: after the etching of step 9), the end of Seed Layer just and the justified margin of dimpling point or be positioned at the outside of dimpling point.
Surface in dimpling point and Seed Layer forms the barrier layer, dimpling point can be greater than the thickness of other position blocks layers with the thickness on the barrier layer of Seed Layer junction, when therefore carrying out etching by dry etching, dimpling point is bigger owing to thickness with the barrier layer of Seed Layer junction, after the barrier layer of other positions is etched away, still exist, join shown in Figure 3.
9) etching is not blocked the Seed Layer that layer covers, and the Seed Layer that is blocked layer covering is positioned at the outside of dimpling point in its end behind over etching, joins shown in Figure 4.
10) reflux solder.
It is to be noted herein, in the step (8), only considered etching is being carried out with when exposing Seed Layer in the barrier layer of bottom, the barrier layer of the dimpling point top clean situation that also is etched in the lump, therefore in subsequent step, do not increase and remove the step that residue stops, yet in actual applications, if the thickness on barrier layer, dimpling point top is greater than the thickness that is positioned at barrier layer, Seed Layer top, then the barrier layer is being carried out in the process of etching by dry etching, the barrier etch of Seed Layer top is finished, but still there is the barrier layer in dimpling point top, also needs to comprise the step that residue barrier layer, dimpling point top is removed this moment.
In third embodiment of the invention, to compare with first embodiment, the thickness on formed barrier layer 802 is heterogeneous in the step 7), the end face on barrier layer is positioned at same plane, specifically joins shown in Figure 5.Barrier layer 902 after the etching as shown in Figure 6, remaining barrier layer is positioned at upper surface and the sidewall of dimpling point.
In sum, the present invention proposes by the covering of the Seed Layer around dimpling point one deck etching barrier layer, like this when carrying out the Seed Layer etching, can protect the Seed Layer below it to avoid etching, thereby prevent the phenomenon of side direction undercutting.Improve reliability and the yields of the processing and manufacturing of dimpling point.
To those skilled in the art, obviously the invention is not restricted to the details of above-mentioned one exemplary embodiment, and under the situation that does not deviate from spirit of the present invention or essential characteristic, can realize the present invention with other concrete form.Therefore, no matter from which point, all should regard embodiment as exemplary, and be nonrestrictive, scope of the present invention is limited by claims rather than above-mentioned explanation, therefore is intended to include in the present invention dropping on the implication that is equal to important document of claim and all changes in the scope.Any Reference numeral in the claim should be considered as limit related claim.
In addition, be to be understood that, though this specification is described according to execution mode, but be not that each execution mode only comprises an independently technical scheme, this narrating mode of specification only is for clarity sake, those skilled in the art should make specification as a whole, and the technical scheme among each embodiment also can form other execution modes that it will be appreciated by those skilled in the art that through appropriate combination.
Claims (8)
1. prevent the method for dimpling point side direction undercutting in the dimpling point manufacture process, it is characterized in that, comprising:
S1, form pad at the semiconductor-based end;
S2, form dielectric layer at pad and semiconductor-based basal surface, offer window on the described dielectric layer, described window is corresponding with pad;
S3, form Seed Layer on the surface of dielectric layer and pad;
S4, form the dimpling point at described Seed Layer electroplating surface;
S5, the Seed Layer around the dimpling point in the certain distance form the barrier layer, and described certain distance satisfies: after the etching of step s6, the end of Seed Layer just and the justified margin of dimpling point or be positioned at the outside of dimpling point;
S6, etching are not blocked the Seed Layer that layer covers;
S7, reflux solder.
2. prevent the method for dimpling point side direction undercutting in the dimpling point manufacture process according to claim 1, it is characterized in that: described step s5 specifically comprises: the surface in dimpling point and Seed Layer forms the barrier layer, graphical described barrier layer, and make the barrier layer stay be covered at least on the interior Seed Layer of certain distance around the dimpling point.
3. prevent the method for dimpling point side direction undercutting in the dimpling point manufacture process according to claim 2, it is characterized in that: described graphical barrier layer adopts photoetching process to carry out, by the barrier layer in the certain distance around the barrier layer above the photoetching reservation dimpling point and the dimpling point, this moment, the material on described barrier layer was light-sensitive material, among the described step s7 of certain distance, also comprise the step of removing the barrier layer.
4. prevent the method for dimpling point side direction undercutting in the dimpling point manufacture process according to claim 2, it is characterized in that: described graphical barrier layer adopts dry etch process to carry out, only keep the barrier layer in the certain distance around the dimpling point by dry etching, this moment, the material on described barrier layer was polymeric material.
5. prevent the method for dimpling point side direction undercutting in the dimpling point manufacture process according to claim 4, it is characterized in that: described polymeric material is PI or PBO.
6. prevent the method for dimpling point side direction undercutting in the dimpling point manufacture process according to claim 1, it is characterized in that: also be formed with a layer insulating at described the semiconductor-based end, described pad is positioned on this insulating barrier, and described insulating barrier material is selected from silica or carborundum.
7. prevent the method for dimpling point side direction undercutting in the dimpling point manufacture process according to claim 1, it is characterized in that: described dimpling point is copper tin dimpling point.
8. prevent the encapsulating structure of dimpling point side direction undercutting in the dimpling point manufacture process, one layer insulating is arranged at semiconductor-based the end, preparation has metal pad on the insulating barrier, electroplate one deck Seed Layer on the metal pad, preparation has the dimpling point on the Seed Layer, it is characterized in that: cover etching barrier layer on the Seed Layer around the dimpling point, the Seed Layer that is covered by described etching barrier layer in its end behind over etching just and the justified margin of dimpling point or be positioned at the outside of dimpling point.
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| CN201310182205.1A CN103311131B (en) | 2013-05-15 | 2013-05-15 | The method of micro convex point side direction undercutting is prevented in a kind of micro convex point manufacture process |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103762197A (en) * | 2013-12-24 | 2014-04-30 | 华进半导体封装先导技术研发中心有限公司 | Method for manufacturing novel Damascus copper and copper bonding structure |
| CN103943578A (en) * | 2014-04-04 | 2014-07-23 | 华进半导体封装先导技术研发中心有限公司 | Copper column protruding point structure and forming method |
| CN105810601A (en) * | 2016-04-19 | 2016-07-27 | 南通富士通微电子股份有限公司 | Semiconductor chip packaging structure and manufacturing method thereof |
| CN112045329A (en) * | 2020-09-07 | 2020-12-08 | 中国电子科技集团公司第二十四研究所 | Flip-chip bonding process method for ball mounting on metal substrate |
Citations (11)
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| CN112045329A (en) * | 2020-09-07 | 2020-12-08 | 中国电子科技集团公司第二十四研究所 | Flip-chip bonding process method for ball mounting on metal substrate |
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