CN103326712B - A kind of clock multiselect one circuit and multiselect one method - Google Patents

Abstract

The invention discloses a clock multi-select one circuit and a multi-select one method, which belong to the technical field of clock selection in aerospace electronic systems. The clock multi-selection circuit is composed of a clock counter module, a clock selection signal generator module and a clock selector module in series; the field programmable logic gate array is used to independently and reliably screen multiple clock sources of the same frequency. The clock counter module performs cycle counting on each input clock signal, the clock selection signal generator module detects the validity of the clock signal and outputs the clock selection signal, and the clock selector module selects the input clock signal and outputs one of the clock signals. The present invention uses triple-mode redundancy technology for the registers in the circuit, which enhances the reliability of the circuit when the single event reversal effect occurs, solves the problem of false detection in the current technology when performing many-to-one detection of the same frequency clock, and reduces the System cost, complexity and coupling degree improve system efficiency and reliability.

Description

A clock multiple selection one circuit and multiple selection one method

technical field

The invention belongs to the technical field of clock selection in aerospace electronic systems, and in particular relates to a clock multiple selection circuit and a multiple selection method realized by using a field programmable logic gate array (FPGA).

Background technique

Due to the high reliability requirements of aerospace technology, in order to ensure the performance of aerospace electronic systems, a 1+1 backup scheme is usually adopted. For some important units, such as FPGA clocks, their operating status is related to whether the system can work normally. Multiple backups will also be used. For the technology of selecting one of the multiple clock sources of the FPGA as an effective clock, the FPGA is required to be able to do it automatically without the assistance of other system units, so as to reduce the complexity and coupling of the system and enhance the reliability.

Since the aerospace electronic system works in a space environment and is affected by high-energy particles, when it impacts the internal memory of the system, a single event upset (SEU) may occur, that is, some data bits in the internal memory of the system change from 0 to 1 or from 1 becomes 0. When SEU occurs in certain key data bits, it will affect the working state of the spacecraft, such as changing the control amount of the magnetic torque device, which in turn affects the control torque of the spacecraft, and finally leads to the attitude deviation of the spacecraft. Therefore, it is necessary to take anti-SEU protection measures for some key memories.

The main function of the same-frequency clock selection technology is to select an effective clock as the system clock from the mutually backup clocks, so as to avoid the impact of a certain clock failure and enhance the reliability of the system. Currently, there are two main schemes for clock selection techniques:

The first scheme is to use the assistance of other units in the system to select the clock.

According to different implementation methods, this scheme can be roughly divided into two ways: mainly relying on hardware assistance and mainly relying on software assistance.

The implementation method mainly relying on hardware assistance is to add a high-reliability clock in addition to the clock to be selected to detect whether each clock signal is valid, and then select the valid clock as the system clock.

The disadvantage of this method is that the added detection clock is required to have a sufficiently high reliability, which increases the cost. At the same time, it also has the problem of backup and selection, which increases the complexity of the system.

Mainly rely on the software-assisted implementation method to complete through the cooperation of the operating system and the FPGA. A flag register that is periodically set by the detected clock signal (that is, the detected clock signal) and periodically reset by the operating system is set inside the FPGA. The operating system The period of reset is greater than the period of setting of the detected clock signal. If the detected clock signal is valid at this time, the detected clock signal has already set the flag register before the next reset of the operating system. Read the status of the flag register before reset to detect whether the clock signal of this channel is valid, and then select the valid clock as the system clock.

The disadvantage of this method is that it increases the workload of the central processing unit (CPU) and the degree of system coupling, increases the burden on the system, and reduces the work efficiency.

The second solution is to perform frequency division and mutual inspection of the two clock signals according to the above-mentioned principle mainly relying on the software-assisted method, so as to detect the working status of the two clock signals, and then select an effective clock as the system clock.

The method is outlined as follows: the first clock signal sets the first flag register once in each clock cycle, the second clock signal sets the second flag register once in each clock cycle, and the two clock signals After frequency division, the first reset signal and the second reset signal are correspondingly obtained. The first reset signal resets the second flag register once in each reset cycle, and the second reset signal resets the first flag register in each reset cycle. Once reset, the reset period is greater than the set period of the clock signal. At this time, if it is detected that the first flag register has been set before each reset of the second reset signal, it indicates that the first clock signal is valid, otherwise it indicates that the first clock signal is valid. The signal is invalid, and the detection of the validity of the second clock signal is the same, and finally an effective clock is selected as the system clock according to the detection result.

Although this method gets rid of the dependence on other system units, a detection error will occur when the number of clocks to be selected exceeds 2. For example, if the number of clocks to be selected is 3, two clock signals are used to detect the other clock signal. The reset signal generated by the clock signal acts at different times. If the time interval between the two reset signals is less than the period of the detected clock, it is possible that the detected clock signal has not set the flag register after the reset of the previous reset signal is completed. It is found that the checked flag register is not set before the reset signal is reset, so it is wrongly judged that the checked clock signal is invalid.

To sum up, the first solution cannot independently select the clock, and requires additional system units to assist, which increases system cost, complexity and coupling, and fails to effectively improve system reliability. There are false detections in the many-to-one detection of the clock, and at the same time, the above two solutions do not highlight the anti-SEU design.

Contents of the invention

The object of the present invention is to aim at the deficiencies in the prior art, and provide a clock multi-choice circuit and a multi-choice method, through which the circuit can autonomously and reliably screen multiple clock sources of the same frequency, with high reliability, It has the advantages of strong independence and single event reversal effect fault tolerance; it is characterized in that: the clock multi-selection circuit is composed of a clock counter module, a clock selection signal generator module and a clock selector module in series; wherein, the clock counter module, It is used to count the cycle of each input clock signal; the clock selection signal generator module is used to detect the validity of the clock signal and output the clock selection signal; the clock selector module is used to select the input clock signal, the clock selector module Contains a multiplexer, the input of which is all the clock signals to be selected, and a certain channel is selected as the output clock signal controlled by the clock selection signal; the clock multi-selection circuit sets m input clock signals, and m≥2, the first channel The clock signal to the m-th clock signal are respectively denoted as clk1 to clkm; the clock multi-selection circuit uses FPGA to independently select one effective clock signal from two or more than two input clock signals of the same frequency as the output clock signal, and the circuit The registers used in use three-mode redundancy technology for anti-SEU protection; the three-mode redundancy technology is a commonly used fault-tolerant technology, that is, three modules perform the same operation, and the output adopts two out of three, as long as the same error does not occur at the same time Two of the modules can shield the influence of the faulty module.

The clock counter module includes m cycle counters, called clock counters, which are used to count cycles from 0 to n for each input clock signal, and n is any integer greater than 2; wherein the cycle counter is triggered by a rising edge Mode, that is, the rising edge of the input clock signal triggers a count, and the counter adds 1.

The clock selection signal generator module includes a main state machine and m-1 sub-state machines, the main state machine is used to control the conversion of the detection state, and the sub-state machine is used to perform the detection of the validity of a certain clock signal; During operation, the states of the main state machine and the sub-state machines match each other.

The main state machine is composed of m states such as clk1 detection, clk2 detection to clk(m-1) detection, and clkm selection, and outputs a clock selection signal in each state, which matches the detected clock signal and is used to control The clock selector module selects the detected clock signal as the output clock signal; when a certain clock signal detects that the detected clock signal is in an invalid state, a state transition occurs, that is, the state transition condition of the state machine is any one of the m-1 sub-state machines Entering the next state, the state transition sequence is clk1 detection, clk2 detection to clk(m-1) detection, and clkm selection; the clkm selection state is the termination state, and the state transition direction is irreversible and acyclic.

The m-1 sub-state machines are respectively driven by clock signals clk2 to clkm, and when a certain road clock signal is invalid, the corresponding sub-state machine stays in the state when the clock signal fails; corresponding to the sub-state of a certain road clock signal clkx The machine has x states, 2≤x≤m; when it is detected that the detected clock is invalid or the main state machine enters the next state, a state transition occurs, and the transition sequence is clk1 detection, clk2 detection to clk(x-1) detection , clkx selection, wherein the clkx selection state is the termination state, and the state transition direction is irreversible and acyclic.

When the main state machine is in the detection state of a certain clock signal clkx, the clock signal clk(x+1) to clkm is used to drive the corresponding sub-state machine to detect the state of clkx.

The sub-state machine includes a first comparison register, a second comparison register and a detected clock invalid counter.

The first comparison register and the second comparison register are used to register the value of the clock count register corresponding to the detected clock signal at intervals of two clock cycles; wherein, the first comparison register is in each state, when driving the sub-state machine When the value of the driving clock count register corresponding to the clock signal of the clock signal is 0, store the value of the detected clock count register; in each state, when the value of the driving clock count register is 2, store the value of the detected clock count register The value of the clock count register.

The invalid counter of the detected clock is used to record the number of times that the detected clock signal is continuously invalid during the inspection process, and is provided with a counting upper limit value. The signal is in an invalid state.

The initial value of the invalid counter of the detected clock is 0, and it is cleared when the state is transferred. When the value of the driving clock count register is 3, its own value is less than the counting upper limit and the state of the sub-state machine is not driven by the main state machine. , if the value of the first comparison register is the same as that of the second comparison register, it is determined that the detected clock signal is invalid once, and the detected clock invalid counter is increased by 1; if they are different, the detected clock invalid counter is 0.

When the sub-state machine detects that the detected clock signal is invalid or the main state machine enters the next state, a state transition occurs, that is, the state transition condition is that the main state machine enters the next state or the count value of the detected clock invalid counter is accumulated to the counting upper limit value.

The clock counting register, the main state machine state register, the sub-state machine state register, the clock selector, the first comparison register, the second comparison register and the invalid counter of the detected clock in the clock multi-choice circuit all adopt triple-mode redundancy technology .

A method for multiple selection of one clock in a clock multiple selection circuit, the method comprises the following steps:

1) Assuming that the number of input clock signals is m, the priority selection sequence is clk1, clk2 to clkm, and the detection logic is designed to use a clock with a low priority to detect a clock with a high priority, that is, to detect a certain clock signal clkx , use clk(x+1) to clkm to detect the state of clkx; respectively trigger an n+1 base counter with m clock signals to be selected, and take the value of the counter each time the interval is greater than 1 and less than 3 clock cycles , compare the similarities and differences of the two values, if they are the same, it means that the detected clock signal is invalid in one detection, and if they are different, it means that the detected clock signal is valid in one detection;

2) A main state machine controls the detection state from clk1 detection, clk2 detection to clk(m-1) detection, clkm selection, and outputs a clock selection signal in each state to control the clock selector module to select the detected clock signal as the output clock Signal, from clk2 to clkm to drive a sub-state machine to detect the corresponding detected clock signal in different states, the sub-state machine corresponding to a certain clock signal clkx is detected by clk1, clk2 until clk (x-1) detection, clkx selection and other x states constitute;

3) The state transition of the main state machine is driven by the state transition of a sub-state machine, and the state transition of the main state machine drives the state transition of the other sub-state machines. The states of the main state machine and sub-state machines match each other during operation. The state transition direction is irreversible and acyclic;

4) The main state machine and the m-1 sub-state machines corresponding to clk2 to clkm enter the clk1 detection state, and the count value of the detected clock invalid counter in all the sub-state machines used for detection is 0, and the circuit selects clk1 as the output clock signal, The sub-state machine is driven by the corresponding clock signal and the interval is greater than 1 and less than n clock cycles. Each takes the value of the clk1 counter and compares it. If they are the same, the detected clock invalid counter of the sub-state machine is increased by 1. If they are different, the counter is detected. The clock invalid counter is cleared;

5) If the count value of the detected clock invalid counter in the m-1 state machine does not reach the counting upper limit, the circuit remains in the clk1 detection state, and when the count value reaches the counting upper limit in a certain state machine value, the road sub-state machine switches to the clk2 detection state, and the main state machine follows and enters the clk2 detection state, and drives the remaining m-2 road sub-state machines to enter the clk2 detection state;

6) After entering the clk2 detection state, the count value of the detected clock invalid counter in all sub-state machines used for detection is 0, and the circuit selects clk2 as the output clock signal, except that the sub-state machine driven by clk2 enters the termination state and does not perform detection. The remaining m-2 road sub-state machines detect clk2 under the drive of the corresponding clock signal, and repeat the corresponding detection parts in steps 2) and 3);

7) When the circuit enters the detection state of a certain clock signal clkx, the circuit selects clkx as the output clock signal, and clk(x+1) to clkm have an effect on the detection of clkx, and execute in this order until the circuit is in the clkm selection state, That is, select clkm as the termination state of the output clock signal.

The beneficial effect of the present invention is to use the characteristics of the clock signal periodically changing the state of the counter as the detection basis, use the multiplexer as the execution device for clock signal selection, rely on the state machine to realize the many-to-one detection of the clock signal and output the clock selection signal. It can automatically and reliably perform many-to-one detection and clock screening of the same frequency clock, and through the use of triple-mode redundancy technology for the registers in the circuit, the reliability of the circuit when the single event reversal effect occurs is enhanced, which solves the current technical needs There is a problem of misdetection when additional system units are used for assistance or many-to-one detection of the same frequency clock, which reduces system cost, complexity and coupling, and improves system performance and reliability.

Description of drawings

Figure 1 is a structural block diagram of a clock multi-choice circuit.

Fig. 2 is a flow chart of a method for choosing one from multiple clocks.

Figure 3 is a block diagram of the circuit principle of the clock counter module.

Figure 4 is a block diagram of the circuit of the clock selector module.

FIG. 5 is a state transition diagram of the main state machine of the clock selection signal generator module.

FIG. 6 is a state transition diagram of the sub-state machine of the clock selection signal generator module.

Fig. 7 is a detection flow chart of the clk1 detection state in the clk3 sub-state machine of the clock selection signal generator module.

detailed description

The invention provides a clock multiple selection circuit and multiple selection method. The present invention will be described in further detail below in conjunction with the accompanying drawings.

Fig. 1 shows the structural block diagram of clock multiple selection one circuit, and this circuit is made up of clock counter module 100, clock selection signal generator module 300 and clock selector module 200 in series;

Assuming that the number of input clock signals is m and m≥2, the first clock signal to the mth clock signal are recorded as clk1 to clkm respectively. For the convenience of explanation, the clock counters corresponding to each clock signal are taken as quaternary cycle counters, each The counting upper limit value of the detected clock invalid counter in the sub-state machine is set to 7;

Described clock counter module comprises m quaternary counter modules, is used for carrying out the cycle count from 0 to 3 to each road input clock signal, and the counter module corresponding to certain road clock signal clkx is called clkx counter, as clk1 counter 110, clk2 counter 120, clk3 counter 130, clkm counter 140, each counter uses a 6-bit counting register to form a three-mode redundancy; the quaternary counter is a rising edge trigger mode, that is, the rising edge of the input clock signal triggers a count, and the counter adds 1.

Taking m equal to 3 as an example, the functional block diagram of the clock counter module circuit is shown in Figure 3:

Three-way clock signal clk1, clk2, clk3 input described clock counter module as candidate clock signal, respectively trigger clk1 quaternary counter 111, clk2 quaternary counter 121, clk3 quaternary counter 131 to carry out quaternary counting, corresponding The clock counting registers of the clock signal clk1 are clk1_cnt1, clk1_cnt2, and clk1_cnt3, all of which are two-bit registers; when clk1 is valid, its rising edge triggers the addition of 1 to clk1_cnt1, clk1_cnt2, and clk1_cnt3, and the three counting registers are judged by the two-out-of-three judgment module 112 The output clk1_cnt can get the value of the counter; when the value of clk1_cnt is 3, if clk1 is valid, it will trigger clk1_cnt1, clk1_cnt2, clk1_cnt3 to return to the initial value 0, and restart a new round of counting, thus achieving three clk1 quaternary counting under modular redundancy protection, the counting principles of the other two clock signals are the same as clk1; when a certain clock signal is invalid, the corresponding counter counting will not be triggered, and the value of the counter stays in the state when the clock signal is invalid; clk1_cnt , clk2_cnt, clk3_cnt are sent to the clock selection signal generator module as output.

The clock selector module is used to select the input clock signal, and includes a multiplexer, the input of which is all the clock signals to be selected, and a certain channel is selected as the output clock signal by the control of the clock selection signal.

Taking m equal to 3 as an example, the circuit schematic diagram of the clock selector module is shown in Figure 4:

The three-way clock signals clk1, clk2, and clk3 are input to the multiplexer 210 as the clock signal to be selected. When the value of the clock selection signal cs is binary number 00, the output clock signal clk_out is clk1; when the value of the clock selection signal cs is When the binary number is 01, the output clock signal clk_out is clk2; when the value of the clock selection signal cs is binary number 10, the output clock signal clk_out is clk3.

The clock selection signal generator module is used to detect the validity of the clock signal and output the clock selection signal. Its input is the clock signal to be selected in the m road and the count value of the corresponding clock count register, and the output is the clock selection signal cs, including a main state machine and m-1 sub-state machines.

The main state machine is used to control the transition of the detection state, and a state transition occurs when a certain clock signal detects that the detected clock signal is in an invalid state.

The sub-state machine is used to detect the validity of a certain clock signal, and a state transition occurs when the detected clock signal is detected to be invalid or the main state machine enters the next state.

The states of the main state machine and the sub-state machines match each other during operation.

Taking m equal to 3 as an example, the working principles of the main state machine and sub-state machine of the clock selection signal generator module are shown in Figure 5 and Figure 6:

As shown in Figure 5, the main state machine is composed of three states of clk1 detection 500, clk2 detection 510 and clk3 selection 520, each state outputs a clock selection signal cs, which matches the detected clock signal for The control clock selector module selects the detected clock signal as the output clock signal. For example, when the main state is in the clk1 detection state, the value of the clock selection signal cs is binary number 00. At this time, the output clock signal clk_out is clk1; the state machine conversion conditions are different The state is different. In the clk1 detection state, because clk2 and clk3 both detect the validity of clk1, any sub-state machine corresponding to the two will enter the next state and drive the main state machine to enter the next state, that is, state transition The condition is that c_st2 or c_st3 is equal to the binary number 01. In the clk2 detection state, because only clk3 detects the validity of clk2, only when the clk3 sub-state machine enters the next state, the main state machine will follow and enter the next state, that is, the state The conversion condition is that c_st3 is equal to the binary number 10;

As shown in Figure 6, described clk2 sub-state machine is driven by clock signal clk2, if clk2 is invalid then this sub-state machine stays in the state when clk2 fails, and it is made up of two states that clk1 detects 600 and clk2 selects 610, when sub-state machine When in the clk1 detection state, the detection of the validity of clk1 is performed, and the state transition condition is that c_st0 is equal to the binary number 01 or the value of the invalid counter clk2_noclk_cnt of the detected clock is 7. When the sub-state machine is in the clk2 selection state, it maintains a fixed state. The effectiveness of the clock signal is not detected; the clk3 sub-state machine is driven by the clock signal clk3, and its work is affected by the clk3 state equally, and it is composed of three states selected by clk1 detection, clk2 detection and clk3, when the sub-state machine is in clk1 or When clk2 detects the state, it executes the detection of the validity of clk1 or clk2. The state transition condition is that c_st0 is equal to the binary number 01 or the value of the invalid counter clk3_noclk_cnt of the detected clock is 7. When the sub-state machine is in the clk3 selection state, the working state is similar to clk2 selection state;

It can be seen from Figure 5 and Figure 6 that the state registers of the main state machine are c_st01, c_st02, and c_st03, all of which are two-bit registers, and the output c_st0 of the three registers after the two-out-of-three judgment is the state flag of the main state machine. When the value of c_st0 is binary number 00, the main state machine is in clk1 detection state, when the value of c_st0 is binary number 01, the main state machine is in clk2 detection state, when the value of c_st0 is binary number 10, the main state machine is in In the clk3 selection state, the clock selection signal cs is obtained after three out of three clock selection registers cs1, cs2, and cs3 in the main state; the same principle, the state registers c_st21, c_st22, and c_st23 of the clk2 sub-state machine are out of three The output c_st2 after the judgment is the state flag of the clk2 sub-state machine, and the output c_st3 after the state register c_st31, c_st32, and c_st33 of the clk3 sub-state machine are judged to be two out of three is the state flag of the clk3 sub-state machine.

After the clock multi-choice circuit is powered on and reset, the main state machine and sub-state machine of the clock selection signal generator module enter the initial state of detecting the clock signal clk1, taking m equal to 3 as an example, clk2 and clk3 respectively execute For the detection of the validity of clk1, take the detection of clk1 by clk3 as an example to illustrate the process of a clock signal combined with a state machine to detect the validity of the detected clock signal, as shown in Figure 7:

The first comparison register reg_clk3_01, reg_clk3_02, reg_clk3_03, the second comparison register reg_clk3_21, reg_clk3_22, reg_clk3_23 and the detected clock invalid counter (octal system) clk3_noclk_cnt1, clk3_noclk_cnt2, clk3_noclk_cnt3 are used for detection. The above registers use triple-mode redundancy technology. The corresponding two-out-of-three judgment output is reg_clk3_0, reg_clk3_2 and clk3_noclk_cnt, and the initial value of each register is 0;

After power-on reset, the main state machine and the sub-state machine enter the clk1 detection state, execute step 701, clk3 drives the clk3 sub-state machine to first judge the value of clk3_cnt;

When the value of clk3_cnt is 0, execute step 702 to assign the value of clk1_cnt to the first comparison registers reg_clk3_01, reg_clk3_02, reg_clk3_03;

When the value of clk3_cnt is 2, execute step 703 to assign the value of clk1_cnt to the second comparison registers reg_clk3_21, reg_clk3_22, reg_clk3_23;

When the value of clk3_cnt is 3, execute step 704, first judge whether c_st0 is binary number 01 or whether clk3_noclk_cnt counts to 7;

If not, it indicates that the main state machine has not entered the next state (clk2 detection) and the number of detections that clk1 is invalid has not reached the preset limit (7 times), then the clk3 sub-state machine will continue to stay in the clk1 detection state, and execute step 705 , so that the values of c_st31, c_st32, and c_st33 are binary numbers 00, and then step 706 is executed to determine whether the values of reg_clkx_0 and reg_clkx_2 are the same; since the values of reg_clk3_0 and reg_clk3_2 are the count values of two clock cycles of clk1_cnt, and when clk1 is valid, it will Change the value of clk1_cnt once every clock cycle. At this time, if reg_clk3_0 and reg_clk3_2 reciprocate, it proves that clk1 is valid. Go to step 707, and clk3_noclk_cnt1, clk3_noclk_cnt2, and clk3_noclk_cnt3 take the value of 0. If reg_clk3_0 and reg_clk3_2 are the same, it proves that clk1 has a detection invalid , execute step 708, add 1 to clk3_noclk_cnt1, clk3_noclk_cnt2, clk3_noclk_cnt3;

If it is judged that c_st0 is a binary number 01, it indicates that the clk2 sub-state machine has driven the main state machine to enter the clk2 detection state. At this time, step 709 is executed. 0 value, then execute step 710, the clk3 sub-state machine enters in the clk2 detection state;

If it is judged that clk3_noclk_cnt counts to 7, it indicates that clk1 has been checked invalid for 7 consecutive times, and it is considered that clk1 is in an invalid state at this time, and steps 709 and 710 are performed at this time.

According to the above method, the corresponding clock signal is detected in each state. If the detected clock signal is valid, the main state machine and the sub-state machine remain in the current state. The clock selection signal cs selects the detected clock signal as output. If the detected clock signal is invalid, then the invalid clock signal is first detected to drive the main state machine and the other sub-state machines to switch to the next state.

To sum up, taking the number of input clock signals equal to 3 as an example, the relationship between the input clock signal and the output clock signal is:

If clk1 is effective, no matter what state clk2 and clk3 are in, the main and sub-state machines are in the state of clk1 detection, and the clock selection signal cs selects clk1 as the output clock signal;

When clk1 is invalid but clk2 and clk3 are both valid, it can be detected that clk1 is in an invalid state, thereby driving the main state machine to enter the clk2 detection state, and at the same time select clk2 as the output clock signal. In the detection state of clk2, the detected invalid The clock signal clk1 is considered as an unreliable clock source, and it is no longer enabled to detect other clock signals, so only clk3 with low priority is used to detect the validity of clk2;

At this time, the clk2 state machine enters the clk2 selection state, which is the termination state of the clk2 state machine. In this state, the values of c_st21, c_st22, and c_st23 are binary numbers 01, and the first comparison register, the second comparison register, and The invalid counters of clock detection are all set to 0, and there are no other actions;

When only clk2 is valid, it can also detect that clk1 is invalid and the main state machine enters the clk2 detection state. At this time, clk2 is selected as the output clock signal. Since clk3 is invalid, it stays in the clk1 detection state and will not affect the normal operation of the circuit. ;

When only clk3 is effective, it can detect that clk1 and clk2 are invalid so that the main state machine enters the clk3 selection state. At this time, clk3 is selected as the output clock signal, which is the termination state of the main state machine when the number of input clock signals is 3.

The above-mentioned relationship between the input clock signal and the output clock signal is shown in Table 1, wherein 1 indicates that the clock signal is in a valid state, 0 indicates that the clock signal is in an invalid state, and X indicates that the clock signal is in any state.

Table 1 Relationship between input clock signal and output clock signal (the number of input clock signals is equal to 3)

Below in conjunction with Fig. 2, the clock selection and detection process of the present invention are described:

First enter step 400, the clock selection signal cs controls the clock selector to select clk1 as the output clock signal, and clk2 to clkm detect the validity of clk1;

Then enter step 410, judge whether clk1 is in valid state, if clk1 is valid, then return to step 400, if clk1 is invalid, then enter step 420;

After entering step 420, the clock selection signal cs controls the clock selector to select clk2 as the output clock signal, and clk3 to clkm detect the validity of clk2;

According to the above steps, when detecting a certain clock signal clkx, enter step 430, the clock selection signal cs controls the clock selector to select clkx as the output clock signal, clk (x+1) to clkm detect the validity of clkx, and then Enter step 440 when the detection result is judged, if clkx is valid, then return to step 430, if clkx is invalid, then enter the next step;

Perform the above steps in sequence until clk(m-1) is detected and enter step 450, the clock selection signal cs controls the clock selector to select clk(m-1) as the output clock signal, and clkm detects the validity of clk1;

Then enter step 460, judge whether clk (m-1) is in a valid state, if clk (m-1) is valid, then return to step 450, if clk (m-1) is invalid, then enter step 470;

Step 470 is the last step, the clock selection signal cs controls the clock selector to select clkm as the output clock signal.

The above method is executed sequentially, and the clock signal that has been detected to be invalid is identified as an unreliable clock source, and its influence is deliberately avoided in the subsequent steps. If a certain detection clock signal fails during the detection process, since the state transition direction of the main state machine and the sub-state machine in the clock selection signal generator module is irreversible and acyclic, and the states in the operation process of the two match each other, it does not It will affect the normal operation of the circuit, thus improving the fault tolerance and reliability of the clock multi-choice circuit.

It should be noted that the above specific implementation is mainly described by taking the number of input clock signals equal to 3 as an example, but those skilled in the art should understand that this method is also applicable to the case where the number of input clock signals is greater than 3 without other constraints. The situation, and the base of the clock counter and the counting upper limit of the invalid counter of the detected clock can also be adjusted according to the actual situation.

The above content shows that the circuit can independently and reliably screen multiple clock sources at the same frequency, and has the advantages of high reliability, strong independence, and fault tolerance for single event flipping effects. For those skilled in the art, any changes in form without departing from the idea of the present invention should be deemed to belong to the protection category of the present invention.

Claims (8)

1. A kind of clock multi-choice one circuit, described clock multi-choice one circuit is made up of clock counter module, clock selection signal generator module and clock selector module in series; Wherein, clock counter module is used for input clock signal to every road Carry out cycle counting; the clock selection signal generator module is used to detect the validity of the clock signal and output the clock selection signal; the clock selector module is used to select the input clock signal, and the clock selector module includes a multiplexer, which The input is all the clock signals to be selected, and a certain channel is selected as the output clock signal by the control of the clock selection signal; the clock multi-selection circuit sets m input clock signals, and m≥2, the first clock signal to the mth clock signal They are respectively recorded as clk1 to clkm; the clock multiple selection circuit uses FPGA to independently select one effective clock signal from two or more input clock signals of the same frequency as the output clock signal, and the registers used in the circuit use triple-mode redundancy Technology for anti-SEU protection, wherein, SEU single event flip; the triple-mode redundancy technology is a commonly used fault-tolerant technology, that is, the three modules perform the same operation, and the output uses two out of three, as long as the same error does not occur in one of them at the same time Two modules can shield the influence of the faulty module; the clock counter module includes m cycle counters, called clock counters, which are used to count cycles from 0 to n for each input clock signal, and n is greater than Any integer of 2, wherein the loop counter is a rising edge trigger mode, that is, the rising edge of the input clock signal triggers a count, and the counter adds 1; it is characterized in that the clock selection signal generator module includes a main state machine and m-1 A sub-state machine, the main state machine is used to control the conversion of the detection state, and the sub-state machine is used to perform the detection of the validity of a certain clock signal; in the running process, the state of the main state machine and the sub-state machine Mutual matching; the sub-state machine includes a first comparison register, a second comparison register and an invalid counter of the detected clock; The main state machine is composed of clk1 detection, clk2 detection to clk(m-1) detection and clkm selection total m states, each state outputs a clock selection signal, which matches the detected clock signal and is used to control The clock selector module selects the detected clock signal as the output clock signal; when a certain clock signal detects that the detected clock signal is in an invalid state, a state transition occurs, that is, the state transition condition of the state machine is any one of the m-1 sub-state machines Entering the next state, the state transition sequence is clk1 detection, clk2 detection to clk(m-1) detection, and clkm selection; the clkm selection state is the termination state, and the state transition direction is irreversible and acyclic. 2. according to the described a kind of clock multiple selection circuit of claim 1, it is characterized in that, described m-1 sub-state machines are respectively driven by clock signal clk2 to clkm, when a certain road clock signal is invalid, corresponding sub-state The machine stays in the state when the clock signal fails; the sub-state machine corresponding to a certain clock signal clkx has x states, 2≤x≤m; the state occurs when the detected clock is invalid or the main state machine enters the next state Transfer, according to the conversion sequence is clk1 detection, clk2 detection to clk(x-1) detection, clkx selection, wherein the clkx selection state is the termination state, and the state transition direction is irreversible and acyclic. 3. according to the described a kind of clock multiple selection circuit of claim 1, it is characterized in that, when described main state machine is in the detection state of a certain road clock signal clkx, use clock signal clk(x+1) to clkm to drive corresponding branch The state machine detects the clkx state. 4. A kind of clock multi-choice circuit according to claim 1, characterized in that, the first comparison register and the second comparison register are used to store the clock count register corresponding to the detected clock signal at intervals of two clock cycles Value; wherein, the first comparison register is in each state, when the value of the drive clock count register corresponding to the clock signal driving the sub-state machine is 0, the value of the clock count register is stored; the second comparison register In each state, when the value of the counting register of the driving clock is 2, the value of the counting register of the detected clock is stored. 5. A kind of clock multi-choice circuit according to claim 1, characterized in that, the invalid counter of the detected clock is used to record the number of times that the detected clock signal continuously appears invalid in the process of being detected, and is provided with a counter Limit value, when the number of consecutive invalid checks reaches the counting upper limit, the clock signal to be checked is deemed to be in an invalid state. 6. according to the described a kind of clock multiple selection circuit of claim 5, it is characterized in that, the initial value of the invalid counter of the detected clock is 0, cleared during state transfer, when the value of the drive clock counting register is 3, it takes When the value is less than the counting upper limit value and the state of the sub-state machine where it is located is not driven by the main state machine, if the value of the first comparison register is the same as that of the second comparison register, it is deemed that the detected clock signal is invalid once and the detected clock signal Invalid counter plus 1, if different, the invalid counter of the detected clock is 0. 7. according to the described a kind of clock multiple selection circuit of claim 5, it is characterized in that, state transition occurs when the sub-state machine detects that the detected clock signal is invalid or the main state machine enters the next state, that is, the state transition condition is The main state machine enters the next state or the count value of the detected clock invalid counter is accumulated to the count upper limit value. 8. A clock multi-choice method for a circuit, characterized in that the method comprises the following steps: 1) Assuming that the number of input clock signals is m, the priority selection sequence is clk1, clk2 to clkm, and the detection logic is designed to use a clock with a low priority to detect a clock with a high priority, that is, to detect a certain clock signal clkx , use clk(x+1) to clkm to detect the state of clkx; respectively trigger an n+1 base counter with m clock signals to be selected, and take the value of the counter each time the interval is greater than 1 and less than n clock cycles , compare the similarities and differences of the two values, if they are the same, it means that the detected clock signal is invalid in one detection, and if they are different, it means that the detected clock signal is valid in one detection; 2) A main state machine controls the detection state from clk1 detection, clk2 detection to clk(m-1) detection, clkm selection, and outputs a clock selection signal in each state to control the clock selector module to select the detected clock signal as the output clock Signal, respectively driven by clk2 to clkm a sub-state machine to detect the corresponding detected clock signal in different states, the sub-state machine corresponding to a certain clock signal clkx is detected by clk1, clk2 until clk(x-1) Detection and clkx selection consist of a total of x states; 3) The state transition of the main state machine is driven by the state transition of a sub-state machine, and the state transition of the main state machine drives the state transition of the other sub-state machines. The states of the main state machine and sub-state machines match each other during operation, The state transition direction is irreversible and acyclic; 4) The main state machine and the m-1 sub-state machines corresponding to clk2 to clkm enter the clk1 detection state, and the count value of the detected clock invalid counter in all the sub-state machines used for detection is 0, and the circuit selects clk1 as the output clock signal, The sub-state machine is driven by the corresponding clock signal and the interval is greater than 1 and less than n clock cycles. Each takes the value of the clk1 counter and compares it. If they are the same, the detected clock invalid counter of the sub-state machine is increased by 1. If they are different, the counter is detected. The clock invalid counter is cleared; 5) If the count value of the detected clock invalid counter in the m-1 road sub-state machine does not reach the counting upper limit, the circuit remains in the clk1 detection state, and when the count value reaches the counting upper limit in a certain road sub-state machine value, the road sub-state machine switches to the clk2 detection state, and the main state machine follows and enters the clk2 detection state, and drives the remaining m-2 road sub-state machines to enter the clk2 detection state; 6) After entering the clk2 detection state, the count value of the invalid counter of the detected clock in all sub-state machines used for detection is 0, and the circuit selects clk2 as the output clock signal, except that the sub-state machine driven by clk2 enters the termination state and does not detect. The remaining m-2 road sub-state machines detect clk2 under the drive of the corresponding clock signal, and repeat the corresponding detection part in steps 2) and 3); 7) When the circuit enters the detection state of a certain clock signal clkx, the circuit selects clkx as the output clock signal, and clk(x+1) to clkm play a role in the detection of clkx, and execute in this order until the circuit is in the clkm selection state, That is, select clkm as the termination state of the output clock signal.