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CN103354228A - Semiconductor packaging part and manufacturing method thereof - Google Patents

Semiconductor packaging part and manufacturing method thereof Download PDF

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Publication number
CN103354228A
CN103354228A CN2013102885895A CN201310288589A CN103354228A CN 103354228 A CN103354228 A CN 103354228A CN 2013102885895 A CN2013102885895 A CN 2013102885895A CN 201310288589 A CN201310288589 A CN 201310288589A CN 103354228 A CN103354228 A CN 103354228A
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chip
semiconductor package
substrate
molding compound
conductive
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陈峥嵘
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Samsung Semiconductor China R&D Co Ltd
Samsung Electronics Co Ltd
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Samsung Semiconductor China R&D Co Ltd
Samsung Electronics Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/48147—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked with an intermediate bond, e.g. continuous wire daisy chain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909—Post-treatment of the connector or wire bonding area
    • H01L2224/8592—Applying permanent coating, e.g. protective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

本发明提供了一种半导体封装件及其制造方法。所述半导体封装件包括：基底；芯片，位于基底上；粘合层，位于基底和芯片之间，将芯片附于基底；导电结构，分散在粘合层中，将芯片与基底电连接；导电模制化合物，包封芯片并且接地。根据本发明的半导体封装件，可以防止芯片受电磁波干扰，并且不需要增加额外的工艺。

Figure 201310288589

The invention provides a semiconductor package and a manufacturing method thereof. The semiconductor package includes: a substrate; a chip on the substrate; an adhesive layer located between the substrate and the chip to attach the chip to the substrate; a conductive structure dispersed in the adhesive layer to electrically connect the chip to the substrate; Molding compound, encapsulating the chip and grounding. According to the semiconductor package of the present invention, the chip can be prevented from being disturbed by electromagnetic waves, and no additional process needs to be added.

Figure 201310288589

Description

半导体封装件及其制造方法Semiconductor package and manufacturing method thereof

技术领域technical field

本申请涉及一种半导体封装件及其制造方法，更具体地讲，本申请涉及一种改善了电磁波屏蔽、信号完整性和散热效果的半导体封装件及其制造方法。The present application relates to a semiconductor package and a manufacturing method thereof, and more specifically, the present application relates to a semiconductor package with improved electromagnetic wave shielding, signal integrity and heat dissipation effects and a manufacturing method thereof.

背景技术Background technique

对于许多集成电路芯片来说，越来越多地使用高频信号。然而，高频信号经常伴随着信号完整性和电磁波屏蔽的问题。另外，对于功耗较大的半导体封装件，如何散热也是一个难题，例如，现有技术中经常使用散热胶等来散热。For many integrated circuit chips, high frequency signals are increasingly used. However, high frequency signals are often accompanied by issues of signal integrity and electromagnetic wave shielding. In addition, for semiconductor packages with high power consumption, how to dissipate heat is also a difficult problem. For example, in the prior art, heat dissipating glue and the like are often used to dissipate heat.

图1是根据现有技术的半导体封装件的示意图。参照图1，根据现有技术的半导体封装件包括：基底10；芯片11，位于基底10上，通过粘合层20附于基底10，并且通过键合引线14与引线框架12电连接；包封树脂15，包封芯片11；屏蔽层16，形成在包封树脂15的外表面上，以防止芯片10受到电磁波干扰。FIG. 1 is a schematic diagram of a semiconductor package according to the prior art. Referring to FIG. 1, a semiconductor package according to the prior art includes: a substrate 10; a chip 11, located on the substrate 10, attached to the substrate 10 through an adhesive layer 20, and electrically connected to a lead frame 12 through a bonding wire 14; The resin 15 encapsulates the chip 11 ; the shielding layer 16 is formed on the outer surface of the encapsulating resin 15 to prevent the chip 10 from being interfered by electromagnetic waves.

另外，根据现有技术的半导体封装件还包括接地焊盘18、竖直导电结构17和导电焊球19，其中，竖直导电结构17在接地焊盘18和屏蔽层16之间提供电连接，通过竖直导电结构17、屏蔽层16的一部分以及导电焊球19将接地焊盘18电连接到接地引线13。因此，虽然屏蔽层16仅形成在包封树脂15的外表面上，但是可以通过屏蔽层16形成从接地焊盘18到接地引线13的通路。In addition, the semiconductor package according to the prior art also includes a ground pad 18, a vertical conductive structure 17 and a conductive solder ball 19, wherein the vertical conductive structure 17 provides an electrical connection between the ground pad 18 and the shielding layer 16, The ground pad 18 is electrically connected to the ground lead 13 through the vertical conductive structure 17 , a portion of the shielding layer 16 and the conductive solder ball 19 . Therefore, although the shielding layer 16 is formed only on the outer surface of the encapsulation resin 15 , a passage from the ground pad 18 to the ground lead 13 can be formed through the shielding layer 16 .

即，根据现有技术的半导体封装件，为了防止电磁干扰，需要在包封树脂15的外表面上形成单独的屏蔽层16，从而需要单独的制造工艺，增加了制造成本。That is, according to the related art semiconductor package, in order to prevent electromagnetic interference, a separate shielding layer 16 needs to be formed on the outer surface of the encapsulation resin 15, thereby requiring a separate manufacturing process and increasing the manufacturing cost.

发明内容Contents of the invention

为了克服现有技术中的问题，本发明提供了一种半导体封装件，所述半导体封装件包括：基底；芯片，位于基底上；粘合层，位于基底和芯片之间，将芯片附于基底；导电结构，分散在粘合层中，将芯片与基底电连接；导电模制化合物，包封芯片并且接地。In order to overcome the problems in the prior art, the present invention provides a semiconductor package comprising: a substrate; a chip positioned on the substrate; an adhesive layer positioned between the substrate and the chip to attach the chip to the substrate ; a conductive structure, dispersed in the adhesive layer, electrically connects the chip to the substrate; and a conductive molding compound, encapsulating the chip and grounding.

根据本发明的实施例，所述半导体封装件还包括位于基底中的接地焊盘和位于基底下方的接地焊球，所述导电模制化合物经由接地焊盘电连接到接地焊球。所述粘合层由绝缘材料制成，防止芯片与导电模制化合物电连接。According to an embodiment of the present invention, the semiconductor package further includes ground pads in the substrate and ground balls under the substrate, the conductive molding compound being electrically connected to the ground balls via the ground pads. The adhesive layer is made of an insulating material and prevents the chip from being electrically connected to the conductive molding compound.

根据本发明的实施例，所述粘合层由聚对二甲苯制成。所述导电模制化合物由环氧树脂和金属导电颗粒制成或者由环氧树脂和导电化合物制成。According to an embodiment of the present invention, the adhesive layer is made of parylene. The conductive molding compound is made of epoxy resin and metal conductive particles or of epoxy resin and conductive compound.

本发明还提供了一种半导体芯片，所述半导体封装件包括：基底；芯片，位于基底上；键合引线，将芯片电连接到基底；绝缘层，覆盖芯片和键合引线；导电模制化合物，包封芯片并且接地，其中，绝缘层防止芯片和键合引线与导电模制化合物电连接。The present invention also provides a semiconductor chip, the semiconductor package comprising: a substrate; a chip on the substrate; bonding wires electrically connecting the chip to the substrate; an insulating layer covering the chip and the bonding wires; a conductive molding compound , encapsulating the chip and grounding, wherein the insulating layer prevents the chip and bonding wires from being electrically connected to the conductive molding compound.

本发明提供了一种半导体封装件的制造方法，所述制造方法包括以下步骤：提供基底；通过粘合层将芯片附于基底，并且通过设置在粘合层中的导电结构将芯片与基底电连接；用导电模制化合物包封芯片，并且所述导电模制化合物接地。The present invention provides a manufacturing method of a semiconductor package, the manufacturing method comprising the following steps: providing a substrate; attaching a chip to the substrate through an adhesive layer, and electrically connecting the chip to the substrate through a conductive structure disposed in the adhesive layer. Connecting; encapsulating the chip with a conductive molding compound and grounding the conductive molding compound.

本发明还提供了一种半导体封装件的制造方法，所述半导体封装件的制造方法包括以下步骤：提供基底；将芯片层叠在基底上方；通过键合引线将芯片电连接到基底；在芯片和键合引线上涂覆绝缘层；用导电模制化合物包封芯片，并且所述导电模制化合物接地。The present invention also provides a method for manufacturing a semiconductor package, which includes the following steps: providing a substrate; stacking a chip on the substrate; electrically connecting the chip to the substrate through bonding wires; An insulating layer is coated on the bonding wire; the chip is encapsulated with a conductive molding compound, and the conductive molding compound is grounded.

通过采用导电模制化合物来包封芯片，将芯片的背面与接地焊盘电连接，从而能够防止芯片受电磁波干扰，并且能够快速散热。因此，根据本发明，不需要另外的结构来防止电磁干扰，简化了结构，降低了制造成本。By encapsulating the chip with a conductive molding compound, the back of the chip is electrically connected to the ground pad, so that the chip can be prevented from being interfered by electromagnetic waves, and heat can be quickly dissipated. Therefore, according to the present invention, no additional structure is needed to prevent electromagnetic interference, the structure is simplified, and the manufacturing cost is reduced.

附图说明Description of drawings

通过结合附图详细描述本发明的实施例，本发明的许多特征和优点将变得更加清楚，在附图中：Many features and advantages of the present invention will become clearer by describing the embodiments of the present invention in detail in conjunction with the accompanying drawings, in which:

图1是根据现有技术的半导体封装件的示意图；1 is a schematic diagram of a semiconductor package according to the prior art;

图2是根据本发明第一示例性实施例的半导体封装件的剖视图；2 is a cross-sectional view of a semiconductor package according to a first exemplary embodiment of the present invention;

图3是根据本发明第二示例性实施例的半导体封装件的剖视图。3 is a cross-sectional view of a semiconductor package according to a second exemplary embodiment of the present invention.

具体实施方式Detailed ways

在下文中，将参照附图详细描述根据本发明实施例的半导体封装件。Hereinafter, a semiconductor package according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

图2是根据本发明第一示例性实施例的半导体封装件的剖视图。参照图2，根据本发明第一示例性实施例的半导体封装件包括：基底100；芯片130，位于基底100上，通过粘合层150附于基底100；导电结构140，分散在粘合层150中，将芯片130与基底100中的导电焊盘电连接；导电模制化合物160，包封芯片130，从而保护芯片130免受外部损坏；导电焊球，位于基底100下方，用于将芯片130电连接到外部电路。2 is a cross-sectional view of a semiconductor package according to a first exemplary embodiment of the present invention. Referring to FIG. 2, a semiconductor package according to a first exemplary embodiment of the present invention includes: a substrate 100; a chip 130, located on the substrate 100, attached to the substrate 100 through an adhesive layer 150; a conductive structure 140, dispersed in the adhesive layer 150 Among them, the chip 130 is electrically connected to the conductive pad in the substrate 100; the conductive molding compound 160 encapsulates the chip 130, thereby protecting the chip 130 from external damage; electrically connected to an external circuit.

根据本发明的第一示例性实施例，导电模制化合物160可以由环氧树脂和金属导电颗粒制成，或者可以由环氧树脂和其它导电化合物制成。导电模制化合物160将芯片130的背面经由接地焊盘120电连接到接地焊球110，从而作为半导体封装件的电磁波屏蔽组件并且能够起到优良的散热路径的作用。即，导电模制化合物160将芯片130的与附于基底100的表面相反的表面电连接到接地焊球110。其中，接地焊盘120位于基底100中，接地焊球110位于基底100下方，并且接地焊球110不与芯片130电连接。According to the first exemplary embodiment of the present invention, the conductive molding compound 160 may be made of epoxy resin and metal conductive particles, or may be made of epoxy resin and other conductive compounds. The conductive molding compound 160 electrically connects the backside of the chip 130 to the ground ball 110 via the ground pad 120 , thereby serving as an electromagnetic wave shielding component of the semiconductor package and capable of functioning as an excellent heat dissipation path. That is, the conductive molding compound 160 electrically connects the surface of the chip 130 opposite to the surface attached to the substrate 100 to the ground solder ball 110 . Wherein, the ground pad 120 is located in the substrate 100 , the ground solder ball 110 is located under the substrate 100 , and the ground solder ball 110 is not electrically connected to the chip 130 .

根据本发明的第一示例性实施例的半导体封装件，粘合层150由绝缘材料形成，从而防止芯片130的与基底100电连接的表面与模制化合物160电连接。According to the semiconductor package of the first exemplary embodiment of the present invention, the adhesive layer 150 is formed of an insulating material, thereby preventing the surface of the chip 130 electrically connected to the substrate 100 from being electrically connected to the molding compound 160 .

根据本发明第一示例性实施例的半导体封装件通过在芯片上方采用导电化合物来进行包封，导电化合物可以起到电磁波屏蔽和散热的作用，而不需要像现有技术中的单独的屏蔽层，从而可以采用简单的制造工艺得到半导体封装件。The semiconductor package according to the first exemplary embodiment of the present invention is encapsulated by using a conductive compound above the chip, and the conductive compound can play the role of electromagnetic wave shielding and heat dissipation without requiring a separate shielding layer as in the prior art , so that a semiconductor package can be obtained by using a simple manufacturing process.

下面将详细描述制造根据本发明第一示例性实施例的半导体封装件的方法，所述方法包括以下步骤：提供基底100；通过粘合层150将芯片130附于基底100，并且通过设置在粘合层150中的导电结构140将芯片130与基底100电连接；用导电模制化合物160包封芯片130，并且所述导电模制化合物接地。A method of manufacturing a semiconductor package according to a first exemplary embodiment of the present invention will be described in detail below, and the method includes the following steps: providing a substrate 100; attaching a chip 130 to the substrate 100 through an adhesive layer 150, and The conductive structure 140 in the lamination layer 150 electrically connects the chip 130 to the substrate 100; the chip 130 is encapsulated with a conductive molding compound 160, and the conductive molding compound is grounded.

图3是根据本发明第二示例性实施例的半导体封装件的剖视图。参照图3，根据本发明第二示例性实施例的半导体封装件包括：基底100；芯片130，层叠在基底100上方，芯片130通过键合引线170电连接到基底100中的导电焊盘；绝缘层180，覆盖芯片130以及键合引线170；导电模制化合物160，包封芯片130，从而保护芯片130免受外部损坏。3 is a cross-sectional view of a semiconductor package according to a second exemplary embodiment of the present invention. Referring to FIG. 3, a semiconductor package according to a second exemplary embodiment of the present invention includes: a substrate 100; a chip 130 stacked above the substrate 100, and the chip 130 is electrically connected to a conductive pad in the substrate 100 by a bonding wire 170; The layer 180 covers the chip 130 and the bonding wires 170; the conductive molding compound 160 encapsulates the chip 130, thereby protecting the chip 130 from external damage.

根据本发明第二示例性实施例的半导体封装件可以包括多个芯片，例如，可以包括两个芯片。The semiconductor package according to the second exemplary embodiment of the present invention may include a plurality of chips, for example, may include two chips.

根据本发明的第二示例性实施例，绝缘层180可以由聚对二甲苯形成，从而防止芯片130、键合引线170与导电模制化合物160电连接。According to the second exemplary embodiment of the present invention, the insulating layer 180 may be formed of parylene so as to prevent the chip 130 , the bonding wire 170 and the conductive molding compound 160 from being electrically connected.

根据本发明的第二示例性实施例，覆盖芯片130的绝缘层180的外表面（即，与绝缘层180接触芯片130的表面相反的表面）、导电模制化合物160、接地焊盘120电连接到接地焊球110，从而防止半导体封装件受电磁波的干扰，并且能够用作优良的散热路径。其中，接地焊盘120位于基底100中，接地焊球110位于基底100下方，并且接地焊球110不与芯片130电连接。According to the second exemplary embodiment of the present invention, the outer surface of the insulating layer 180 covering the chip 130 (that is, the surface opposite to the surface of the insulating layer 180 contacting the chip 130), the conductive molding compound 160, the ground pad 120 are electrically connected to the ground solder ball 110, thereby preventing the semiconductor package from being disturbed by electromagnetic waves, and can be used as an excellent heat dissipation path. Wherein, the ground pad 120 is located in the substrate 100 , the ground solder ball 110 is located under the substrate 100 , and the ground solder ball 110 is not electrically connected to the chip 130 .

另外，根据本发明的第二示例性实施例，半导体封装件还可以包括穿过绝缘层180形成的通孔190。导电模制化合物160填充通孔190，所以绝缘层180的外表面经由导电模制化合物160、通孔190、接地焊盘120电连接到接地焊球110，从而防止芯片130受电磁波干扰。In addition, according to the second exemplary embodiment of the present invention, the semiconductor package may further include a via hole 190 formed through the insulating layer 180 . The conductive molding compound 160 fills the via hole 190, so the outer surface of the insulating layer 180 is electrically connected to the ground solder ball 110 via the conductive molding compound 160, the via hole 190, and the ground pad 120, thereby preventing the chip 130 from being interfered by electromagnetic waves.

下面将详细描述根据本发明第二示例性实施例的半导体封装件的制造方法，所述制造方法包括以下步骤：提供基底100；将芯片130层叠在基底100上方；通过键合引线170将芯片130电连接到基底100；在芯片100和键合引线170上涂覆绝缘层180；用导电模制化合物160包封芯片130，并且所述导电模制化合物接地。The manufacturing method of the semiconductor package according to the second exemplary embodiment of the present invention will be described in detail below, the manufacturing method includes the following steps: providing the substrate 100; stacking the chip 130 on the substrate 100; Electrically connected to substrate 100; insulating layer 180 coated on chip 100 and bonding wires 170; chip 130 encapsulated with conductive molding compound 160 and grounded.

根据本发明的半导体封装件及其制造方法，通过采用导电模制化合物来包封芯片，将芯片的背面与接地焊盘电连接，从而能够防止芯片受电磁波干扰，并且能够快速散热。因此，根据本发明，不需要另外的结构来防止电磁干扰，简化了结构，降低了制造成本。According to the semiconductor package and its manufacturing method of the present invention, by encapsulating the chip with a conductive molding compound and electrically connecting the back of the chip to the ground pad, the chip can be prevented from being disturbed by electromagnetic waves and heat can be quickly dissipated. Therefore, according to the present invention, no additional structure is needed to prevent electromagnetic interference, the structure is simplified, and the manufacturing cost is reduced.

以上参照附图示例性地示出了本发明，本发明的范围由权利要求及其等同物限定。The present invention has been exemplarily illustrated above with reference to the accompanying drawings, and the scope of the present invention is defined by the claims and their equivalents.

Claims (10)

1.一种半导体封装件，其特征在于所述半导体封装件包括：1. A semiconductor package, characterized in that the semiconductor package comprises: 基底；base; 芯片，位于基底上；a chip on a substrate; 粘合层，位于基底和芯片之间，将芯片附于基底；An adhesive layer, located between the substrate and the chip, attaches the chip to the substrate; 导电结构，分散在粘合层中，将芯片与基底电连接；Conductive structures, dispersed in the adhesive layer, electrically connect the chip to the substrate; 导电模制化合物，包封芯片并且接地。Conductive molding compound, encapsulating the chip and grounding. 2.根据权利要求1所述的半导体封装件，其特征在于所述半导体封装件还包括位于基底中的接地焊盘和位于基底下方的接地焊球，所述导电模制化合物经由接地焊盘电连接到接地焊球。2. The semiconductor package according to claim 1, wherein the semiconductor package further comprises a ground pad in the substrate and a ground solder ball under the substrate, the conductive molding compound is electrically connected to the ground via the ground pad. Connect to ground ball. 3.根据权利要求1所述的半导体封装件，其特征在于所述粘合层由绝缘材料制成，防止芯片与导电模制化合物电连接。3. The semiconductor package according to claim 1, wherein the adhesive layer is made of an insulating material to prevent the chip from being electrically connected to the conductive molding compound. 4.根据权利要求3所述的半导体封装件，其特征在于所述粘合层由聚对二甲苯制成。4. The semiconductor package according to claim 3, wherein the adhesive layer is made of parylene. 5.根据权利要求1所述的半导体封装件，其特征在于所述导电模制化合物由环氧树脂和金属导电颗粒制成或者由环氧树脂和导电化合物制成。5. The semiconductor package according to claim 1, wherein the conductive molding compound is made of epoxy resin and metal conductive particles or epoxy resin and conductive compound. 6.一种半导体芯片，其特征在于所述半导体封装件包括：6. A semiconductor chip, characterized in that the semiconductor package comprises: 基底；base; 芯片，位于基底上；a chip on a substrate; 键合引线，将芯片电连接到基底；Bonding wires to electrically connect the chip to the substrate; 绝缘层，覆盖芯片和键合引线；An insulating layer, covering the chip and bonding wires; 导电模制化合物，包封芯片并且接地，conductive molding compound, encapsulating the chip and grounding, 其中，绝缘层防止芯片和键合引线与导电模制化合物电连接。Among other things, the insulating layer prevents the chips and bonding wires from being electrically connected to the conductive molding compound. 7.根据权利要求6所述的半导体封装件，其特征在于所述绝缘层由聚对二甲苯制成。7. The semiconductor package according to claim 6, wherein the insulating layer is made of parylene. 8.根据权利要求6所述的半导体封装件，其特征在于所述半导体封装件还包括位于基底中的接地焊盘和位于基底下方的接地焊球，所述导电模制化合物电连接到接地焊盘和接地焊球。8. The semiconductor package according to claim 6, wherein the semiconductor package further comprises a ground pad in the substrate and a ground solder ball under the substrate, the conductive molding compound is electrically connected to the ground pad pad and ground solder ball. 9.根据权利要求6所述的半导体封装件，其特征在于所述半导体封装件还包括穿过绝缘层的通孔，所述导电模制化合物经由所述通孔、接地焊盘电连接到接地焊球。9. The semiconductor package according to claim 6, wherein the semiconductor package further comprises a via hole through the insulating layer, the conductive molding compound is electrically connected to ground via the via hole, the ground pad Solder balls. 10.根据权利要求6所述的半导体封装件，其特征在于所述导电模制化合物由环氧树脂和金属导电颗粒制成或者由环氧树脂和导电化合物制成。10. The semiconductor package according to claim 6, wherein the conductive molding compound is made of epoxy resin and metal conductive particles or epoxy resin and conductive compound.
CN2013102885895A 2013-07-10 2013-07-10 Semiconductor packaging part and manufacturing method thereof Pending CN103354228A (en)

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Application publication date: 20131016