CN103378095A - Metal oxide semiconductor electrical parameter testing device and method of manufacture - Google Patents

Abstract

The invention discloses a metal oxide semiconductor electrical parameter testing device and a manufacturing method. The gate is a metal gate, and the first P-type well region and the first N+ region of the N-type substrate form a first PN structure to form a first diode. The second P-type well region of the N-type substrate and the second N+ region form a second PN structure to form a second diode, and the first diode and the second diode are connected in reverse parallel and connected to the gate to form an N-type metal oxide Semiconductor electrical parameter testing device; or, the N-type substrate and the first P+ region form a third PN structure to form a third diode, and the N-type substrate and the second P+ region form a fourth PN structure to form a fourth diode, and the third The first diode is connected in antiparallel with the fourth diode and connected with the gate to form a P-type metal oxide semiconductor electrical parameter testing device. The invention can well release the positive charge or negative charge introduced by the plasma damage, so that the change of the threshold voltage is small.

Description

A metal oxide semiconductor electrical parameter testing device and manufacturing method

technical field

The invention relates to the technical field of semiconductor manufacturing, in particular to a metal oxide semiconductor electrical parameter testing device and a manufacturing method.

Background technique

In modern semiconductor technology, especially in the manufacturing process of large-scale integrated circuits, in order to meet the special requirements of small-sized devices to avoid high-temperature thermal processes, more plasma processes are used in the production process. For example, active area etching, polysilicon gate etching, contact hole etching, metal wiring etching, passivation layer etching, etc. in the etching process; formation of metal wiring insulating layer, final passivation protection layer in thin film process formation etc.

When using the plasma process, it will inevitably bring some problems, such as plasma damage, film stress change, etc., plasma damage will introduce positive or negative charges into the gate insulating dielectric film, thereby changing the interface state and causing Individual device threshold voltage drift; film stress can also cause individual device threshold voltage drift.

Existing metal oxide semiconductor circuits mainly include composite metal oxide semiconductor devices and individual metal oxide semiconductor devices. In the composite metal oxide semiconductor device with polysilicon as the gate, due to the inherent characteristics of high polysilicon density, plasma damage and film stress have little effect on the interface state, so N-type metal oxide semiconductor devices and P-type metal oxide The variation of the threshold voltage of the material semiconductor device is small (|Δvt|<0.06v); but in the metal oxide semiconductor device with the metal as the gate, since the semiconductor device for monitoring the electrical parameters is a separate metal oxide semiconductor device, the gate There is no structure that releases charges. The damage caused by plasma etching metal and the passivation layer directly covering the surface of the metal gate have a great influence on the metal interface state, and the threshold voltage of metal oxide semiconductor devices changes greatly (|Δvt |)>0.06v).

Therefore, in the process of implementing the present invention, the inventor finds that the prior art has at least the following technical problems:

In metal-oxide-semiconductor devices with metal gates, if there is plasma damage, the introduced positive or negative charges cannot be released, and the interface state will be changed, resulting in a shift in the threshold voltage.

Contents of the invention

In order to solve the above-mentioned technical problems, the present invention provides a metal oxide semiconductor electrical parameter testing device and a manufacturing method, so that the positive charge or negative charge introduced by the metal oxide semiconductor electrical parameter testing device with metal as the gate can be released, improving Effect of voltage threshold changes due to plasma damage.

The invention provides a metal oxide semiconductor electrical parameter testing device, the gate of the semiconductor device is a metal gate, specifically,

The first P-type well region of the N-type substrate and the first PN structure formed by the first N+ region form the first diode, and the second P-type well region of the N-type substrate and the second N+ region form the second diode. The PN structure forms a second diode, the first diode is connected in antiparallel to the second diode, and is connected to the gate to form an N-type metal oxide semiconductor electrical parameter testing device; or,

The third PN structure formed by the N-type substrate and the first P+ region forms a third diode, the fourth PN structure formed by the N-type substrate and the second P+ region forms a fourth diode, and the third diode It is connected in antiparallel with the fourth diode and connected with the gate to form a P-type metal oxide semiconductor electrical parameter testing device.

The present invention also provides a method for manufacturing an N-type metal oxide semiconductor electrical parameter testing device, wherein the gate of the N-type metal oxide semiconductor electrical parameter testing device is a metal gate, and the method includes:

forming a first P-type well region on an N-type substrate;

Implanting N-type impurities into the first P-type well region to form a first N+ region;

A first PN structure formed by the first P-type well region and the first N+ region forms a first diode;

forming a second P-type well region on the N-type substrate;

Implanting N-type impurities into the second P-type well region to form a second N+ region;

A second PN structure formed by the second P-type well region and the second N+ region forms a second diode;

The first diode is connected in antiparallel with the second diode and connected to the gate to form an N-type metal oxide semiconductor electrical parameter testing device.

Another aspect of the present invention also provides a method for manufacturing a P-type metal oxide semiconductor electrical parameter testing device, the gate of the P-type metal oxide semiconductor electrical parameter testing device is a metal gate, and the method includes:

Implanting P-type impurities into the N-type substrate region to form a first P+ region;

The N-type substrate region and the first P+ region form a third PN structure to form a third diode;

Implanting P-type impurities into the N-type substrate region to form a second P+ region;

The N-type substrate region and the second P+ region form a fourth PN structure to form a fourth diode;

The third diode is connected in antiparallel to the fourth diode and connected to the gate to form a P-type metal oxide semiconductor electrical parameter testing device.

The beneficial effects of the present invention are as follows: in the metal oxide semiconductor electrical parameter testing device using metal as the gate, the gate and substrate of the N-type metal oxide semiconductor electrical parameter testing device or the P-type metal oxide semiconductor electrical parameter testing device Two parallel reverse diodes are formed at the bottom, which can well release the positive or negative charges introduced by the plasma damage, thereby improving the interface state, making the threshold voltage change smaller, and at the same time making the threshold test value actually reflect the semiconductor in the circuit. device threshold.

Description of drawings

Figure 1a is a schematic structural diagram of an N-type metal oxide semiconductor electrical parameter testing device in an embodiment of the present invention;

Figure 1b is a schematic structural diagram of a P-type metal oxide semiconductor electrical parameter testing device in an embodiment of the present invention;

Fig. 2 is a schematic diagram of the diode structure in the N-type metal oxide semiconductor electrical parameter testing device in the embodiment of the present invention;

Fig. 3 is a schematic diagram of the composition of diodes in the P-type metal oxide semiconductor electrical parameter testing device in the embodiment of the present invention;

FIG. 4 is a flow chart of manufacturing an N-type metal oxide semiconductor electrical parameter testing device in an embodiment of the present invention;

FIG. 5 is a flow chart of manufacturing a P-type metal oxide semiconductor electrical parameter testing device in an embodiment of the present invention.

Detailed ways

In the embodiment of the present invention, in the metal oxide semiconductor electrical parameter test device with metal as the gate, two parallel reverse diodes are connected through the gate to release the charge introduced by the gate due to plasma damage, thereby improving the interface state and making the threshold test The values actually reflect the thresholds of the semiconductor devices in the circuit.

The schematic diagrams of the N-type metal oxide semiconductor electrical parameter test device and the P-type metal oxide semiconductor electrical parameter test device in the first embodiment of the present invention are shown in Fig. 1a and Fig. 1b.

In Fig. 1a, in the N-type metal oxide semiconductor electrical parameter test device with metal as the gate, the first P-type well region of the N-type substrate and the first PN structure formed by the first N+ region form the first diode 101 , the second PN structure formed by the second P-type well region of the N-type substrate and the second N+ region forms a second diode 102, and the first diode 101 is connected in antiparallel with the second diode 102 , and connected with the gate to form an N-type metal oxide semiconductor electrical parameter testing device.

In Fig. 1b, in the P-type metal-oxide-semiconductor electrical parameter test device with metal as the gate, the third PN structure formed by the N-type substrate and the first P+ region forms the third diode 103, and the N-type substrate The fourth PN structure formed with the second P+ region forms a fourth diode 104, the third diode 103 is connected in antiparallel with the fourth diode 104, and is connected to the gate to form a P-type metal oxide Semiconductor electrical parameter test device.

In the embodiment of the present invention, the metal-oxide-semiconductor electrical parameter test device using metal as the gate adopts an N-type substrate, so there is no need to separately fabricate the N-type well region, and the substrate is directly used instead, which is simple to implement.

Embodiment 2 of the present invention will describe in detail the composition of the reverse diode in the N-type metal oxide semiconductor electrical parameter testing device and the P-type metal oxide semiconductor electrical parameter testing device respectively.

As shown in Figure 2, it is a schematic diagram of the composition of the diode in the N-type metal oxide semiconductor electrical parameter testing device in the embodiment of the present invention:

(A), the anode is a P-type well region;

(B), the cathode is an N+ region formed by implanting N-type impurities into the P-type well region;

(C), the PN structure formed by the P-type well region and the N+ region forms a diode.

In FIG. 2, the cathode is connected to the metal grid, but it is not limited thereto.

According to the composition of the diode shown in Figure 2, two identical diodes are made and connected in reverse parallel to the gate to form an N-type metal oxide semiconductor electrical parameter test device, then the N-type metal oxide semiconductor electrical parameter in the first embodiment The composition of the test device specifically includes:

The anode of the first diode is the first P-type well region;

The cathode of the first diode is a first N+ region formed by implanting N-type impurities into the first P-type well region;

The anode of the second diode is the second P-type well region;

The cathode of the second diode is a second N+ region formed by implanting N-type impurities into the second P-type well region;

the cathode of the first diode is grounded to the anode of the second diode, the anode of the first diode is connected to the cathode of the second diode to the grid; or,

The anode of the first diode is grounded to the cathode of the second diode, and the cathode of the first diode is connected to the grid with the anode of the second diode.

Preferably, the first diode and the second diode are connected in antiparallel to the gate and can be connected in the following manner:

The cathode of the first diode and the anode of the second diode are grounded, the anode of the first diode and the cathode of the second diode open a contact hole, and are connected to the gate through a metal wiring ;or,

The anode of the first diode and the cathode of the second diode are grounded, the cathode of the first diode and the anode of the second diode open a contact hole, and are connected to the gate through a metal wiring .

As shown in Figure 3, it is a schematic diagram of the composition of the diode in the P-type metal oxide semiconductor electrical parameter testing device in the embodiment of the present invention:

(A), the cathode is an N-type substrate region;

(B), the anode is a P+ region formed by implanting P-type impurities into the N-type substrate region;

(C), the PN structure formed by the N-type substrate region and the P+ region forms a diode.

In FIG. 3, the anode is connected to the metal grid, but it is not limited thereto.

Similarly, two identical diodes as shown in Figure 3 are connected in reverse parallel and connected to the gate to form a P-type metal oxide semiconductor electrical parameter test device, then the specific composition of the P-type metal oxide semiconductor electrical parameter test device is:

The cathode of the third diode is the N-type substrate region;

The anode of the third diode is the first P+ region formed by implanting P-type impurities into the N-type substrate region;

The cathode of the fourth diode is the N-type substrate region;

The anode of the fourth diode is the second P+ region formed by implanting P-type impurities into the N-type substrate region;

The cathode of the third diode is grounded to the anode of the fourth diode, and the anode of the third diode is connected to the grid with the cathode of the fourth diode; or,

The anode of the third diode is grounded to the cathode of the fourth diode, and the cathode of the third diode is connected to the grid with the anode of the fourth diode.

Preferably, the third diode and the fourth diode are connected in antiparallel to the gate and can be connected in the following manner:

The cathode of the third diode and the anode of the fourth diode are grounded, the anode of the third diode and the cathode of the fourth diode open a contact hole, and are connected to the gate through a metal wiring ;or,

The anode of the third diode is grounded to the cathode of the fourth diode, a contact hole is opened between the cathode of the third diode and the anode of the fourth diode, and the gate is connected to the gate through a metal wiring .

Embodiment 3 of the present invention also provides a method for manufacturing the N-type metal oxide semiconductor electrical parameter test device in Embodiment 1, as shown in FIG. 4 , the method includes:

Step S401: forming a first P-type well region on an N-type substrate.

Specifically, a first P-type well region is formed on the N-type substrate as the anode of the first diode.

Step S402: Implanting N-type impurities into the first P-type well region to form a first N+ region.

Specifically, the first N+ region formed by implanting N-type impurities into the first P-type well region serves as the cathode of the first diode.

Step S403: a first PN structure formed by the first P-type well region and the first N+ region forms a first diode.

Step S404: forming a second P-type well region on the N-type substrate.

Specifically, a second P-type well region is formed on the N-type substrate as the anode of the second diode.

Step S405: Implanting N-type impurities into the second P-type well region to form a second N+ region.

Specifically, the second N+ region formed by implanting N-type impurities into the second P-type well region serves as the cathode of the second diode.

Step S406: A second PN structure formed by the second P-type well region and the second N+ region forms a second diode.

Step S407: The first diode is connected in antiparallel with the second diode and connected to the gate to form an NMOS electrical parameter testing device.

Specifically, the process of connecting the first diode and the second diode in antiparallel and connecting to the gate is as follows: the cathode of the first diode and the anode of the second diode are grounded, and the first diode is grounded. The anode of one diode is connected to the cathode of the second diode and the gate to form the N-type metal oxide semiconductor electrical parameter testing device; or,

The anode of the first diode is grounded to the cathode of the second diode, and the cathode of the first diode is connected to the anode of the second diode to the gate to form the N-type metal oxide Semiconductor electrical parameter test device.

Preferably, in this embodiment of the present invention, a contact hole may be opened on the anode or cathode of the first diode and the second diode, and the gate may be connected to the gate through a metal wiring.

Preferably, the formation process of the diode in the embodiment of the present invention can be realized in the following manner, which is of course not limited thereto.

(A), the P-type well region is used as the anode of the diode.

Specifically, the formation process of the P-type well region in the embodiment of the present invention is as follows: after using the P-type well photolithography plate to manufacture the P-type well through the steps of glue coating, exposure and development, etc., using a medium beam implanter to perform boron implantation, Form the P-type well implantation region; then, wet etch the P-type well with a buffered silicon oxide etching solution, and remove the photoresist on the surface with sulfuric acid; finally, push the well at a high temperature of 1150 degrees to obtain The required P-type well area.

(B) When testing the source and drain of the N-type metal oxide semiconductor electrical parameters, an N+ region is formed, and the N+ region is used as the cathode of the diode.

Specifically, when the electrical parameters of the N-type metal oxide semiconductor are tested for the source and drain of the device, a large beam implanter is used to implant N-type impurities into the P-type well region to form an N+ region, wherein the N+ region is heavily doped with group five elements. mixed area.

(C), the PN structure formed by the P-type well region and the N+ region forms a diode, and is connected to the gate.

Embodiment 4 of the present invention also provides a method for manufacturing a P-type metal oxide semiconductor electrical parameter testing device whose gate is a metal gate. The specific manufacturing process is shown in FIG. 5 :

Step S501: Implanting P-type impurities into the N-type substrate region to form a first P+ region.

Step S502: The N-type substrate region and the first P+ region form a third PN structure to form a third diode.

Specifically, the N-type substrate region is used as the cathode of the third diode; the first P+ region formed by implanting P-type impurities into the N-type substrate region is used as the anode of the third diode.

Step S503: Implanting P-type impurities into the N-type substrate region to form a second P+ region.

Step S504: the N-type substrate region and the second P+ region form a fourth PN structure to form a fourth diode.

Specifically, the N-type substrate region is used as the cathode of the fourth diode; the second P+ region formed by implanting P-type impurities into the N-type substrate region is used as the anode of the fourth diode.

Step S505: the third diode is connected in antiparallel to the fourth diode and connected to the gate to form a P-type metal oxide semiconductor electrical parameter testing device.

Specifically, the process of connecting the third diode in antiparallel with the fourth diode and connecting to the gate is as follows: the cathode of the third diode is grounded to the anode of the fourth diode, and the anode of the fourth diode is grounded. The anodes of the three diodes are connected to the cathode of the fourth diode and the gate to form the P-type metal oxide semiconductor electrical parameter testing device; or, the anode of the third diode is connected to the fourth diode The cathode of the first diode is grounded, the cathode of the third diode is connected to the anode of the fourth diode and the gate, forming the P-type metal oxide semiconductor electrical parameter testing device.

Preferably, in the embodiment of the present invention, a contact hole may be opened on the anode or cathode of the third diode and the fourth diode, and connected to the gate through metal wiring.

Preferably, the specific formation process of the diode in the PMOS electrical parameter testing device in the embodiment of the present invention can be realized in the following manner, which is not limited thereto.

(A), the N-type substrate region is used as the cathode of the diode.

(B) When testing the source and drain of the P-type metal oxide semiconductor electrical parameters, a P+ region is formed, and the P+ region is used as the anode of the diode.

Specifically, when the source and drain of the P-type metal oxide semiconductor electrical parameter test device is used, a large beam implanter is used to implant P-type impurities into the N-type substrate region to form a P+ region, wherein the P+ region is a heavily doped region of Group III elements .

(C), the PN structure formed by the N-type substrate and the P+ region forms a diode, and is connected to the gate.

In the embodiment of the present invention, in the metal oxide semiconductor electrical parameter testing device using metal as the gate, the gate and substrate of the N-type metal oxide semiconductor electrical parameter testing device or the P-type metal oxide semiconductor electrical parameter testing device Forming two parallel reverse diodes can well release the positive or negative charges introduced by plasma damage, thereby improving the interface state, making the threshold voltage change less, and making the threshold test value actually reflect the semiconductor device in the circuit threshold.

Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalent technologies, the present invention also intends to include these modifications and variations.

Claims (11)

1. A metal oxide semiconductor electrical parameter testing device, the gate of the semiconductor device is a metal gate, characterized in that the first P-type well region of the N-type substrate and the first N+ region form the first PN structure form the first diode, and the second PN structure formed by the second P-type well region of the N-type substrate and the second N+ region forms the second diode, and the first diode is opposite to the second diode connected in parallel and connected to the gate to form an N-type metal oxide semiconductor electrical parameter testing device; or, The third PN structure formed by the N-type substrate and the first P+ region forms a third diode, the fourth PN structure formed by the N-type substrate and the second P+ region forms a fourth diode, and the third diode It is connected in antiparallel with the fourth diode and connected with the gate to form a P-type metal oxide semiconductor electrical parameter testing device. 2. semiconductor electrical parameter testing device as claimed in claim 1, is characterized in that, the formation of described N-type metal oxide semiconductor electrical parameter testing device specifically comprises: The anode of the first diode is a first P-type well region; The cathode of the first diode is a first N+ region formed by implanting N-type impurities into the first P-type well region; The anode of the second diode is a second P-type well region; The cathode of the second diode is a second N+ region formed by implanting N-type impurities into the second P-type well region; the cathode of the first diode is grounded to the anode of the second diode, the anode of the first diode is connected to the cathode of the second diode to the grid; or, The anode of the first diode is grounded to the cathode of the second diode, and the cathode of the first diode is connected to the grid with the anode of the second diode. 3. The semiconductor electrical parameter testing device according to claim 2, wherein the first diode is connected in antiparallel with the second diode and is connected to the gate specifically comprising: The cathode of the first diode and the anode of the second diode are grounded, the anode of the first diode and the cathode of the second diode open a contact hole, and are connected to the gate through a metal wiring ;or, The anode of the first diode and the cathode of the second diode are grounded, the cathode of the first diode and the anode of the second diode open a contact hole, and are connected to the gate through a metal wiring . 4. semiconductor electrical parameter testing device as claimed in claim 1, is characterized in that, the composition of described P-type metal oxide semiconductor electrical parameter testing device specifically comprises: The cathode of the third diode is an N-type substrate region; The anode of the third diode is the first P+ region formed by implanting P-type impurities into the N-type substrate region; The cathode of the fourth diode is the N-type substrate region; The anode of the fourth diode is a second P+ region formed by implanting P-type impurities into the N-type substrate region; The cathode of the third diode is grounded to the anode of the fourth diode, and the anode of the third diode is connected to the grid with the cathode of the fourth diode; or, The anode of the third diode is grounded to the cathode of the fourth diode, and the cathode of the third diode is connected to the grid with the anode of the fourth diode. 5. The semiconductor electrical parameter testing device according to claim 4, wherein the third diode is connected in antiparallel with the fourth diode and is connected to the gate specifically comprising: The cathode of the third diode and the anode of the fourth diode are grounded, the anode of the third diode and the cathode of the fourth diode open a contact hole, and are connected to the gate through a metal wiring ;or, The anode of the third diode is grounded to the cathode of the fourth diode, a contact hole is opened between the cathode of the third diode and the anode of the fourth diode, and the gate is connected to the gate through a metal wiring . 6. A method for manufacturing an N-type metal oxide semiconductor electrical parameter testing device, the gate of the N-type metal oxide semiconductor electrical parameter testing device is a metal grid, it is characterized in that the method comprises: forming a first P-type well region on an N-type substrate; Implanting N-type impurities into the first P-type well region to form a first N+ region; A first PN structure formed by the first P-type well region and the first N+ region forms a first diode; forming a second P-type well region on the N-type substrate; Implanting N-type impurities into the second P-type well region to form a second N+ region; A second PN structure formed by the second P-type well region and the second N+ region forms a second diode; The first diode is connected in antiparallel with the second diode and connected to the gate to form an N-type metal oxide semiconductor electrical parameter testing device. 7. The manufacturing method of N-type metal oxide semiconductor electrical parameter testing device as claimed in claim 6, is characterized in that, the method specifically comprises: forming a first P-type well region on the N-type substrate as the anode of the first diode; The first N+ region formed by implanting N-type impurities into the first P-type well region is used as the cathode of the first diode; forming a second P-type well region on the N-type substrate as the anode of the second diode; A second N+ region formed by implanting N-type impurities into the second P-type well region is used as the cathode of the second diode; The cathode of the first diode is grounded to the anode of the second diode, and the anode of the first diode is connected to the cathode of the second diode to the gate to form the N-type metal oxide Semiconductor electrical parameter testing devices; or, The anode of the first diode is grounded to the cathode of the second diode, and the cathode of the first diode is connected to the anode of the second diode to the gate to form the N-type metal oxide Semiconductor electrical parameter test device. 8. The manufacturing method of an N-type metal oxide semiconductor electrical parameter testing device as claimed in claim 7, wherein the first diode is connected in reverse parallel with the second diode and then connected to the gate The process is specifically: The cathode of the first diode and the anode of the second diode are grounded, the anode of the first diode and the cathode of the second diode open a contact hole, and are connected to the gate through a metal wiring ;or, The anode of the first diode and the cathode of the second diode are grounded, the cathode of the first diode and the anode of the second diode open a contact hole, and are connected to the gate through a metal wiring . 9. A method for manufacturing a P-type metal oxide semiconductor electrical parameter testing device, wherein the grid of the P-type metal oxide semiconductor electrical parameter testing device is a metal grid, characterized in that the method comprises: Implanting P-type impurities into the N-type substrate region to form a first P+ region; The N-type substrate region and the first P+ region form a third PN structure to form a third diode; Implanting P-type impurities into the N-type substrate region to form a second P+ region; The N-type substrate region and the second P+ region form a fourth PN structure to form a fourth diode; The third diode is connected in antiparallel to the fourth diode and connected to the gate to form a P-type metal oxide semiconductor electrical parameter testing device. 10. The manufacturing method of P-type metal oxide semiconductor electrical parameter testing device as claimed in claim 9, is characterized in that, the method specifically comprises: The N-type substrate region serves as the cathode of the third diode; The first P+ region formed by implanting P-type impurities into the N-type substrate region is used as the anode of the third diode; The N-type substrate region serves as the cathode of the fourth diode; The second P+ region formed by implanting P-type impurities into the N-type substrate region is used as the anode of the fourth diode; The cathode of the third diode is grounded to the anode of the fourth diode, and the anode of the third diode is connected to the cathode of the fourth diode to the gate to form the P-type metal oxide Material semiconductor electrical parameter test device; or, The anode of the third diode is grounded to the cathode of the fourth diode, and the cathode of the third diode is connected to the anode of the fourth diode to the grid to form the P-type metal oxide Material semiconductor electrical parameter test device. 11. The manufacturing method of P-type metal oxide semiconductor electrical parameter test device as claimed in claim 10, it is characterized in that, after described third diode and described fourth diode anti-parallel are connected with described gate The connected process is specifically: The cathode of the third diode and the anode of the fourth diode are grounded, the anode of the third diode and the cathode of the fourth diode open a contact hole, and are connected to the gate through a metal wiring ;or, The anode of the third diode is grounded to the cathode of the fourth diode, a contact hole is opened between the cathode of the third diode and the anode of the fourth diode, and the gate is connected to the gate through a metal wiring .

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