CN103389917A - SRAM (static random access memory) type FPGA SEU (field programmable gate array single event upset) operation fixing method - Google Patents

Abstract

The invention discloses an SRAM (static random access memory) type FPGA SEU (field programmable gate array single event upset) operation fixing method, belonging to the technical field of configuration of SRAM type FPGAs. The method comprises the following steps: 1) after an SRAM type FPGA is electrified, a configuration management FPGA is used for carrying out whole configuration on the SRAM type FPGA; 2) the configuration management FPGA reads a configuration bit stream file, detects the bit stream file and carrying out the follow steps: when a frame write-in command FDRI in the bit stream file is detected, an incidental frame word number in the FDRI is replaced with a logic and interconnection frame word number; when content configuration dada Block RAM is detected, the Block RAM is replaced with a no-operation command; when a register resetting command GRESTORE is detected, the GRESTORE is replaced with a no-operation command; when I/O start command STARTUP is detected, the STARTUP is replaced with a no-operation command; 3) the bit stream file which is subjected to the process of the step 2) is written into the SRAM type FPGA; and 4) the step 2) and the step 3) are repeated until the SRAM type FPGA stops working. The method is suitable for SRAM type FPGA SEU operation fixation.

Description

The method of a kind of SRAM type FPGA SEU reparation in service

Technical field

The present invention relates to the configuring technical field of SRAM type FPGA, particularly the method for a kind of SRAM type FPGASEU reparation in service.

Background technology

The Virtex-5 Series FPGA is the novel FPGA based on SRAM technique that Xilinx company releases, and its integrated level is high, and logic function is strong, is widely used in the Modern Digital System design.The logic function of Virtex-5FPGA configures the data realization by its SRAM type configuring area,

The SRAM attribute has determined configuring area data meeting loss after power down, therefore configuration data must be kept in nonvolatile external memory, after FPGA powers on, it is reconfigured.

In aerospace applications, the Energetic particle bombardment causes SRAM type FPGA configuring area single-particle inversion SEU may cause the fpga logic mistake, must repair the normal operation that can guarantee FPGA to the configuring area single-particle inversion of FPGA.Single-particle inversion in the configuring area of traditional reply FPGA has following several strategy usually:

1), regular global reconfiguration

SEU is a kind of soft error, and it can not cause the permanent damages of hardware, and after FPGA reloaded configuration data, the impact of SEU can be removed.The application not bery high to some reliability requirements, system has certain tolerance to a small amount of SEU, and regular FPGA global reconfiguration can be eliminated the accumulation of SEU again, can guarantee that substantially system is in normal operating conditions.Thus, the application general to reliability requirement, it is a kind of acceptable scheme that the global reconfiguration by FPGA solves the SEU effect.

2), urgent global reconfiguration

In some occasion higher to reliability requirement, regular global reconfiguration becomes and can not accept owing to can't eliminating fast the SEU impact.Urgent global reconfiguration system must possess corresponding SEU error-detecting and errorlevel judgment mechanism, determines to carry out immediately global reconfiguration or postpone global reconfiguration until current key operation is completed after the SEU mistake occurs.

In requiring the application that FPGA is highly reliable, long-time continuous is moved, regularly reshuffle strategy, promptly reshuffle strategy and all because of the normal operation that meeting interrupts FPGA, become inapplicable, how in the situation that do not interrupt the operation of FPGA, the reparation of carrying out the SEU mistake will be the development trend of the configuring technical of SRAM type FPGA.

The reparation in service of SEU, traditional method is to adopt " retaking of a year or grade-comparison-write-back " mode, wherein need use a shielding file .msk and a retaking of a year or grade file .rbb, actual process is: use retaking of a year or grade file .rbb and original configuration file .bit to compare, if both difference utilizes shielding file .msk that retaking of a year or grade file .rbb is write in FPGA.This mode is except the logic of relative complex, and maximum shortcoming is that .msk all has the size identical with original configuration file .bit with the .rbb file, causes taking of storage space to reach original three times; And, because the retaking of a year or grade holding time of configuring area is longer, do not reach and carry out the needed real-time of middle reparation.The mode of therefore above " retaking of a year or grade-comparison-write-back " is also impracticable.

Summary of the invention

In view of this, the invention provides the method for a kind of SRAM type FPGA SEU reparation in service, purpose is to realize the global configuration that powers on of SRAM type FPGA, and the SEU of configuring area is carried out reparation in service, and takies less storage space, possesses real-time.

For achieving the above object, the method comprises the steps:

The first step, after SRAM type FPGA powers on, use configuration management FPGA to carry out global configuration one time to SRAM type FPGA;

Second step, configuration management FPGA read the configuration bit stream file, detect this bit stream file and are handled as follows:

When the frame in the bit stream file being detected writes order FDRI, frame number of words subsidiary in FDRI is replaced with logic and interconnect frame number of words;

When content configuration data Block RAM being detected, use the blank operation order to replace Block RAM;

When register reset command GRESTORE being detected, use the blank operation order to replace GRESTORE;

When I/O startup command STARTUP being detected, use the blank operation order to replace STARTUP;

The 3rd the step, the bit stream file after second step is processed is write SRAM type FPGA;

The 4th step, repetition second step and the 3rd go on foot until SRAM type FPGA quits work.

Beneficial effect:

1, the present invention has adopted the method that the SEU mistake is carried out " washing " to realize the reparation in service of SEU.The data that configuring area is write with a brush dipped in Chinese ink are still from original configuration bit stream file, its central principle is to configuration frame data entrance register FDRI data writing the time, only write the logic data relevant with interconnection configuration, Block RAM content-data is masked, so namely realize the washing of SEU, also can not destroy the data in user RAM.The order that can interrupt simultaneously the FPGA operation also will mask, and as the GRESTORE order, this and order interrupts the normal operation of FPGA.Therefore the method can be in operation the SEU mistake of FPGA is repaired.

2, because the method does not detect the SEU mistake, but to configuring area, repeatedly write with a brush dipped in Chinese ink into correct configuration data, SEU mistake " washing " is fallen.Compare " retaking of a year or grade-comparison-write-back " mode of classic method, do not use shielding file .msk and retaking of a year or grade file .rbb, use original configuration bit stream file, therefore take less storage space; Due to the retaking of a year or grade time of having saved configuring area, SEU also wants shorter from occurring to relative classic method of the time that is repaired, and possesses real-time simultaneously;

Description of drawings

Fig. 1 circuit connection diagram;

The transforming relationship of Fig. 2 bit stream file and SEU washing bit stream;

Fig. 3 SEU washing flow figure.

Embodiment

, below in conjunction with the accompanying drawing embodiment that develops simultaneously, describe the present invention.

The method of the SEU reparation in service for SRAM type FPGA used in the present invention, wherein the method connects and can complete based on traditional FPGA circuit, and its circuit connects as shown in Figure 1.

The SRAM type FPGA that uses in the present embodiment is the Virtex-5 Series FPGA;

The configuration bit stream file of this Virtex-5FPGA is deposited in nonvolatile external memory, and normally used nonvolatile external memory is PROM in practical operation;

The configuration of this Virtex-5FPGA is controlled by configuration management FPGA, and the configuration management FPGA that uses in the present embodiment is anti-fuse-type, not affected by SEU;

Wherein be connected by Slvae SelectMAP interface between Virtex-5FPGA and configuration management FPGA.

The method specific works step of the SEU reparation in service for SRAM type FPGA provided by the present invention as shown in Figure 3, comprises following concrete steps:

The first step, power on after, use configuration management FPGA to start SRAM type FPGA is carried out global configuration one time; The global configuration method, for to read the configuration bit stream file from nonvolatile external memory PROM, flows to SRAM type FPGA to carry out global configuration with its former state; After completing global configuration, the DONE signal of SRAM type FPGA is drawn high, and sign SRAM type FPGA global configuration is completed;

Second step, configuration management FPGA enters washers' SEU operation mode after the success of the global configuration of the first step.

In the present embodiment, configuration management FPGA need to carry out global configuration to RAM type FPGA on the one hand, namely realizes the first step; Need on the other hand configuration bit stream file dissection process and write RAM type FPGA to carry out the SEU washing, namely realizing second step.Therefore configuration management FPGA inside has the circuit setting of writing direct of a road bit stream file in the present embodiment, has simultaneously a road bit stream document analysis circuit, and concrete configuration management FPGA structure as shown in Figure 1.

Configuration management FPGA reads the configuration bit stream file, via bit stream document analysis circuit, the bit stream file is done real-time processing, the settling signal DONE that SRAM type FPGA detected as configuration management FPGA is drawn high, be the global configuration success, the bit stream file after processing is in real time flowed to SRAM type FPGA.APA600 restarts to read bit stream from the XCF16P first address, and the bit stream parser circuitry is resolved the bit road, and part order in bit stream and data are done and replaced and shielding processing, detects in bit stream after the DESYNC order, and a SEU washs and completes.

In this step, the structure of analyzing the bit stream file forms, as shown in Figure 2, before and after the bit stream file comprises command group, logic and interconnected configuration data and, wherein before and after frame in command group write order FDRI and include frame number of words, register reset command GRESTORE and startup command START and can have influence on the operation of SRAM type FPGA.

Wherein the real-time processing in this step comprises:

When if frame in the bit stream file being detected and writing order FDRI, in FDRI with the frame number of words comprised the frame number of words summation of logic and interconnect frame number of words and content configuration data, owing to washing in the present invention, that repeats to write with a brush dipped in Chinese ink should only be logic and interconnected configuration data, do not need to comprise the content configuration data, so in ordering, subsidiary frame number of words replaces with logic and interconnect frame number of words herein;

If content configuration data Block RAM detected, use the blank operation order to replace Block RAM,, because in SRAM type FPGA, Block RAM has put down in writing user data, therefore do not need washing.Make Block RAM content initial value can not be written into SRAM type FPGA so use the blank operation order to replace Block RAM, the user data in SRAM type FPGA is preserved, and only configuring area SEU is washed;

, if register reset command GRESTORE order detected, use the blank operation order to replace the GRESTORE order, the SRAM type FPGA interruption of having avoided the register in SRAM type FPGA to reset and cause;

, if startup command START order detected, use the blank operation order to replace the START order.Because the START order can start the flow process that a series of FPGA start, and the some of them flow process can make I/O be in high-impedance state within a period of time, thereby destroy the normal operation of I/O, therefore this method is not write with a brush dipped in Chinese ink the START order as SRAM type FPGA, thereby avoid starting the SRAM type FPGA that brings, interrupts;

Bit stream file after the acquisition of this step is processed is designated as SEU washing bit stream.

The 3rd step, SEU is washed bit stream write SRAM type FPGA;

The 4th step, repetition second step and the 3rd go on foot until FPGA quits work.After namely a SEU washing was completed, SEU washing next time was to start immediately, till washing work should be continued until that FPGA quits work.

Can be found out by above-mentioned flow process,, except part order in bit stream and data have been done replacement and shielding processing, be consistent to the process of the SEU process of washing and the global configuration that powers on.

The present invention also can use timer, by starting washers' operation mode of SEU after timer appointment regularly, after washing is completed each time, by start to wash after timer appointment regularly next time.Equally also can use peripheral control unit, by peripheral control unit, send SEU washing instruction to configuration management FPGA, configuration management FPGA receives after SEU washing instruction the washers' operation mode that starts SEU.In the implementation process of reality, can select flexibly according to the demand of application scenario.

In sum, these are only preferred embodiment of the present invention, not be used for limiting protection scope of the present invention.Within the spirit and principles in the present invention all, any modification of doing, be equal to replacement, improvement etc., within all should being included in protection scope of the present invention.

Claims (1)

1. the method for SRAM type FPGA SEU reparation in service, is characterized in that, the method comprises the steps:

The first step, after SRAM type FPGA powers on, use configuration management FPGA to carry out global configuration one time to SRAM type FPGA;

Second step, configuration management FPGA read the configuration bit stream file, detect this bit stream file and are handled as follows:

When the frame in the bit stream file being detected writes order FDRI order, frame number of words subsidiary in FDRI is replaced with logic and interconnect frame number of words;

When content configuration data Block RAM being detected, use the blank operation order to replace Block RAM;

When register reset command GRESTORE order being detected, use the blank operation order to replace GRESTORE;

When startup command START order being detected, use the blank operation order to replace START;

The 3rd the step, the bit stream file after second step is processed is write SRAM type FPGA;

The 4th step, repetition second step and the 3rd go on foot until SRAM type FPGA quits work.

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