CN103383641A - Synchronous device for multi-assembly lines - Google Patents

Abstract

The invention discloses a multi-pipeline synchronization device. In the device, the control state register transmission unit completes the control state register transmission between pipelines, including the control register configuration operation of pipeline A to pipeline B, and the control register configuration operation of pipeline A to pipeline B. Status register read operation. The pipeline register transfer unit completes the register transfer between the general registers in pipeline A and the pipeline configuration registers in pipeline B, so that pipeline B can obtain the register information required for its operation. The synchronization logic unit is responsible for receiving scheduling instructions and blocking information, and according to the control status register, generates a pause signal for pipeline A, generates scheduling enable and transmits scheduling information for pipeline B.

Description

A Multi-Pipeline Synchronization Device

technical field

The invention relates to the technical field of pipelines, in particular to a multi-pipeline synchronization device. the

Background technique

Pipeline technology refers to a quasi-parallel processing implementation technology in which multiple instructions overlap and operate during program execution. With the development of processor architecture, many new pipeline technologies have emerged, such as dynamic pipeline technology and super pipeline technology, which have greatly improved the performance of processors. the

With the progress of the times and the development of society, in the information age, people's demand for information processing is increasing, and the ability of the information processing system is required to be higher and higher. In particular, with the rapid development of the Internet, cloud computing, and the Internet of Things, a large number of mobile devices and wireless sensors are generating information all the time, and hundreds of millions of Internet services have generated a huge amount of information interaction. Large-scale computing puts forward requirements for the development of processors. the

In order to solve the above problems, processor designers continue to innovate to improve processor performance, and the proposal of multi-processor core technology is particularly important. For example, Nvdia's GPU architecture GT480 processor has 15 stream processors (Streaming Multiprocessors), and each stream processor has 32 cuda processors. The cuda core has independent registers and program counters, but there is no fetching and scheduling unit to It constitutes a complete front end, but it is provided by a stream processor; another example is a general-purpose multi-core CPU processor, which only completes synchronous communication between cores, but does not involve multi-pipeline synchronization within the core. the

Contents of the invention

In view of this, the present invention provides a multi-pipeline synchronization device, which can efficiently implement multi-pipeline configuration synchronization, so as to meet the requirements of adapting to large-scale computing processors. The present invention proposes a multi-pipeline synchronization device, including: an instruction storage unit, a configuration pipeline A, an operation pipeline B, and a pipeline synchronization device, wherein the pipeline synchronization device includes a control status register transmission unit, a pipeline register transmission unit, and a synchronization logic unit. A further includes ordinary registers, and pipeline B further includes control status registers and pipeline configuration registers, wherein the control status register transfer unit realizes the transfer of control status registers between pipelines, including the control register configuration operation of pipeline A to pipeline B, and pipeline A For the read operation of the status register of the pipeline B, the pipeline register transmission unit realizes the transmission of the general register and the pipeline configuration register, the synchronization logic unit is used to realize the synchronization function between the pipelines, and the control register is used to control which operation state the pipeline B is in, the state The register reflects the busy state of pipeline B, and the instruction storage unit provides instructions for the pipeline register transfer unit. the

Among them, pipeline A is a configuration pipeline, which is used to schedule pipeline B; pipeline B is a computing pipeline, which is used to meet large-scale computing requirements. the

Among them, the pipeline B is divided into two clusters, X and Y, and has three working modes, namely, no clustering work, only X work in the case of clustering, and only Y work in the case of clustering. the

Among them, the control register is represented by CCtrl, and the status register is represented by CStat, both of which are 3-bit registers. The control register CCtrl is xx0, which means that no clustering works, 011 means that only X works in the case of clustering, and 101 means that only Y works in the case of clustering , the status register CStat[0] indicates the busy/idle state of pipeline B without clustering, 1 means busy, CStat[1] indicates the busy/idle state of cluster X in pipeline B under clustering, 1 means busy, CStat [2] Indicates the busy/idle state of cluster Y in pipeline B in the case of clustering. the

The multi-pipeline synchronization device of the present invention can configure the control register and read the status register; according to the scheduling instruction, by querying the status register and the control register, the synchronization of multiple pipelines can be flexibly realized; at the same time, according to the state of the control register, the register of any state pipeline can be completed configuration. the

Description of drawings

Fig. 1 is the module structural diagram of multi-pipeline synchronization device of the present invention;

Fig. 2 is an explanatory diagram of the control state register of the present invention;

Figure 3 configuration register coding example;

Fig. 4 is the structural diagram of pipeline register transmission unit of the present invention;

Fig. 5 is the block diagram of synchronous logic unit of the present invention;

Fig. 6 is the synchronous logic unit Called signal generation code of the present invention;

Fig. 7 is the synchronous logical unit dispatching enabling generation circuit diagram of the present invention;

FIG. 8 is a circuit diagram for generating a pipeline stall of a synchronous logic unit according to the present invention. the

Detailed ways

In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be described in further detail below in conjunction with specific embodiments and with reference to the accompanying drawings. the

There are two pipelines in each core of the multi-core processor related to the present invention, one pipeline is used for large-scale computing, and the other is used for small-scale computing and scheduling of large-scale computing pipelines, which can efficiently target applications Implement reasonable operational planning. In order to realize the synchronization between the pipelines, it is necessary to design a high-performance pipeline synchronization device, and the present invention is implemented based on the above considerations. the

FIG. 1 is a structural diagram of a multi-pipeline synchronization device of the present invention. Referring to FIG. 1 , taking dual-pipeline synchronization as an example, the dual-pipeline synchronization device mainly includes the following components: instruction storage unit 106 , configuration pipeline A104 , operation pipeline B105 , and pipeline synchronization device 100 . The pipeline synchronization device includes a control status register transfer unit 101, a pipeline register transfer unit 102 and a synchronization logic unit 103, the pipeline A104 further includes a general register 107, and the pipeline B105 further includes a control status register 108 (which includes a control register and a status register), Pipeline Configuration Register 109. The control status register transmission unit 101 implements the control status register transmission between pipelines, including the control register configuration operation from pipeline A to pipeline B, and the status register read operation from pipeline A to pipeline B. The pipeline register transmission unit 102 realizes the transmission of the general register 107 and the pipeline configuration register 109, and the synchronization logic unit 103 is the core of the whole device, and realizes the synchronization function between the pipelines. The control register is used to control which operation state the pipeline B is in. The status register reflects the busy/idle state of the pipeline B. The general register is used to provide input to the control status register and the pipeline configuration register. The pipeline configuration register provides the configuration information required for the operation of the pipeline B. the

The control status register transmission unit 101 completes the control status register transmission between pipelines, including the control register configuration operation from pipeline A to pipeline B, and the status register read operation from pipeline A to pipeline B. Pipeline A is a configuration pipeline used to schedule pipeline B; pipeline B is a computing pipeline used to meet large-scale computing needs. Pipeline B adopts clustering technology and can be divided into X and Y clusters. In the case of clustering, only X works, and in the case of clustering, only Y works. the

The control register is configured by pipeline A to control the operation status of pipeline B. The status register reflects the busy and idle status of pipeline B, which is fed back by pipeline B. The control register is represented by CCtrl, and the status register is represented by CStat, both of which are 3-bit registers, as shown in Figure 2. The control register CCtrl is xx0, which means no clustering, 011 means only X works under clustering, and 101 means only Y works under clustering. The status register CStat[0] indicates the busy/idle state of pipeline B without clustering, 1 means busy; CStat[1] indicates the busy/idle state of cluster X in pipeline B under clustering, 1 means busy; CStat[ 2] Indicates the busy/idle status of cluster Y in pipeline B in the case of clustering. In this way, arbitrary characteristics of the pipeline configuration and state can be indicated. the

The operation of the operation pipeline B requires a large amount of configuration information, which requires the pipeline A to be configured through the pipeline synchronization device 100, and the pipeline register transmission unit 102 is responsible for the register transmission of the general register 107 in the pipeline A and the pipeline configuration register 109 in the pipeline B. the

Pipelines that run large-scale computations necessarily require a lot of configuration register information. This article provides an instruction configuration form, KAs=Rm, KBs=Rm, etc., where s is a subscript indicating which KA it is (there are multiple KAs). Rm indicates the value of an ordinary register. Here KA and KB are pipeline configuration registers, and R is an ordinary register. Since pipeline B contains many pipeline configuration registers 109, and they have common characteristics, they can be divided into multiple groups, and each group contains many registers. Accordingly, the present invention provides a flexible encoding method, mi-1mi-2mi-3...m2m1m0nj-1nj-2nj-3...n2n1n0, wherein mi-1mi-2mi-3...m2m1m0 provides i pipelines Configure register groups, nj-1nj-2nj-3...n2n1n0 provide j registers in each register group. In this way, according to the number of register groups and the number of registers of each register group, the coding of configuration registers can be completed flexibly by selecting appropriate i and j. Figure 3 depicts an encoding example. KA to KD can represent at most 16 corresponding registers, and KE, KF, and KG can adjust the available codes according to the number of registers, and only use 3, 2, and 1-bit codes to represent at most 8, 4, and 2 corresponding registers. the

FIG. 4 is an implementation structural diagram of the pipeline register transfer unit 102 . The pipeline register transfer unit completes the register transfer between the general registers in pipeline A and the pipeline configuration registers in pipeline B, so that pipeline B can obtain the register information required for its operation. The instruction storage unit 106 provides instructions for the pipeline register transmission unit, and the instruction generates the enable signal En, the ID signal GrpID/RegID and the data signal Data through the decoding logic a (404), GrpID is the code mi-1mi-2mi-3 above. The information given by ..m2m1m0 can identify which group of registers a certain pipeline register transfer unit should transfer to, and then transfer En, RegID and Data to the selected register group, such as register group 406, after decoding logic The unit b405 analyzes the RegID, and then can select a designated register such as KA1 for reading and writing. For example, suppose there are 7 register banks, each with a maximum of 16 registers. If you want to write a register coded as 0000001, first take out the instruction from the instruction storage unit, generate En and ID through the decoding logic a, get Data from the general register 107, and identify the GrpID as 000, that is, write the register group KA, so that En, The RegID and Data are passed to the decoding logic B, and the RegID is identified as 0001, that is, the register KA0 is written. In this way, a write configuration register operation is completed. the

The synchronization logic unit 103 is the core part of the pipeline synchronization device. FIG. 5 is a block diagram of the synchronization logic unit 103 . It is responsible for receiving scheduling instructions and blocking information from the instruction storage unit 106, and according to the control status register 108, generates a pause signal for the configuration pipeline A104, generates a scheduling enable and transmits scheduling information for the operation pipeline B105. the

The main function of the synchronization logic unit 103 is to generate scheduling enable and pause signals to ensure correct operation between pipelines. According to the control register CCtrl described above, there may be three configuration modes, no clustering, only X works in the case of clustering, and only Y works in the case of clustering. Scheduling enable and pause signals need to be coordinated and generated according to the configuration and operation of the pipeline. The signal list of the synchronization logic unit 103 is as follows. the

Signal in/out describe Instr in dispatch instruction fetched from instruction store iCCtrl0 in Configure pipeline B to work without clustering iCCtrl1 in Configure pipeline B to cluster only cluster X to work iCCtrl2 in Configure pipeline B to cluster only cluster Y to work iCStat0 in Busy/idle state of pipeline B without clustering iCStat1 in Pipeline B only works in the busy/idle state of cluster X iCStat2 in Pipeline B only works in the busy/idle state of cluster Y CallEn out Enable the scheduling of pipeline B Stall out Stop pipeline A

At the same time, the synchronization logic unit 103 will generate a series of intermediate signals, CallEn0, CallEn1, and CallEn2 respectively indicate no clustering, X working under clustering, and scheduling enablement under clustering Y working. Called0, Called1, and Called2 indicate the status of pipeline B not finishing processing after CallEn is issued under the three working conditions. If pipeline B is finished processing, Called is cleared. The generation of Called is shown in Figure 6. Stall0, Stall1, and Stall2 represent pipeline stalls under three working conditions. CallBlkEn indicates that blocking is enabled when Call is enabled, and SYNCodeEn indicates that the Call command is valid, and CallBlkEn and SYNCodeEn can be obtained from the command. the

Scheduling and pipeline stall signals can then be generated. Taking CallEn0 and Stall0 as examples, the situation generated by CallEn0 is (iCCtrl0&&!iCStat0)&&!Called0, that is, pipeline B is configured to work without clustering and pipeline B is idle and the requests before pipeline B have been processed. The situation generated by Stall0 is iCCtrl0&&iCStat0||(!iCState0&&CallBlkEn&&!Called0), one is to configure pipeline B to work without clustering and pipeline B is busy, and the other is to configure pipeline B to work without clustering, pipeline B is idle but blocked able. The generation of CallEn1, CallEn2 and Stall1, Stall2 is similar. Finally, the combination of the three situations can produce the correct scheduling enable and pipeline stall. The generation circuit of CallEn is shown in Figure 7, and the generation circuit of StallEn is shown in Figure 8. It can be seen that the generation logic is relatively simple, and this device efficiently realizes the synchronization of the pipeline. the

In this way, the synchronization of the dual pipelines is realized, and the configuration pipelines can safely schedule the computing pipelines to meet the needs of large-scale computing. This synchronization idea is also applicable to the synchronization of multiple pipelines, as long as a similar synchronization circuit is realized. the

The specific embodiments described above have further described the purpose, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above descriptions are only specific embodiments of the present invention, and are not intended to limit the present invention. Within the spirit and principles of the present invention, any modifications, equivalent replacements, improvements, etc., shall be included in the protection scope of the present invention. the

Claims (4)

1. multiple pipeline synchronous device, comprise: the location of instruction (106), configuration assembly line A (104), arithmetic pipelining B (105), pipeline synchronization device (100), wherein pipeline synchronization device (100) comprises state of a control register transfer unit (101), pipeline register delivery unit (102) and synchronous logic unit (103), assembly line A (104) further comprises general register (107), streamline B (105) further comprises state of a control register (108), pipeline configuration register (109), wherein state of a control register transfer unit (101) realize the state of a control register transfer between streamline, comprise that assembly line A (104) is to the control register configuration operation of streamline B (105), and assembly line A (104) is to the status register read operation of streamline B (105), pipeline register delivery unit (102) is realized the transmission of general register (107) and pipeline configuration register (109), synchronous logic unit (103) is for the synchronizing function that realizes between streamline, control register is used for controlling streamline B (105) and is in which kind of compute mode, the busy-idle condition of status register reflection streamline B (105), the location of instruction (106) provides instruction for pipeline register delivery unit (102), general register (107) is used for providing input to state of a control register and pipeline configuration register, pipeline configuration register (109) provides streamline B operation required configuration information.

2. device according to claim 1, is characterized in that, assembly line A is the configuration flow waterline, is used for streamline B is dispatched; Streamline B is arithmetic pipelining, is used for satisfying extensive computing demand.

3. system according to claim 2, is characterized in that, streamline B is divided into two bunches of X, Y, and three kinds of working methods are arranged, and is respectively only Y work in only X work, sub-clustering situation in not sub-clustering work, sub-clustering situation.

4. system according to claim 3, it is characterized in that, control register represents with CCtrl, status register represents with CStat, it is all the 3bit register, control register CCtrl is xx0, represent not sub-clustering work, only X work in 011 expression sub-clustering situation, only Y work in 101 expression sub-clustering situations, status register CStat[0] busy-idle condition of the dirty waterline B of not sub-clustering of indication situation, 1 for busy, CStat[1] busy-idle condition of X bunch in the dirty waterline B of indication sub-clustering situation, 1 for busy, CStat[2] busy-idle condition of Y bunch in the dirty waterline B of indication sub-clustering situation.

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