CN103390548A - Method for preparing gate silicon oxide layers and method for processing semiconductor substrate - Google Patents
Method for preparing gate silicon oxide layers and method for processing semiconductor substrate Download PDFInfo
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Abstract
本发明提供一种栅氧化硅层的制备方法及半导体衬底处理方法，预先在低压器件区注入氮离子以及在高压器件区注入氟离子，使得在热氧化半导体衬底表面生长栅氧化硅层时，低压器件区的栅氧化硅层的生长得到抑制，高压器件区的栅氧化硅层的生长得到促进，进而形成不同厚度的栅氧化硅层，大大简化了工艺流程；进一步在半导体衬底中锗和/或硅预非晶化注入，提高了沟道载流子迁移率；并且在非晶化注入和氟氮离子注入后的退火再结晶过程中，硅衬底表面特性会得到优化，有利于随后的栅氧化层的可靠性提高；而且这种工艺处理使得低压器件区氮浓度分布的峰值靠近栅氧化硅层表面，可有效阻挡后续来自P+多晶硅的硼穿透，增强低压器件区薄栅氧化硅层的可靠性。
The invention provides a method for preparing a gate silicon oxide layer and a method for treating a semiconductor substrate. Nitrogen ions are implanted in the low-voltage device region and fluorine ions are implanted in the high-voltage device region in advance, so that when the gate silicon oxide layer is grown on the surface of the thermally oxidized semiconductor substrate , the growth of the gate silicon oxide layer in the low-voltage device region is suppressed, and the growth of the gate silicon oxide layer in the high-voltage device region is promoted, thereby forming gate silicon oxide layers with different thicknesses, which greatly simplifies the process flow; further, germanium in the semiconductor substrate And/or silicon pre-amorphization implantation, which improves the channel carrier mobility; and in the annealing and recrystallization process after amorphization implantation and fluorine nitrogen ion implantation, the surface characteristics of the silicon substrate will be optimized, which is beneficial to The reliability of the subsequent gate oxide layer is improved; and this process makes the peak of the nitrogen concentration distribution in the low-voltage device region close to the surface of the gate silicon oxide layer, which can effectively block the subsequent boron penetration from P+ polysilicon, and enhance the thin gate oxidation of the low-voltage device region Silicon layer reliability.
Description
Technical field
The present invention relates to field of semiconductor manufacture, relate in particular to a kind of preparation method and Semiconductor substrate processing method of grid silicon oxide layer.
Background technology
Along with microelectronic industry, the develop rapidly of very lagre scale integrated circuit (VLSIC) (ULSI), Dual Gate Oxide technique (Dual Gate Oxide, DGO) high tension apparatus and low-voltage device are integrated on same chip, be the key process technology in producing process of deep submicron integrated circuit, directly affect and determined electrology characteristic and the reliability of device.Its need to grow simultaneously on same chip grid silicon oxide layer of two kinds of thickness, with the transistor of preparation work in different voltages.
As shown in Figure 1, in prior art, CMOS high voltage integrated circuit (High-Voltage Integrated Circuits with the standard CMOS process compatibility, HVIC) in, partly produce control signal by low voltage logic and control high-pressure section work, its output rises to a level high by the high-voltage driving circuit that comprises high tension apparatus.So CMOS manufacturing technology of high voltage integrated circuit, general high voltage device regions II, the III that isolates at the device isolation structure 101 of substrate 100 makes high pressure NMOS and the PMOS device that is used for realizing input/output operations, at core devices (Core device) the district I that device isolation structure 101 isolates, makes for the low voltage CMOS device of realizing the logic control high-pressure section.Because the grid source of high voltage PMOS need to be worked under the high pressure of 100V left and right, thereby high voltage PMOS device need adopt thick grid oxygen technique (as shown in Fig. 1 104) to realize that high grid source is withstand voltage.And low voltage CMOS device and high pressure NMOS can adopt thin grid oxygen technique (as shown in Fig. 1 102,103) to realize.And require to contain a small amount of nitrogen element in wherein thin-grid silicon oxide layer 102, to stop the boron penetration (B penetration) from the P+ polycrystalline and to improve Si-SiO between substrate silicon and grid silicon oxide layer
2Interfacial characteristics, the reliability of enhancing thin-grid silicon oxide layer 102.
In order to achieve the above object, nitrogen element in thin-grid silicon oxide layer distributes and wishes to meet following the requirement: the peak value that the nitrogen concentration of element distributes is near grid silicon oxide layer surface (being the interface of polysilicon and grid oxide layer), and the atom content of 1%-3% is arranged, can effectively stop like this boron penetration from the P+ polycrystalline; On the other hand, the interface between grid oxide layer and substrate silicon only needs a small amount of nitrogen element, both can improve the interfacial characteristics between substrate silicon and grid oxide layer, strengthens the reliability of thin-grid silicon oxide layer, can not affect again the mobility of charge carrier in following raceway groove.But in present technique, the peak value that the nitrogen concentration of element distributes is always at the interface near between grid silicon oxide layer and substrate silicon, rather than the ideal distribution of foregoing description, and such distribution can reduce the mobility of charge carrier in raceway groove.yet, the Dual Gate Oxide technique of commonly using now, all generally Mr. voltage device region II that grows tall, after the thick gate oxidation silicon 104 and the first thin oxide gate silicon 103 of III, the thickness of second thin oxide gate silicon 102(the second thin oxide gate silicon 102 of regrowth low-voltage device district I is relatively minimum, the thickness of the first thin oxide gate silicon 103 is placed in the middle, the thickness of thick gate oxidation silicon 104 is relatively maximum), and then the second thin oxide gate silicon 102 is carried out nitrogen treatment, thereby make thick, nitrogen concentration of element distribution peak value in thin two kinds of gate oxidation silicon is all in close silicon face one side, have a strong impact on thick, the mobility of two kinds of transistorized channel carriers of thin grid, this Dual Gate Oxide technique of while, repeatedly thermal oxidation technology and repeatedly wet etching or Self-aligned etching technique, make technique very complicated usually.
Summary of the invention
The object of the present invention is to provide a kind of preparation method and Semiconductor substrate processing method of grid silicon oxide layer, can be by thermal oxidation technology and on a chip grid silicon oxide layer of a plurality of different-thickness of growth, technique is simple.
In order to address the above problem, the invention provides a kind of preparation method of grid silicon oxide layer, comprise the following steps:
Semiconductor substrate with low-voltage device district and high voltage device regions is provided;
Semiconductor substrate surface in described low-voltage device district carries out the nitrogen Implantation, carries out fluorine ion at the semiconductor substrate surface of described high voltage device regions and injects;
The described semiconductor substrate surface of thermal oxidation is with the growth grid silicon oxide layer, and described high voltage device regions is thicker than the grid silicon oxide layer in low-voltage device district.
Further, before described nitrogen Implantation and fluorine ion inject, the semiconductor substrate surface of described low-voltage device district and high voltage device regions is carried out germanium and/or the pre-amorphous injection of silicon ion.
Further, the energy of described pre-amorphous injection is 10KeV ~ 50KeV, and dosage is 1E14/cm
2~ 1.5E15/cm
2, angle is 2 ~ 30 °.
Further, the energy of described nitrogen Implantation is 0.2KeV ~ 3KeV, and dosage is 1E14/cm
2~ 2.5E15/cm
2, angle is 2 ~ 30 °.
Further, the energy that described fluorine ion injects is 0.2KeV ~ 10KeV, and dosage is 1E14/cm
2~ 2.5E15/cm
2, angle is 2 ~ 30 °.
Further, described high voltage device regions comprises the first high voltage device regions and the second high voltage device regions, and described the second high voltage device regions is larger than the dosage that the fluorine ion of the first high voltage device regions injects so that the grid silicon oxide layer that thermal oxidation forms in the second high voltage device regions thick than in the first high voltage device regions.
Further, the energy that the fluorine ion of described the first high voltage device regions injects is 0.2KeV ~ 5KeV, and dosage is 1E14/cm
2~ 1.5E15/cm
2, angle is 2 ~ 30 °; The energy that the fluorine ion of described the second high voltage device regions injects is 1KeV ~ 10KeV, and dosage is 3E14/cm
2~ 2.5E15/cm
2, angle is 2 ~ 30 °.
Further, provide the step of the Semiconductor substrate with low-voltage device district and high voltage device regions to comprise:
Silicon substrate is provided, forms device isolation structure in described silicon substrate, to keep apart low-voltage device district and high voltage device regions;
Form pad oxide on described silicon substrate;
Carry out trap Implantation and annealing in described silicon substrate;
The described pad oxide of etching, to expose the channel region of low-voltage device district and high voltage device regions.
Further, described nitrogen Implantation and fluorine ion carry out before or after being infused in the described pad oxide of etching.
Further, the technical recipe of described thermal oxidation comprises dried oxygen and wet oxygen growth, and the technological parameter of described dried oxide growth comprises: oxygen flow is 0.3L/min ~ 1.5L/min, and nitrogen flow is 1L/min ~ 20L/min, air pressure is 0.5atm ~ 1.5atm, temperature 700 ~ 800oC; The technological parameter of described wet oxygen growth: the steam flow is 0.1L/min ~ 1L/min, and nitrogen flow is 1L/min ~ 20L/min, and air pressure is 0.5atm ~ 1.5atm, 700 ~ 800 ° of C of temperature.
The present invention also provides a kind of Semiconductor substrate processing method, comprises the following steps:
Semiconductor substrate is provided, and described Semiconductor substrate comprises a plurality of subregions;
The nitrogen Implantation is carried out on a subregion surface in described Semiconductor substrate, carries out fluorine ion on another subregion surface of described Semiconductor substrate and injects;
The described semiconductor substrate surface of thermal oxidation is with the growth oxide layer, and the subregion that described fluorine ion injects is than the oxidation bed thickness of the subregion of described nitrogen Implantation.
Further, before described nitrogen Implantation and fluorine ion injection, described semiconductor substrate surface is carried out germanium and/or the pre-amorphous injection of silicon ion.
Further, the energy of described pre-amorphous injection is 10KeV ~ 50KeV, and dosage is 1E14/cm
2~ 1.5E15/cm
2, angle is 2 ~ 30 °.
Further, the energy of described nitrogen Implantation is 0.2KeV ~ 3KeV, and dosage is 1E14/cm
2~ 2.5E15/cm
2, angle is 2 ~ 30 °.
Further, the energy that described fluorine ion injects is 0.2KeV ~ 10KeV, and dosage is 1E14/cm
2~ 2.5E15/cm
2, angle is 2 ~ 30 °.
Further, the technical recipe of described thermal oxidation comprises dried oxygen and wet oxygen growth, and the technological parameter of described dried oxide growth comprises: oxygen flow is 0.3L/min ~ 1.5L/min, and nitrogen flow is 1L/min ~ 20L/min, air pressure is 0.5atm ~ 1.5atm, temperature 700 ~ 800oC; The technological parameter of described wet oxygen growth: the steam flow is 0.1L/min ~ 1L/min, and nitrogen flow is 1L/min ~ 20L/min, and air pressure is 0.5atm ~ 1.5atm, 700 ~ 800 ° of C of temperature.
Compared with prior art, the preparation of grid silicon oxide layer provided by the invention and Semiconductor substrate processing method, inject fluorine ion at low-voltage device district injecting nitrogen ion and in high voltage device regions in advance, make when thermal oxidation semiconductor substrate surface growth oxide layer, the growth of the oxide layer in low-voltage device district is inhibited, the growth of the oxide layer of high voltage device regions is promoted, and then can form the oxide layer of different-thickness in a thermal oxide growth technique, has greatly simplified technological process; Further, the pre-amorphous injection of germanium and/or silicon in Semiconductor substrate, the channeling effect of reduction Implantation, reduce the diffusion of follow-up ion, improved the channel carrier mobility; And the annealing recrystallization process after decrystallized injection and fluorine, nitrogen Implantation, the surface of silicon characteristic can be optimized, and the reliability that is conducive to oxide layer subsequently improves; And the peak value that this PROCESS FOR TREATMENT makes low-voltage device district nitrogen concentration profile can effectively stop follow-up boron penetration from the P+ polysilicon near the grid silicon oxide layer surface, the reliability of enhancing low-voltage device district thin-grid silicon oxide layer.
Description of drawings
Fig. 1 is the sectional structure chart of the CMOS high voltage integrated circuit structure of a kind of of prior art and standard CMOS process compatibility;
Fig. 2 is preparation method's flow chart of the grid silicon oxide layer of the embodiment of the present invention one;
Fig. 3 A ~ 3C is the device architecture cutaway view in the preparation process of grid silicon oxide layer of the embodiment of the present invention one;
Fig. 4 is preparation method's flow chart of the grid silicon oxide layer of the embodiment of the present invention two;
Fig. 5 A ~ 5C is the device architecture cutaway view in the preparation process of grid silicon oxide layer of the embodiment of the present invention two;
Fig. 6 is the variation schematic diagram of silicon oxide layer thickness with nitrogen ion implantation dosage and fluorine ion implantation dosage;
Fig. 7 is the Semiconductor substrate process flow figure of the embodiment of the present invention three.
Embodiment
Preparation method to the grid silicon oxide layer of the present invention's proposition is described in further detail below in conjunction with the drawings and specific embodiments.
Embodiment one
As shown in Figure 2, this enforcement provides a kind of preparation method of grid silicon oxide layer, comprises the following steps:
S21, provide silicon substrate, forms device isolation structure in described silicon substrate, to keep apart low-voltage device district and high voltage device regions;
S22, form pad oxide on described silicon substrate;
S23, carry out trap Implantation and annealing in described silicon substrate;
S24, the described pad oxide of etching, to expose the channel region of low-voltage device district and high voltage device regions;
S25, carry out the pre-amorphous injection of germanium ion to the semiconductor substrate surface of described low-voltage device district and high voltage device regions;
S26, the semiconductor substrate surface in described low-voltage device district carries out the nitrogen Implantation, carries out fluorine ion at the semiconductor substrate surface of described high voltage device regions and injects;
S27, the described semiconductor substrate surface of thermal oxidation is with the growth grid silicon oxide layer, and described high voltage device regions is thicker than the grid silicon oxide layer in low-voltage device district.
Please refer to Fig. 3 A, in step S21, the silicon substrate 300 that provides can be the pure silicon substrate, it can be also germanium silicon (SiGe) substrate, can also be silicon-on-insulator substrate, then etch silicon substrate 300 forms shallow trench, and fill oxide in the shallow trench after etching, form fleet plough groove isolation structure (STI) 301, by STI 301, isolate low-voltage device district I, the first high voltage device regions II and the second high voltage device regions III.
Please continue the 3A with reference to figure, in step S22, by techniques such as ald, plasma enhanced chemical vapor deposition and physical vapor depositions, form pad oxide 302 on described silicon substrate 300.Described pad oxide 302 provides buffering for the hard mask layer that forms before follow-up Implantation, can also be as the stop-layer in follow-up removal hard mask layer step.
Please continue the 3A with reference to figure, in step S23, first form the hard mask layer of well region Implantation on pad oxide 302, then carry out boron and inject to form P well region (not shown) in described silicon substrate 300, and carry out arsenic or phosphorus injection N well region (not shown); Then remove the hard mask layer of the well region Implantation that forms.
Please continue the 3A with reference to figure, in step S24, the described pad oxide 302 of etching, to expose low-voltage device district I, the first high voltage device regions II and the second high voltage device regions III, that is, only keep the pad oxide 302 on STI 301.
Please continue the 3A with reference to figure, in step S25, form pre-amorphous injection hard mask layer on pad oxide 302, then take the pre-amorphous injection hard mask layer that forms as mask, carry out germanium (Ge) or the pre-amorphous injection of silicon ion on silicon substrate 300 surfaces that expose low-voltage device district I, the first high voltage device regions II and the second high voltage device regions III, and carry out annealing, make the silicon on silicon substrate 300 surfaces become noncrystalline state by monocrystalline state.Before follow-up Implantation, the germanium that injects or silicon ion make silicon substrate 300 surfaces pre-amorphous, can reduce the channeling effect of follow-up Implantation, reduce Impurity Diffusion, therefore pre-amorphous injection can realize shallow junction and precipitous Impurity Distribution, and can improve impurity activation by the annealing process after pre-amorphous Implantation; Then remove the pre-amorphous injection hard mask layer that forms.
Preferably, the energy of the pre-amorphous injection of described germanium ion is 10KeV ~ 50KeV, and dosage is 1E14/cm
2~ 1.5E15/cm
2, angle is 2 ~ 30 °.
Please refer to Fig. 3 B, in step S26, form nitrogen and inject the hard mask layer (not shown) on pad oxide 302, this nitrogen injects hard mask layer and exposes the channel region of low-voltage device district I, then inject hard mask layer as mask take the nitrogen that forms, at the channel region that exposes low-voltage device district I, inject the nitrogen plasma; Then, remove the nitrogen that forms and inject hard mask layer; Then, form the first fluorine and inject the hard mask layer (not shown) on pad oxide 302, this first fluorine injects hard mask layer and exposes the channel region of the first high voltage device regions II, then inject hard mask layer as mask take the first fluorine that forms, at the channel region that exposes the first high voltage device regions II, inject the fluorine plasma; Then, remove the first fluorine that forms and inject hard mask layer; Then, form the second fluorine and inject the hard mask layer (not shown) on pad oxide 302, this second fluorine injects hard mask layer and exposes the channel region of the second high voltage device regions III, then inject hard mask layer as mask take the second fluorine that forms,, with the fluorine ion implantation dosage larger than the first high voltage device regions, at the channel region that exposes the second high voltage device regions III, inject the fluorine plasma; Then, remove the second fluorine that forms and inject hard mask layer.The fluorine of the pre-amorphous injection of germanium in step S25 and/or silicon and step S26, the annealing recrystallization process after the nitrogen Implantation, the substrate surface characteristic can be optimized, and the reliability that is conducive to gate oxide subsequently improves; And the peak value that this PROCESS FOR TREATMENT makes low-voltage device district nitrogen concentration profile can effectively stop follow-up boron penetration from the P+ polysilicon near the grid silicon oxide layer surface, the reliability of enhancing low-voltage device district thin-grid silicon oxide layer.
Please refer to Fig. 3 C, in step S27, thickness requirement according to the gate oxide of low-voltage device and high tension apparatus, set corresponding thermal oxidation technology formula (gate oxide recipe), according to this technical recipe thermal oxidation silicon substrate surface, and then grow the grid silicon oxide layer of low-voltage device district I, the first high voltage device regions II and the second high voltage device regions III.
Need to prove, as shown in Figure 6, find after tested, in the situation that other technological parameters are identical, for example the nitrogen Implantation Energy is that 0.7KeV or fluorine inject 1KeV, the thickness of thermal oxidation silicon substrate growing silicon oxide layer reduces with the increase of nitrogen (N) ion implantation dosage, increase with fluorine (F) ion implantation dosage increases, and the thermal oxidation technology parameter of adjusting nitrogen (N) ion implantation dosage, fluorine (F) ion implantation dosage and corresponding Controlling Growth Rate just can be adjusted the device grid silicon oxide layer thickness of thermal oxide growth.Therefore.Please refer to Fig. 3 C, by the thermal oxidation technology formula set can so that the thickness of the grid silicon oxide layer 304 of low-voltage device district I less than the thickness of the grid silicon oxide layer 305 of the first high voltage device regions II, the thickness of the grid silicon oxide layer 305 of the first high voltage device regions II is less than the thickness of the grid silicon oxide layer 306 of the second high voltage device regions III.
Preferably, the energy of described nitrogen Implantation is 0.2KeV ~ 3KeV, and dosage is 1E14/cm
2~ 2.5E15/cm
2, angle is 2 ~ 30 °.
Preferably, the energy that the fluorine ion of described the first high voltage device regions injects is 0.2KeV ~ 5KeV, and dosage is 1E14/cm
2~ 1.5E15/cm
2, angle is 2 ~ 30 °; The energy that the fluorine ion of described the second high voltage device regions injects is 1KeV ~ 10KeV, and dosage is 3E14/cm
2~ 2.5E15/cm
2, angle is 2 ~ 30 °.
Preferably, the technical recipe of described thermal oxidation comprises dried oxygen and wet oxygen growth, and the technological parameter of described dried oxide growth comprises: oxygen flow is 0.3L/min ~ 1.5L/min, and nitrogen flow is 1L/min ~ 20L/min, air pressure is 0.5atm ~ 1.5atm, temperature 700 ~ 800oC; The technological parameter of described wet oxygen growth: the steam flow is 0.1L/min ~ 1L/min, and nitrogen flow is 1L/min ~ 20L/min, and air pressure is 0.5atm ~ 1.5atm, 700 ~ 800 ° of C of temperature.
In the successive process of CMOS integrated circuit, can carry out polysilicon deposition, then etch polysilicon and grid silicon oxide layer 304,305,306 on the device architecture that step S27 forms, to form the stacked gate architectures of low-voltage device district I, the first high voltage device regions II and the second high voltage device regions III.
The preparation method of the grid silicon oxide layer that provides of the present embodiment, the pre-amorphous injection of germanium and/or silicon in Semiconductor substrate, then at low-voltage device district injecting nitrogen ion and in high voltage device regions, inject fluorine ion, make when thermal oxidation semiconductor substrate surface growth grid silicon oxide layer, the growth of the grid silicon oxide layer in low-voltage device district is inhibited, the growth of the grid silicon oxide layer of high voltage device regions is promoted, and then can form the grid silicon oxide layer of different-thickness in a thermal oxide growth technique, greatly simplified technological process; The pre-amorphous injection of germanium and/or silicon simultaneously reduces the channeling effect of Implantation, reduce the diffusion of follow-up ion, improved the channel carrier mobility, and the annealing recrystallization process after decrystallized injection and fluorine, nitrogen Implantation, the substrate surface characteristic can be optimized, and the reliability that is conducive to grid silicon oxide layer subsequently improves; And the peak value that this PROCESS FOR TREATMENT makes low-voltage device district nitrogen concentration profile can effectively stop follow-up boron penetration from the P+ polysilicon near the grid silicon oxide layer surface, the reliability of enhancing low-voltage device district thin-grid silicon oxide layer.
Embodiment two
As shown in Figure 4, this enforcement provides a kind of preparation method of grid silicon oxide layer, comprises the following steps:
S41, provide silicon substrate, forms device isolation structure in described silicon substrate, to keep apart low-voltage device district and high voltage device regions;
S42, form pad oxide on described silicon substrate;
S43, carry out trap Implantation and annealing in described silicon substrate;
S44, carry out the pre-amorphous injection of germanium ion to the semiconductor substrate surface of described low-voltage device district and high voltage device regions;
S45, the semiconductor substrate surface in described low-voltage device district carries out the nitrogen Implantation, carries out fluorine ion at the semiconductor substrate surface of described high voltage device regions and injects;
S46, the described pad oxide of etching, to expose the channel region of low-voltage device district and high voltage device regions;
S47, the described semiconductor substrate surface of thermal oxidation is with the growth grid silicon oxide layer, and described high voltage device regions is thicker than the grid silicon oxide layer in low-voltage device district.
Please refer to Fig. 5 A, in step S41, the silicon substrate 500 that provides can be the pure silicon substrate, it can be also germanium silicon (SiGe) substrate, can also be silicon-on-insulator substrate, then can form shallow trench by etch silicon substrate 500, and fill oxide in the shallow trench after etching, form fleet plough groove isolation structure (STI) 501, by STI 501, isolate low-voltage device district I, the first high voltage device regions II and the second high voltage device regions III.
Please continue the 5A with reference to figure, in step S42, by techniques such as ald, plasma enhanced chemical vapor deposition and physical vapor depositions, form pad oxide 502 on described silicon substrate 500.Described pad oxide 502 provides resilient coating for the hard mask layer that forms before follow-up Implantation and can be used as stop-layer in follow-up removal hard mask layer step.
Please continue the 5A with reference to figure, in step S43, first form the hard mask layer of well region Implantation on pad oxide 502, then carry out boron and inject to form P well region (not shown) in described silicon substrate 500, and carry out arsenic or phosphorus injection N well region (not shown); Then remove the hard mask layer of the well region Implantation that forms.
Please continue the 5A with reference to figure, in step S44, form pre-amorphous injection hard mask layer on pad oxide 502, then take the pre-amorphous injection hard mask layer that forms as mask, carry out germanium (Ge) or the pre-amorphous injection of silicon ion on silicon substrate 500 surfaces that expose low-voltage device district I, the first high voltage device regions II and the second high voltage device regions III, and carry out annealing, make the silicon on silicon substrate 500 surfaces become noncrystalline state by monocrystalline state.Before follow-up Implantation, the germanium that injects or silicon ion make silicon substrate 500 surfaces pre-amorphous, can reduce the channeling effect of follow-up Implantation, reduce Impurity Diffusion, therefore pre-amorphous injection can realize shallow junction and precipitous Impurity Distribution, and can improve impurity activation by the annealing process after pre-amorphous Implantation; Then remove the pre-amorphous injection hard mask layer that forms.
Preferably, the energy of the pre-amorphous injection of described germanium ion is 10KeV ~ 50KeV, and dosage is 1E14/cm
2~ 1.5E15/cm
2, angle is 2 ~ 30 °.
Please refer to Fig. 5 B, in step S45, form nitrogen and inject the hard mask layer (not shown) on pad oxide 502, this nitrogen injects hard mask layer and exposes the channel region of low-voltage device district I, then inject hard mask layer as mask take the nitrogen that forms, at the channel region that exposes low-voltage device district I, inject the nitrogen plasma; Then, remove the nitrogen that forms and inject hard mask layer; Then, form the first fluorine and inject the hard mask layer (not shown) on pad oxide 502, this first fluorine injects hard mask layer and exposes the channel region of the first high voltage device regions II, then inject hard mask layer as mask take the first fluorine that forms, at the channel region that exposes the first high voltage device regions II, inject the fluorine plasma; Then, remove the first fluorine that forms and inject hard mask layer; Then, form the second fluorine and inject the hard mask layer (not shown) on pad oxide 502, this second fluorine injects hard mask layer and exposes the channel region of the second high voltage device regions III, then inject hard mask layer as mask take the second fluorine that forms,, with the fluorine ion implantation dosage larger than the first high voltage device regions, at the channel region that exposes the second high voltage device regions III, inject the fluorine plasma; Then, remove the second fluorine that forms and inject hard mask layer.Annealing recrystallization process after the fluorine nitrogen Implantation of the pre-amorphous injection of germanium in step S44 and/or silicon and step S45, the surface of silicon characteristic can be optimized, and the reliability that is conducive to gate oxide subsequently improves; And the peak value that this PROCESS FOR TREATMENT makes low-voltage device district nitrogen concentration profile can effectively stop follow-up boron penetration from the P+ polysilicon near the grid silicon oxide layer surface, the reliability of enhancing low-voltage device district thin-grid silicon oxide layer.
Please refer to Fig. 5 C, in step S46, the described pad oxide 502 of etching, to expose low-voltage device district I, the first high voltage device regions II and the second high voltage device regions III.
Please refer to Fig. 5 C, in step S47, thickness requirement according to the gate oxide of low-voltage device and high tension apparatus, set corresponding thermal oxidation technology formula (gate oxide recipe), according to this technical recipe thermal oxidation silicon substrate surface, and then grow the grid silicon oxide layer of low-voltage device district I, the first high voltage device regions II and the second high voltage device regions III.Wherein, the thickness of the grid silicon oxide layer 504 of low-voltage device district I is less than the thickness of the grid silicon oxide layer 505 of the first high voltage device regions II, and the thickness of the grid silicon oxide layer 505 of the first high voltage device regions II is less than the thickness of the grid silicon oxide layer 506 of the second high voltage device regions III.
Preferably, the energy of described nitrogen Implantation is 0.2KeV ~ 3KeV, and dosage is 1E14/cm
2~ 2.5E15/cm
2, angle is 2 ~ 30 °.
Preferably, the energy that the fluorine ion of described the first high voltage device regions injects is 0.2KeV ~ 5KeV, and dosage is 1E14/cm
2~ 1.5E15/cm
2, angle is 2 ~ 30 °; The energy that the fluorine ion of described the second high voltage device regions injects is 1KeV～10KeV, and dosage is 3E14/cm
2~ 2.5E15/cm
2, angle is 2 ~ 30 °.
Preferably, the technical recipe of described thermal oxidation comprises dried oxygen and wet oxygen growth, and the technological parameter of described dried oxide growth comprises: oxygen flow is 0.3L/min～1.5L/min, and nitrogen flow is 1L/min ~ 20L/min, air pressure is 0.5atm～1.5atm, temperature 700 ~ 800oC; The technological parameter of described wet oxygen growth: the steam flow is 0.1L/min ~ 1L/min, and nitrogen flow is 1L/min ~ 20L/min, and air pressure is 0.5atm～1.5atm, 700 ~ 800 ° of C of temperature.
In the successive process of CMOS integrated circuit, can carry out polysilicon deposition, then etch polysilicon and grid silicon oxide layer 504,505,506 on the device architecture that step S47 forms, to form the stacked gate architectures of low-voltage device district I, the first high voltage device regions II and the second high voltage device regions III.
The preparation method of the grid silicon oxide layer that the present embodiment provides, compare with embodiment one, before the etching of pad oxide is adjusted to thermal oxide growth gate oxidation silicon, equally also only need one thermal oxidation technology can obtain the grid silicon oxide layer of low-voltage device district and high voltage device regions different-thickness.
Embodiment three
As shown in Figure 7, the present embodiment provides a kind of Semiconductor substrate processing method, comprises the following steps:
S71, provide Semiconductor substrate, and described Semiconductor substrate comprises a plurality of subregions;
S72, carry out the nitrogen Implantation on a subregion surface of described Semiconductor substrate, carries out fluorine ion on another subregion surface of described Semiconductor substrate and inject;
S73, the described semiconductor substrate surface of thermal oxidation is with the growth oxide layer, and the subregion that described fluorine ion injects is than the oxidation bed thickness of the subregion of described nitrogen Implantation.
The Semiconductor substrate that provides in step S71 comprises a plurality of subregions, and these subregions can be the high voltage device regions described in embodiment one and embodiment two and low-voltage device district, also can be the device isolation groove.
The concrete operations of step S72 can reference example one step S26 and the step S45 of embodiment two; The concrete operations of step S63 can reference example one step S27 and the step S47 of embodiment two.
Need to prove, as shown in Figure 6, find after tested, in the situation that other technological parameters are identical, for example the nitrogen Implantation Energy is that 0.7KeV or fluorine inject 1KeV, the thickness of thermal oxidation substrate growth oxide layer reduces with the increase of nitrogen (N) ion implantation dosage, increase with fluorine (F) ion implantation dosage increases, and adjusts the thermal oxidation technology parameter of nitrogen (N) ion implantation dosage, fluorine (F) ion implantation dosage and corresponding Controlling Growth Rate and just can adjust the oxidated layer thickness of thermal oxide growth.
Preferably, the energy of described nitrogen Implantation is 0.2KeV ~ 3KeV, and dosage is 1E14/cm
2~ 2.5E15/cm
2, angle is 2 ~ 30 °; The energy that described fluorine ion injects is 0.2KeV ~ 10KeV, and dosage is 1E14/cm
2~ 2.5E15/cm
2, angle is 2 ~ 30 °.
Preferably, before described nitrogen Implantation and fluorine ion injection, described semiconductor substrate surface is carried out germanium and/or the pre-amorphous injection of silicon ion, to reduce the channeling effect of Implantation, reduce the diffusion of follow-up ion, improved the channel carrier mobility, preferred, the energy of described pre-amorphous injection is 10KeV ~ 50KeV, and dosage is 1E14/cm
2~ 1.5E15/cm
2, angle is 2 ~ 30 °.
Preferably, the technical recipe of described thermal oxidation comprises dried oxygen and wet oxygen growth, and the technological parameter of described dried oxide growth comprises: oxygen flow is 0.3L/min ~ 1.5L/min, and nitrogen flow is 1L/min ~ 20L/min, air pressure is 0.5atm ~ 1.5atm, temperature 700 ~ 800oC; The technological parameter of described wet oxygen growth: the steam flow is 0.1L/min ~ 1L/min, and nitrogen flow is 1L/min ~ 20L/min, and air pressure is 0.5atm ~ 1.5atm, 700 ~ 800 ° of C of temperature.
The semiconductor processing that the present embodiment provides, inject nitrogen and the fluorine of variable concentrations by the subregion different, just can go out the oxide layer of different-thickness at different subregion thermal oxide growths, greatly simplify the oxide layer manufacturing process flow in same substrate different-thickness zone; Annealing recrystallization process after while germanium and/or the pre-amorphous injection of silicon and fluorine, nitrogen Implantation, the substrate surface characteristic can be optimized, and is conducive to the reliability of the oxide layer of thermal oxide growth subsequently and improves.
In sum, the preparation method of grid silicon oxide layer and Semiconductor substrate processing method, inject fluorine ion at low-voltage device district injecting nitrogen ion and in high voltage device regions in advance, make when thermal oxidation semiconductor substrate surface growth grid silicon oxide layer, the growth of the grid silicon oxide layer in low-voltage device district is inhibited, the growth of the grid silicon oxide layer of high voltage device regions is promoted, and then forms the grid silicon oxide layer of different-thickness, has greatly simplified technological process; The further pre-amorphous injection of germanium and/or silicon in Semiconductor substrate, improved the channel carrier mobility; And the annealing recrystallization process after decrystallized injection and fluorine nitrogen Implantation, the surface of silicon characteristic can be optimized, and the reliability that is conducive to gate oxide subsequently improves; And the peak value that this PROCESS FOR TREATMENT makes low-voltage device district nitrogen concentration profile can effectively stop follow-up boron penetration from the P+ polysilicon near the grid silicon oxide layer surface, the reliability of enhancing low-voltage device district thin-grid silicon oxide layer.
Obviously, those skilled in the art can carry out various changes and modification and not break away from the spirit and scope of the present invention invention.Like this, if within of the present invention these are revised and modification belongs to the scope of the claims in the present invention and equivalent technologies thereof, the present invention also is intended to comprise these changes and modification interior.
Claims (16)
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| CN112382612A (en) * | 2020-11-04 | 2021-02-19 | 上海华力集成电路制造有限公司 | Method for preparing gate oxide layer |
| CN112582272A (en) * | 2020-12-11 | 2021-03-30 | 长江存储科技有限责任公司 | Semiconductor device and method for manufacturing the same |
| CN113380799A (en) * | 2021-05-28 | 2021-09-10 | 重庆中科渝芯电子有限公司 | Low dislocation density high reliability high and low voltage CMOS self-aligned double-well process and device |
| CN115995390A (en) * | 2023-02-24 | 2023-04-21 | 上海华力集成电路制造有限公司 | Method for Improving Electrical Mismatch of MOS Devices |
| CN119698053A (en) * | 2025-02-21 | 2025-03-25 | 合肥晶合集成电路股份有限公司 | Method for manufacturing semiconductor device |
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