CN103390646B - Semiconductor element and its manufacturing method - Google Patents

Abstract

The present invention discloses a semiconductor element and a manufacturing method thereof, wherein the semiconductor element comprises: a semiconductor deposition layer formed on an insulating structure and a substrate; the semiconductor element further comprises a gate formed on a contact region between a first injection region and a second injection region of the semiconductor deposition layer; both the first injection region and the second injection region have a first conductivity type, and the gate has a second conductivity type; the semiconductor element may further comprise a second gate formed under the semiconductor deposition layer.

Description

Semiconductor element and its manufacturing method

technical field

The present invention relates to a semiconductor technology, in particular to a Junction Field Effect Transistor (JEFT) element and a manufacturing method thereof.

Background technique

A known junction field effect transistor element has a structure as shown in FIG. 1 . The junction field effect transistor device 100 shown in FIG. 1 is formed on a semiconductor substrate 102 such as a silicon wafer. The substrate 102 can be modified by implantation processes such as diffusion doping, ion implantation or in-situ doping to introduce P-type dopants. An N-well 104 is formed in the substrate 102 to provide a channel for charge to flow between the source terminal and the drain terminal. The N well 104 can be formed by introducing N-type dopants through a known implantation process. The junction field effect transistor device 100 further includes a plurality of first injection regions 106 and a plurality of second injection regions 108 . Each of the first injection regions includes a high-concentration N-type dopant, and each first injection region can be used as a source or a drain. Each of the second implanted regions 108 includes P-type dopants, and each second implanted region can be used as a gate.

During operation, a positive drain-source voltage (V _DS ) drives charges in the N-well 104 to flow from the source to the drain. The conductivity of the N-well 104 can be controlled by a negative gate-source voltage (V _{GS )} , which induces the formation of a depletion region at each PN junction. The value of the gate-to-source voltage V _GS can be adjusted to pinch off the path of charge flow in the depletion region to turn off the JFET device 100 . The pinch off voltage is called pinch off voltage (V _P ). When JFET devices are integrated into an integrated circuit, the influence of semiconductor substrate noise can change V _P , leading to inconsistencies and defects in multiple JFET devices. Therefore, to allow for a more accurate _Vp , it is necessary to insulate the JFET element.

Contents of the invention

A first exemplary embodiment discloses a semiconductor element, including a substrate, an insulating structure formed on the substrate; and a semiconductor deposition layer formed on the insulating structure and the substrate, the semiconductor deposition layer has a first A conductivity type. The disclosed semiconductor device further includes a first implantation region formed in the semiconductor deposition layer, the first implantation region has a first conductivity type and a higher doping concentration than the semiconductor deposition layer; and a second implantation region is formed in the semiconductor deposition layer In the deposition layer, the second injection region has the first conductivity type and a higher doping concentration than the semiconductor deposition layer. The disclosed semiconductor device further includes a metal contact layer formed on a contact region between the first implantation region of the semiconductor deposition layer and the second implantation region of the semiconductor deposition layer, so as to form a contact region between the metal contact layer and the semiconductor deposition layer. A junction, wherein the junction is a Schottky barrier.

A second exemplary embodiment discloses a semiconductor device including a substrate, a first insulating structure formed on the substrate, and a first semiconductor deposition layer formed on the first insulating structure. The disclosed semiconductor device further includes a second insulating structure formed on the first semiconductor deposition layer, a second semiconductor deposition layer formed on the second insulating structure, and the second semiconductor deposition layer has a conductivity type. The disclosed semiconductor device may include a first implantation region formed in the second semiconductor deposition layer, the first implantation region has a conductivity type and a higher doping concentration than the second semiconductor deposition layer; and a second implantation region is formed in the second semiconductor deposition layer In the second semiconductor deposition layer, the second injection region has a conductivity type and a higher doping concentration than the second semiconductor deposition layer. A metal contact layer is formed on a contact region between the first injection region of the second semiconductor deposition layer and the second injection region of the second semiconductor deposition layer, so as to form a junction at the contact region between the metal layer and the second semiconductor deposition layer , where this junction is a Schottky barrier.

The related manufacturing method of the semiconductor device disclosed in the present invention is also disclosed.

Description of drawings

FIG. 1 is a cross-sectional view of a conventional junction field effect transistor.

FIG. 2 is a cross-sectional view of a junction field effect transistor disclosed in the present invention.

FIG. 3 is a partial view of a specific structure of the junction field effect transistor device of FIG. 2 .

FIG. 4 shows a front view of a junction field effect transistor device 300 with a three-dimensional gate structure.

FIG. 5 is a partial view of an embodiment of the junction field effect transistor device of FIG. 4 .

FIG. 6 is a partial view of another embodiment of the junction field effect transistor device of FIG. 4 .

FIG. 7 shows a conventional circuit including resistors.

FIG. 8 illustrates an embodiment of a circuit including the junction field effect transistor device disclosed in the present invention.

FIG. 9 shows the relationship between the source-to-gate voltage of the JFET device and the drain voltage of the MOS device in an embodiment of FIG. 8 .

[Description of main component symbols]

100, 200, 300: junction field effect transistor components

102, 202, 302: substrate

104: N well 106: First implantation region

108: Second injection area

204: Insulation structure

206, 306: field oxide layer

208: high temperature oxide layer

210: the first well area

212: semiconductor deposition layer 214, S: source

216, D: Drain

218, 324: metal contact layer

220, 326: contact area

304: first insulating structure

308: Gate oxide layer

310: first semiconductor deposition layer

312: second insulating structure

314: Second semiconductor deposition layer

316: first injection region, source

318: second injection region, drain

320: first major axis

322: second major axis

400, 500: circuit

410: resistance

420, 550: capacitance

430, 520: pulse width modulation circuit

530: HVdepletionMOS

540: diode

I _D : Current from MOS

I _IC : charging current

I _AUX : auxiliary current

V _Z : breakdown voltage

V _CC : supply voltage

V _S : Source to Gate Voltage

V _ss : Source voltage

V _gg : gate voltage

detailed description

FIG. 2 shows a cross-sectional view of a JFET device 200 that can reduce noise and increase pinch-off sharpness. The JFET device 200 includes a substrate 202 and an insulating structure 204 formed on the substrate 202 . The insulating structure 204 can be used to substantially protect the structures thereon from noise influence and interference of the underlying substrate. The insulating structure 204 may include a field oxide layer 206 (field oxide, FOX) formed on the substrate 202 , and in some embodiments, may further include a high temperature oxide layer 208 (high temperature oxide, HTO) formed on the field oxide layer 206 . Field oxide layer 206 and high temperature oxide layer 208 can be formed by known standard masking and thermal oxidation techniques. For example, the field oxide layer 206 can be formed by a local oxidation of silicon (LOCOS) process. The same process can be repeated to form the high temperature oxide layer 208 . Exemplary technologies of LOCOS include shallow trench isolation (shallow trench isolation, STI) or silicon on insulator (silicon on insulator, SO1). Although the values may vary, the field oxide layer may have a thickness ranging from 1000 angstrom to 10000 angstrom, preferably about 5000 angstrom, and the high temperature oxide layer 208 may have a thickness between 120 angstrom to 400 angstrom, preferably about 300 Angstroms.

Under the insulating structure 204 , a first well region 210 may be formed in the substrate 210 under the insulating structure 204 . In the embodiment depicted in FIG. 2 , the substrate 202 includes P-type dopants, but in another embodiment, the substrate 202 may include N-type dopants. In any embodiment, the first well region 210 can be a P well or an N well.

On the insulating structure 204, a semiconductor deposition layer 212 may be formed on the insulating structure 204 by a deposition process. The semiconductor deposition layer 212 can have a first conductivity type, allowing charges to flow from the source 214 to the drain 216 . The conductivity of the semiconductor deposition layer 212 can be controlled by the gate 218 . The structure of the junction field effect transistor device 200 will be described in detail below with reference to FIG. 3 .

FIG. 3 is a partial view of a junction field effect transistor device 200 . The semiconductor deposition layer 212 can be a polysilicon layer fabricated by standard processes, and as discussed above, the semiconductor deposition layer 212 can be modified by an implantation process to have a first conductivity type, which can be N-type or P-type. In one embodiment, the semiconductor deposition layer 212 can be formed by depositing polysilicon, and N-type dopant such as phosphorus oxychloride (POCl) can be introduced by in-situ doping during polysilicon deposition. In one embodiment, the concentration of POCl ₃ is about 1×10 ¹¹ /cm ² . Other N-type dopants such as phosphorous (P) can also be used. In another embodiment, the N-type dopant can be introduced by ion implantation diffusion doping or in-situ doping. In yet another embodiment, the P-type dopant can also be introduced into the semiconductor deposition layer 212 by the same process as that of introducing the N-type dopant. An example of a P-type dopant is boron (B).

A first implantation region 214 can be formed in the semiconductor deposition layer 212 , the first implantation region has a first conductivity type and a doping concentration higher than that of the semiconductor deposition layer 212 . The first implanted region 214 can be labeled as source 214 . A second implantation region 216 can be formed in the semiconductor deposition layer 212 , the second implantation region has the first conductivity type and has a higher doping concentration than the semiconductor deposition layer 212 . The second implanted region 216 can be labeled as the drain 216 .

In the exemplary embodiment shown in FIG. 3 , the first conductivity type is N type, and the semiconductor deposition layer 212 is operable to provide an N channel for charge to flow between the first N+ implantation region 214 and the second N+ implantation region 216 . In another embodiment, the first conductivity type may be P type, and the semiconductor deposition layer 212 may operate to provide a P channel for charge to flow between the first P+ doped region 214 and the second P+ doped region 216 .

In addition to the semiconductor deposition layer 212, the junction field effect transistor device 200 may further include a metal contact layer 218 formed on a contact region 220 of the semiconductor deposition layer 212, and the contact region 220 is located between the first implant region 214 and the second implant region. There are 216 injection areas. The metal contact layer 218 may include a suitable metal, so that the junction between the metal contact layer 218 and the contact region 220 of the semiconductor deposition layer 212 acts as a Schottky barrier. Depending on whether the semiconductor deposition layer 212 includes N-type or P-type dopants, the Schottky barrier can be used as a P-type gate or an N-type gate, respectively. The metal contact layer 218 as described above may be denoted as gate 218 . To form a P-type gate, the metal contact layer 218 may include a suitable metal such as titanium, tungsten, nickel, platinum, aluminum, gold or cobalt. To form an N-type gate, the metal contact layer 218 may include a suitable metal such as platinum (Pt).

The gate 218 is operable to control the conductivity of the channel of the semiconductor deposition layer 212 . During operation, a positive drain-source voltage (V _DS ) causes charges to flow from the source 214 of the semiconductor deposition layer 212 to the drain 216 . The conductivity of the semiconductor deposition layer 212 can be controlled by a negative gate-source voltage (V _{GS )} , which induces a depletion region in or around the contact region 220 . The value of V _GS can be adjusted to pinch off the path of charge flow in the depletion region to turn off the JFET device 200 . Depending on the thickness of the deposited semiconductor layer, the pinchoff voltage (V _P ) may vary. In an exemplary embodiment, the thickness of the semiconductor deposition layer is in a range such that V _P is between 0.7-30 volts. In another embodiment, the semiconductor deposition layer may have a thickness ranging from 500 angstroms to 6000 angstroms.

By forming the metal contact layer 218 and the semiconductor deposition layer 212 on the insulating structure 204, the noise and interference from the substrate 202 are substantially reduced, and the control of the semiconductor deposition layer 212 can be improved through the gate 218 and a more precise V _P . conductivity control. Another advantage of the disclosed structure is that the first well region 210 under the insulating structure 204 can be used to accommodate other components that may not have space to form a PN junction in a junction field effect transistor.

FIG. 4 shows a front view of a junction field effect transistor device 300 with a three-dimensional gate structure. The JFET device 300 includes a substrate 302 and a first insulating structure 304 formed on the substrate. Similar to the isolation structure 204 discussed in FIGS. 2 and 3 , the first isolation structure 304 can be used to substantially protect structures thereon from noise and interference from the underlying substrate 302 . The first insulating structure 304 may include a field oxide layer 306 formed on the substrate 302 . In some embodiments, the first insulating structure 304 may further include a gate oxide layer 308 disposed on the field oxide layer 306 . Field oxide layer 306 and gate oxide layer 308 can be formed by known standard masking and thermal oxidation techniques.

The junction field effect transistor device 300 further includes a first semiconductor deposition layer 310 formed on the first insulating structure 304, a second insulating structure 312 formed on the first semiconductor deposition layer 310, and a second insulating structure formed on the second insulating structure A second semiconductor deposition layer 314 on 312 . FIG. 5 is a partial view of the structure formed on the first insulating structure 304 in the JFET device 300 . In one embodiment, the first semiconductor deposition layer 310 and the second semiconductor deposition layer 314 may extend toward the first long axis 320 and the second long axis 322 respectively as shown in FIG. 5 . In an exemplary embodiment, the first major axis 320 is substantially orthogonal to the second major axis 322, but in another embodiment, the first major axis 320 and the second major axis may be aligned at an angle. The first semiconductor deposition layer 310 may include any one of N-type or P-type dopants to provide conductivity required for forming a three-dimensional gate structure, which will be described in detail below. In one embodiment, the first semiconductor deposition layer can be deposited with tungsten silicide WSi and cobalt silicide CoSi to form a silicide that can reduce the resistance of the first semiconductor deposition layer 310 . The insulating structure 312 can be a high temperature oxide layer 208 as described in the embodiments of FIGS. 2 and 3 .

In addition, the second semiconductor deposition layer 314 may be substantially similar to the semiconductor deposition layer 212 described in the embodiments of FIGS. 2 and 3 . The second semiconductor deposition layer 314 can be a polysilicon layer fabricated by a standard process, and can be modified by an implantation process to have a first conductivity type, and the first conductivity type can be N-type or P-type. In an exemplary embodiment shown in FIG. 6 , the second semiconductor deposition layer 314 can be formed on the first insulating structure 304 and the second insulating structure 312 by depositing polysilicon, and the N-type dopant can be formed when depositing the polysilicon. , implanted in the second semiconductor deposition layer 314 by in-situ doping. In another embodiment, the N-type dopant can be introduced by diffusion doping or in-situ doping by ion implantation. In yet another embodiment, the N-type dopant can be replaced by the P-type dopant, and introduced into the second semiconductor deposition layer 314 by the same process.

4 to 6, a first implantation region 316 can be formed in the second semiconductor deposition layer 314, and the first implantation region 316 has the same conductivity type as the second semiconductor deposition layer 314 and is higher than that of the second semiconductor deposition layer. 314 high doping concentration. The first implant region 316 can be labeled as source S. A second implantation region 318 can be formed in the second semiconductor deposition layer 314 . The second implantation region 318 has the same conductivity type as the second semiconductor deposition layer 314 and a higher doping concentration than the second semiconductor deposition layer 314 . The second implant region 318 can be labeled as drain D.

The JFET device 300 includes a metal contact layer formed on a contact region 326 of the second semiconductor deposition layer 314 , and the contact region 326 is located between the first implant region 316 and the second implant region 318 . Similar to the metal contact layer 218 , the metal contact layer 324 may include a suitable metal such that the junction between the metal contact layer 324 and the contact region 326 of the second semiconductor deposition layer 314 acts as a Schottky barrier. The metal contact layer 324 may surround the second semiconductor deposition layer 314 and not be in contact with the first semiconductor deposition layer. Depending on whether the second semiconductor deposition layer 314 includes N-type or P-type dopants, the Schottky barrier can be used as a P-type gate or an N-type gate, respectively. The metal contact layer 324 as described above may be designated as gate 324 .

After implanting N-type or P-type dopants, the conductivity of the second semiconductor deposition layer 314 allows charges to flow from the source 316 to the drain 318 . The conductivity of the second semiconductor deposition layer 314 can be controlled by both the gate 324 and the first semiconductor deposition layer 310 . When performed independently, the gate 324 can control the conductivity of the second semiconductor deposition layer 314 with a negative first gate-to-source voltage V _GS1 that _induces a first depletion region in or around the contact region 326 . The value of V _GS1 can be adjusted to depletion region to pinch off the path of charge flow to turn off JFET device 300 . However, the first semiconductor deposition layer 300 and the second insulating structure 312 can function as a second gate to form a second depletion region in the second semiconductor deposition layer 314 . The second depletion region can be formed by additionally applying a negative second gate-to-source voltage V _GS2 on the electrode (not shown) connected to the first semiconductor deposition layer 310 . In addition to the improvement caused by the first insulating structure 304, the first depletion region and the second depletion region can interact, not only to better control V _P , but also to improve pinch-off precision.

By improving the controllability and accuracy of the clamping voltage, the junction field effect transistor device disclosed in the present invention can achieve more and more various improvements on the integrated circuit (IC). For example, in recent years, considering the high conversion efficiency and low standby power consumption of the junction field effect transistor device disclosed by the present invention, it is especially suitable for the development of green technology. A switching power supply IC includes an integrated startup circuit and a pulse width modulation (PulseWidthMoldulation, PWM) circuit. FIG. 7 shows a traditional high voltage start-up circuit 400, and the resistor 410 continues to generate power consumption after start-up. The resistor 410 can be selected from a type that can provide a charging current (charging current (I _IC ) to the capacitor 420 and enable the pulse width modulation circuit to start operating. The PWM circuit 430 continues to operate until the voltage V _CC is lower than the minimum operating voltage, and then an auxiliary current I _aux is applied to the PWM circuit. The PWM circuit 430 generally operates between 10V-30V. To reduce power consumption, the resistor 410 of the start-up circuit can be replaced by HVdepletionMOS or HVJEFT elements. However, a HVdepletion NMOS has a large leakage current (>100μA) at the threshold voltage (<-4V). A HVJEFT requires a large drift region (driftregion) to form a reduced surface field (reduced surfacefield, RESURF), so the pinch feature of the HVJEFT lacks precision.

FIG. 8 illustrates an exemplary circuit 500 including a junction field effect transistor device 510 disclosed in the present invention. The JFET device 510 can be any JFET configuration according to the principles disclosed in the present invention. In addition to the JFET device 510 , the circuit 500 further includes a PWM circuit 520 , an HVdepletionMOS 530 , and a diode 540 . In operation, the source-to-gate voltage V _S during start-up is less than the pinch-off voltage V _P of the JFET device, and the JFET device exhibits low resistance. An exemplary pinch voltage V _P is about 15 volts. When the junction field effect transistor device exhibits low resistance, the HVdepletionMOS 530 with an exemplary threshold voltage (threshold voltage, V _th ) of -3V can provide the current required for the operation of the pulse width modulation circuit 520 and the charging of the capacitor 450 until the junction field The _VS of the effect transistor element 510 reaches the pinch voltage _Vp . When V _S is higher than the pinch voltage _VP , the resistance of the JFET device 510 increases substantially while the drain-to-source voltage remains the same as the pinch voltage _VP . When V _S is higher than the pinch-off voltage V _P -threshold voltage V _th , the MOS 530 will be turned off. For example, in an exemplary embodiment, the pinch voltage V _P is about 15V and the threshold voltage V _th is -3V. The graph of FIG. 9 shows that, in this embodiment, when V _S is about 15V higher than the pinch voltage VP , the current (I _D ) from MOS 530 starts to decrease due to the increased resistance of JFET device 510 _. When V _S reaches _18V , which is higher than the pinch voltage V _P - threshold voltage V _th , the current ID from the MOS 530 will stop. Please refer to FIG. 8 , after the PWM is started, I _aux can be used to charge the capacitor 550 . Therefore, the junction FET device 510 that can precisely control the pinch-off voltage VP can reduce the leakage current of the _{HVdepletionMOS} 530 and increase the efficiency.

Although the present invention has been disclosed above with the embodiments, it is not intended to limit the present invention. Those skilled in the art of the present invention can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed, and should include changes and modifications made within the spirit and scope of the present invention, and the protection scope of the present invention should be defined as defined by the appended claims. allow.

Claims (8)

1. a semiconductor element, comprising:

One substrate;

One first insulation system, is formed over the substrate;

One first semiconductor deposition, is formed on this first insulation system, and this first semiconductor deposition is an electrode;

One the 2nd insulation system, is formed in this first semiconductor deposition;

One the 2nd semiconductor deposition, is formed on the 2nd insulation system, and the 2nd semiconductor deposition has one first conductivity type;

One first injection region, is formed in the 2nd semiconductor deposition, and this first injection region has this first conductivity type and the doping content that relatively the 2nd semiconductor deposition is high;

One the 2nd injection region, is formed in the 2nd semiconductor deposition, and the 2nd injection region has this first conductivity type and the doping content that relatively the 2nd semiconductor deposition is high; And

One metal contact layer, it is formed on a zone of action of the 2nd semiconductor deposition, this zone of action is between this first injection region and the 2nd injection region, one junction is formed between this zone of action of this metal contact layer and the 2nd semiconductor deposition, and wherein this junction is a Schottky barrier (Schottkybarrier).

2. semiconductor element according to claim 1, wherein this first insulation system comprises a field oxide (fieldoxidelayer).

3. semiconductor element according to claim 2, wherein this first insulation system more comprises a grid oxic horizon, is arranged on this field oxide.

4. semiconductor element according to claim 1, more comprises one first trap district, is formed in this substrate, and wherein this first trap district is positioned at the lower section of this first insulation system, and this first trap district has this first conductivity type or one the 2nd conductivity type.

5. semiconductor element according to claim 1, wherein the 2nd semiconductor deposition comprises a polysilicon layer.

6. semiconductor element according to claim 1, wherein this first conductivity type is N-type, and this Schottky barrier can be used as a P-type grid electrode.

7. semiconductor element according to claim 1, wherein this first conductivity type is P type, and this Schottky barrier can be used as a N-type grid.

8. a manufacture method for semiconductor element, comprising:

A substrate is formed one first insulation system;

Forming one first semiconductor deposition on this first insulation system, this first semiconductor deposition is an electrode;

This first semiconductor deposition is formed one the 2nd insulation system;

Forming one the 2nd semiconductor deposition on the 2nd insulation system, the 2nd semiconductor deposition has one first conductivity type;

Forming one first injection region in the 2nd semiconductor deposition, this first injection region has this first conductivity type and doping content that relatively the 2nd semiconductor deposition is high;

Forming one the 2nd injection region in the 2nd semiconductor deposition, the 2nd injection region has this first conductivity type and doping content that relatively the 2nd semiconductor deposition is high;

A zone of action of the 2nd semiconductor deposition forms a metal contact layer, this zone of action is between this first injection region and the 2nd injection region, and then form a junction between this metal contact layer and this zone of action of the 2nd semiconductor deposition, wherein this junction is a Schottky barrier.