CN103415128B - Circuit for realizing controllable silicon dimming and high-power factor - Google Patents
Circuit for realizing controllable silicon dimming and high-power factor Download PDFInfo
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Abstract
The invention discloses a circuit for realizing controllable silicon dimming and a high-power factor. The circuit samples a primary voltage signal through a first sampling circuit and a second sampling circuit, thus implementing the fact that average output current and average output voltage of a load LED (light emitting diode) is non-related with a load, obtaining a higher input voltage adjustment rate and a higher load adjustment rate and realizing constant-current output control over the load LED; furthermore, the primary input current can track an alternating current input sine waveform and the average output current of the load LED can be changed along with the change of a controllable silicon triggering angle alpha after the circuit for realizing the controllable silicon dimming and the high-power factor is added into an existing flyback type LED driving circuit based on original boundary feedback; therefore the higher-power factor and the controllable silicon dimming are realized.
Description
Technical Field
The invention relates to a circuit for realizing silicon controlled rectifier dimming and high power factor, in particular to a circuit for realizing silicon controlled rectifier dimming and high power factor based on primary side feedback.
Background
Under the background of global energy shortage and continuously improved environmental protection requirements, green energy-saving illumination is vigorously developed in all countries in the world. LED lighting is rapidly developing as a revolutionary energy-saving lighting technology. However, the demand for LED driving power is also increasing. High efficiency, high power factor, safety isolation, compliance with EMI standards, high current control accuracy, high reliability, small size, low cost, etc. are becoming key ratings for LED driving power supplies. Furthermore, since LED lamps are required to directly replace incandescent lamps, the LED driving power supply must also be able to accommodate conventional thyristor dimmers for dimming.
As shown in fig. 1, an existing flyback LED driving circuit based on primary side feedback includes: an alternating current power supply; an LC filter; a primary absorption circuit; a transformer composed of a primary winding, a secondary winding and an auxiliary winding; a secondary circuit connected to the secondary winding; an auxiliary power supply circuit connected to the auxiliary winding; a power switch tube M1; a power switch tube current sampling resistor R4 and an LED drive control circuit.
The LED driving control circuit in fig. 1 (the control circuit is referred to as a critical conduction mode flyback constant current control module in the invention) includes: the circuit comprises a first comparator, a second comparator, a trigger, a grid drive circuit and a leading edge blanking circuit. When the LED drive control circuit works, the LED drive control circuit needs to extract information related to output voltage and primary peak current, and outputs a modulation signal through a GATE signal of a GATE port to control the on and off of a power switch tube M1 so as to keep the current of a load LED constant. In the system shown in fig. 1, the above-mentioned information about the output voltage and the primary peak current can be extracted by means of the signal CS at the CS port and the signal DEMAG at the DEMAG port. According to the relevant theory, it can be deduced that the average current of the load LED conforms to the following formula:
wherein,the average output current of the load LED is N is the turns ratio of the primary winding and the secondary winding of the transformer, IpkIn order to obtain the primary peak current,for the on-time of the power switch M1,the off time of the power switch M1.
The first comparator in fig. 1 implements the primary peak current I by comparing the sampled CS signal with a reference Vref3pkThe second comparator is implemented by comparing the sampled DEMAG signal with a reference Vref4 for a fixed valueIs a fixed value, such that the average output current for the load LEDIt is a fixed value which does not vary with the input voltage and the load, thereby realizing constant current driving. However, such a control method cannot achieve high power factor and thyristor dimming. Because the primary current waveform must track the ac input sinusoidal waveform if a high power factor is to be achieved; if input thyristor dimming is to be realized, the average output current of the load LED must be changed along with the change of the trigger angle of the thyristorAnd (4) changing.
In summary, in order to achieve high power factor and silicon controlled rectifier dimming, an additional control circuit needs to be added on the basis of the existing flyback LED driving circuit based on primary side feedback.
Disclosure of Invention
The invention aims to solve the technical problem of providing a circuit for realizing silicon controlled rectifier dimming and high power factor, and after the circuit is added, the existing flyback LED driving circuit based on primary side feedback can realize high power factor and silicon controlled rectifier dimming.
In order to solve the technical problems, the invention adopts the technical scheme that: a circuit for implementing thyristor dimming and high power factor, the circuit comprising: a first sampling circuit; a second sampling circuit; a first switch comprising a first gate, a first terminal, and a second terminal; a second switch comprising a second gate, a third terminal, and a fourth terminal; a third switch comprising a third gate, a fifth terminal, and a sixth terminal; a second transistor comprising a fourth gate, a seventh terminal, and an eighth terminal; a third transistor including a fifth gate, a ninth terminal, and a tenth terminal; a fourth transistor comprising a sixth gate, an eleventh terminal, and a twelfth terminal; a digital-to-analog converter; a counter; an inverter; a first operational amplifier; a second operational amplifier; a seventh resistor; a fifth capacitor; a first comparator; a first flip-flop; a delay circuit; a fifth resistor; a sixth resistor; an eighth resistor; a second comparator; wherein, the first sampling circuit samples and processes the voltage signal of the primary winding of the external flyback LED driving circuit and transmits the voltage signal to the positive input end of the second operational amplifier, the negative input end of the second operational amplifier is connected to the twelfth terminal, the output end of the second operational amplifier is connected to the sixth gate, the second sampling circuit samples and processes the voltage signal of the primary winding of the external flyback LED driving circuit and transmits the voltage signal to the positive input end of the first operational amplifier, the negative input end of the first operational amplifier is connected to the tenth terminal, the output end of the first operational amplifier is connected to the fifth gate, the ninth terminal is connected to the second terminal, the eleventh terminal is connected to the fourth terminal, the first terminal and the third terminal are connected to the eighth terminal after being combined, the seventh terminal receives an external power supply voltage, the fourth gate is connected to the eighth terminal and the digital-to-analog converter, the first gate is connected to the input end of the inverter, the third gate and the Q-bar end of an external second trigger, the second gate is connected to the output end of the inverter, the tenth terminal is connected to the positive input end of the second comparator, the tenth terminal and the twelfth terminal are grounded through the fifth resistor and the sixth resistor, the digital-to-analog converter is connected to the counter, the fifth terminal and one end of the seventh resistor, the other end of the seventh resistor is connected to one end of the eighth resistor and the negative input end of the external third comparator, the other end of the eighth resistor is grounded, and the sixth terminal is connected to one end of the fifth capacitor and the negative input end of the first comparator, the other end of the fifth capacitor is grounded, a positive input end of the first comparator is connected to a first reference voltage, a negative input end of the second comparator is connected to a second reference voltage, the first comparator outputs to the first flip-flop, an output end of the second comparator is respectively connected to a CLK end of the counter and one end of the delay circuit, a D end of the first flip-flop receives an external power supply voltage, a Qnegative end of the first flip-flop is connected to a UP/DN end of the counter, and a CLR end of the first flip-flop is connected to the other end of the delay circuit.
Preferably, in the circuit for implementing thyristor dimming and high power factor, the first sampling circuit includes: the circuit comprises a ninth resistor, a tenth resistor, an eleventh resistor, a fifth transistor, a sixth capacitor and a second inverter, wherein one end of the tenth resistor is connected to the drain electrode of the external first transistor, the other end of the tenth resistor is respectively connected to one end of the eleventh resistor and one end of the ninth resistor, the other end of the eleventh resistor is grounded, the other end of the ninth resistor is connected to one end of the fifth transistor, the other end of the fifth transistor is respectively connected to one end of the sixth capacitor and the positive input end of the second operational amplifier, the gate of the fifth transistor is connected to the output end of the second inverter, the input end of the second inverter is connected to the gate of the external first transistor, and the other end of the sixth capacitor is grounded; the second sampling circuit includes: one end of the twelfth resistor is connected to the output end of the external LC filter, the other end of the twelfth resistor is connected to the positive input end of the first operational amplifier and one end of the thirteenth resistor respectively, and the other end of the thirteenth resistor is grounded.
Preferably, in the circuit for implementing thyristor dimming and high power factor, the fifth transistor is an N-type field effect transistor.
Preferably, in the circuit for implementing thyristor dimming and high power factor, the first sampling circuit includes: the circuit comprises a ninth resistor, a tenth resistor, an eleventh resistor and a sixth capacitor, wherein one end of the tenth resistor is connected to the drain electrode of the external first transistor, the other end of the tenth resistor is respectively connected to one end of the eleventh resistor and one end of the ninth resistor, the other end of the eleventh resistor is grounded, the other end of the ninth resistor is respectively connected to one end of the sixth capacitor and the positive input end of the second operational amplifier, and the other end of the sixth capacitor is grounded; the second sampling circuit includes: one end of the twelfth resistor is connected to an output end of an external LC filter, the other end of the twelfth resistor is connected to one end of the fifth transistor, one end of the thirteenth resistor and one end of the fourteenth resistor respectively, the other end of the thirteenth resistor is grounded, the other end of the fifth transistor is grounded, a grid of the fifth transistor is connected to a grid of an external first transistor, the other end of the fourteenth resistor is connected to a positive input end of the first operational amplifier and one end of the seventh capacitor respectively, and the other end of the seventh capacitor is grounded.
Preferably, in the circuit for implementing thyristor dimming and high power factor, the first sampling circuit includes: one end of the tenth resistor is connected to the output end of the external LC filter, the other end of the tenth resistor is respectively connected to one end of the eleventh resistor and the positive input end of the second operational amplifier, and the other end of the eleventh resistor is grounded; the second sampling circuit includes: one end of the twelfth resistor is connected to an output end of an external LC filter, the other end of the twelfth resistor is connected to one end of the fifth transistor, one end of the thirteenth resistor and one end of the fourteenth resistor respectively, the other end of the thirteenth resistor is grounded, the other end of the fifth transistor is grounded, a grid of the fifth transistor is connected to a grid of an external first transistor, the other end of the fourteenth resistor is connected to a positive input end of the first operational amplifier and one end of the seventh capacitor respectively, and the other end of the seventh capacitor is grounded.
Preferably, in the circuit for implementing thyristor dimming and high power factor, the first sampling circuit includes: the circuit comprises a ninth resistor, a tenth resistor, an eleventh resistor, a fifth transistor, a sixth capacitor and a second inverter, wherein one end of the tenth resistor is connected to the drain electrode of the external first transistor, the other end of the tenth resistor is respectively connected to one end of the eleventh resistor and one end of the ninth resistor, the other end of the eleventh resistor is grounded, the other end of the ninth resistor is connected to one end of the fifth transistor, the other end of the fifth transistor is respectively connected to one end of the sixth capacitor and the positive input end of the second operational amplifier, the gate of the fifth transistor is connected to the output end of the second inverter, the input end of the second inverter is connected to the gate of the external first transistor, and the other end of the sixth capacitor is grounded; the second sampling circuit includes: the circuit comprises a twelfth resistor, a thirteenth resistor, a fourteenth resistor and a seventh capacitor, wherein one end of the twelfth resistor is connected to the drain electrode of the external first transistor, the other end of the twelfth resistor is respectively connected to one end of the thirteenth resistor and one end of the fourteenth resistor, the other end of the thirteenth resistor is grounded, the other end of the fourteenth resistor is respectively connected to the positive input end of the first operational amplifier and one end of the seventh capacitor, and the other end of the seventh capacitor is grounded.
Preferably, the circuit for implementing thyristor dimming and high power factor further comprises: a critical conduction mode flyback constant current control module, the module comprising: the circuit comprises a third comparator, a second trigger, a grid drive circuit, a fourth comparator and a leading edge blanking circuit; wherein the negative input terminal of the third comparator is connected to the junction of the seventh resistor and the eighth resistor, a positive input terminal of the third comparator is connected to one end of the leading edge blanking circuit, an output terminal of the third comparator is connected to the D terminal of the second flip-flop, the S end of the second trigger is connected to the output end of the fourth comparator, the Q end of the second trigger is connected to the input end of the grid drive, the Q non end of the second trigger is connected to the first grid, the negative input end of the fourth comparator is used for sampling a voltage division signal of an external auxiliary winding, the positive input end of the fourth comparator receives a fourth reference voltage, the output end of the gate drive is connected to the gate of the external first transistor, and the other end of the leading edge blanking circuit is connected to the source of the external first transistor.
Preferably, the circuit for implementing thyristor dimming and high power factor further comprises: a rectifier bridge; an LC filter; a primary absorption circuit; a transformer composed of a primary winding, a secondary winding and an auxiliary winding; a secondary circuit connected to the secondary winding; an auxiliary power supply circuit connected to the auxiliary winding; a first transistor; a fourth resistor; the rectifier bridge, the LC filter, the primary absorption circuit and the transformer are sequentially connected in series, the drain electrode of the first transistor is connected to the primary winding, and the source electrode of the first transistor is grounded through a fourth resistor.
Preferably, the circuit for implementing thyristor dimming and high power factor further comprises: and the silicon controlled dimmer is connected to the front end of the rectifier bridge.
Preferably, the circuit for implementing thyristor dimming and high power factor further comprises: and the alternating current power supply is connected to the front end of the silicon controlled rectifier dimmer.
The invention has the advantages that the primary voltage signal is sampled by the first sampling circuit and the second sampling circuit, so that the average output current of the load LED is independent of the output voltage and the load, thereby obtaining better input voltage regulation rate and load regulation rate and realizing the constant current output control of the load LED; meanwhile, after the circuit for realizing silicon controlled rectifier dimming and high power factor is added into the existing flyback LED drive circuit based on primary side feedback, the primary input current can track the AC input sine waveform and the average output current of the load LED can follow the trigger angle of the silicon controlled rectifierThereby realizing higher power factor and silicon controlled rectifier dimming.
Drawings
Fig. 1 is a prior art flyback LED driving circuit based on primary side feedback;
fig. 2 is a circuit diagram of a flyback LED driving circuit based on primary-side feedback according to a first embodiment of the present invention;
fig. 3 is a circuit diagram of a primary feedback based flyback LED drive circuit incorporating a first alternative embodiment of the present invention;
fig. 4 is a circuit diagram of a flyback LED drive circuit based on primary-side feedback that includes a second alternative embodiment of the present invention;
fig. 5 is a circuit diagram of a flyback LED drive circuit based on primary-side feedback that includes a third alternative embodiment of the present invention;
fig. 6 is a circuit diagram of a flyback LED drive circuit based on primary-side feedback that includes a fourth alternative embodiment of the present invention.
Detailed Description
To further disclose the technical solution of the present invention, the following detailed description is made with reference to the accompanying drawings:
the basic concept of the invention is as follows: fig. 2 is a circuit diagram of a flyback LED driving circuit based on primary-side feedback according to a first embodiment of the present invention, which includes: an AC power source 116; a thyristor dimmer 117; a rectifier bridge; an LC filter; a primary absorption circuit; a transformer composed of a primary winding, a secondary winding and an auxiliary winding; a secondary circuit connected to the secondary winding; an auxiliary power supply circuit connected to the auxiliary winding; the power switch transistor M1 is the first transistor M1; the power switch tube M1 current sampling resistor R4 and the LED drive control circuit, the grid of the power switch tube M1 is connected with the GATE port of the LED drive control circuit, the drain electrode of the power switch tube M1 is connected with the primary winding, and the source electrode of the power switch tube M1 is grounded through the power switch tube M1 current sampling resistor R4. The LED driving control circuit comprises a peak current reference generator module and a critical conduction mode flyback constant current control module, wherein the peak current reference generator module is the circuit for realizing silicon controlled rectifier dimming and high power factor, the input ends VC1 and VC2 of the peak current reference generator module are used for sampling primary voltage signals, and the output end Vref3 of the circuit is provided for a peak current reference required by the critical conduction mode flyback constant current control module. The critical conduction mode flyback constant current control module is characterized in that an input end DEMAG of an existing LED drive control circuit is used for sampling a voltage division signal of the auxiliary winding, an input end CS of the critical conduction mode flyback constant current control module is used for sampling a voltage signal on a current sampling resistor R4 of a power switch tube M1, and an output end GATE of the critical conduction mode flyback constant current control module is used for driving the power switch tube M1.
First embodiment specifically, as shown in fig. 2, the peak current reference generator module, i.e., the circuit for implementing thyristor dimming and high power factor of the present invention, includes: a circuit for implementing thyristor dimming and high power factor, the circuit comprising: a first sampling circuit 101; a second sampling circuit 118; a first switch SW1, the first switch SW1 including a first gate, a first terminal and a second terminal; a second switch SW2, the second switch SW2 including a second gate, a third terminal and a fourth terminal; a third switch SW3, the third switch SW3 including a third gate, a fifth terminal, and a sixth terminal; a second transistor M2, the second transistor M2 including a fourth gate, a seventh terminal, and an eighth terminal; a third transistor M3, the third transistor M3 including a fifth gate, a ninth terminal, and a tenth terminal; a fourth transistor M4, the fourth transistor M4 including a sixth gate, an eleventh terminal, and a twelfth terminal; a digital-to-analog converter 103; a counter 104; an inverter 102; a first operational amplifier 105; a second operational amplifier 106; a seventh resistor R7; a fifth capacitance C5; a first comparator 107; a first flip-flop 110; a delay circuit 109; a fifth resistor R5; a sixth resistor R6; an eighth resistor R8; a second comparator 108; wherein, the first sampling circuit 101 samples and processes the voltage signal of the primary winding of the external flyback LED driving circuit, and transmits the voltage signal to the positive input terminal of the second operational amplifier 106, the negative input terminal of the second operational amplifier 106 is connected to the twelfth terminal, the output terminal of the second operational amplifier 106 is connected to the sixth gate, the second sampling circuit 118 samples and processes the voltage signal of the primary winding of the external flyback LED driving circuit, and transmits the voltage signal to the positive input terminal of the first operational amplifier 105, the negative input terminal of the first operational amplifier 105 is connected to the tenth terminal, the output terminal of the first operational amplifier 105 is connected to the fifth gate, the ninth terminal is connected to the second terminal, the eleventh terminal is connected to the fourth terminal, the first terminal and the third terminal are connected to the eighth terminal after being combined, the seventh terminal receives an external supply voltage, the fourth gate is respectively connected to the eighth terminal and the digital-to-analog converter 103, the first gate is respectively connected to the input terminal of the inverter 102, the third gate and the Q-not terminal of the external second flip-flop 112, the second gate is connected to the output terminal of the inverter 102, the tenth terminal is connected to the positive input terminal of the second comparator 108, the tenth terminal and the twelfth terminal are respectively grounded through the fifth resistor R5 and the sixth resistor R6, the digital-to-analog converter 103 is respectively connected to the counter 104, the fifth terminal and one end of the seventh resistor R7, the other end of the seventh resistor R7 is respectively connected to one end of an eighth resistor R8 and the negative input terminal of the external third comparator 111, the other end of the eighth resistor R8 is grounded, that is, a connection point of the seventh resistor R7 and the eighth resistor R8 outputs a third reference voltage 3 to the negative input terminal of the external third comparator 111, the sixth terminal is respectively connected to one end of the fifth capacitor C5 and the negative input end of the first comparator 107, the other end of the fifth capacitor C5 is grounded, the positive input end of the first comparator 107 is connected to a first reference voltage Vref1, the negative input end of the second comparator 108 is connected to a second reference voltage Vref2, the first comparator 107 outputs to the first flip-flop 110, the output end of the second comparator 108 is respectively connected to the CLK end of the counter 104 and one end of the delay circuit 109, the D end of the first flip-flop 110 receives an external power supply voltage, the Q-bar end of the first flip-flop 110 is connected to the UP/DN end of the counter 104, and the CLR end of the first flip-flop 110 is connected to the other end of the delay circuit 109.
In addition, the critical conduction mode flyback constant current control module includes: a third comparator 111, a second flip-flop 112, a gate driver 113, a fourth comparator 114, and a leading edge blanking circuit 115; wherein a negative input terminal of the third comparator 111 is connected to a junction point of the seventh resistor R7 and the eighth resistor R8, i.e., a negative input terminal of the third comparator 111 is connected to the output terminal of the peak current reference generator module to receive a third reference voltage Vref3, a positive input terminal of the third comparator 111 is connected to one terminal of the leading edge blanking circuit 115, an output terminal of the third comparator 111 is connected to a D terminal of the second flip-flop 112, an S terminal of the second flip-flop 112 is connected to an output terminal of the fourth comparator 114, a Q terminal of the second flip-flop 112 is connected to an input terminal of the gate driver 113, a Q terminal of the second flip-flop 112 is connected to the first gate, a negative input terminal of the fourth comparator 114 is used for sampling a voltage division signal of an external auxiliary winding, and a positive input terminal of the fourth comparator 114 receives a fourth reference voltage Vref4, the output terminal of the gate driver 113 is connected to the gate of the external first transistor M1, and the other terminal of the leading edge blanking circuit 115 is connected to the source of the external first transistor M1.
First alternative embodiment fig. 3 is a circuit diagram of a primary feedback-based flyback LED driving circuit including a first alternative embodiment of the present invention, and the diagram is merely an example of the first sampling circuit 101 and the second sampling circuit 118 in the circuit for implementing thyristor dimming and high power factor, and does not limit the scope of the claims. In fig. 3, the first sampling circuit 101 includes: a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a fifth transistor M5, a sixth capacitor C6 and a second inverter, wherein one end of the tenth resistor R10 is connected to the drain of the external first transistor M1, the other end of the tenth resistor R10 is respectively connected to one end of the eleventh resistor R11 and one end of a ninth resistor R9, the other end of the eleventh resistor R11 is grounded, the other end of the ninth resistor R9 is connected to one end of the fifth transistor M5, the other end of the fifth transistor M5 is respectively connected to one end of the sixth capacitor C6 and the positive input end of the second operational amplifier 106, the gate of the fifth transistor M5 is connected to the output end of the second inverter, the input end of the second inverter is connected to the gate of the external first transistor M1, and the other end of the sixth capacitor C6 is grounded; the second sampling circuit 118 includes: a twelfth resistor R12 and a thirteenth resistor R13, wherein one end of the twelfth resistor R12 is connected to the output end of the external LC filter, the other end of the twelfth resistor R12 is connected to the positive input end of the first operational amplifier 105 and one end of the thirteenth resistor R13, and the other end of the thirteenth resistor R13 is grounded.
As shown in fig. 3, the operation process of the circuit for implementing thyristor dimming and high power factor of the present invention is as follows: and sampling the primary voltages VC2 and VC1, and then performing division operation to obtain a reference voltage Vref3 required by the system. In fig. 3: the sampling circuit of VC2 is composed of a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a fifth transistor M5, i.e. an N-type fet M5, a sixth capacitor C6 and a second inverter, and the sampling circuit functions as envelope detection, the sampled signal is a voltage signal (denoted as Vdrain) at the drain of the primary power switch M1, and the output result is:wherein, k is a constant in the present text,for the input of the voltage to the primary winding,is an alternating current phase, N is the turns ratio of the primary winding and the secondary winding of the transformer,is the output voltage across the secondary LED. A VC1 sampling circuit composed of a twelfth resistor R12 and a thirteenth resistor R13, which is used for voltage division detection, wherein the sampled signal is a primary input voltage signal (denoted as V)in) The output result is:. The first operational amplifier 105, the third transistor M3, and the fifth transistor M3The resistor R5 is used for converting the voltage signal output by the voltage division detection circuit into a current signal I3The circuit formed by the second operational amplifier 106, the fourth transistor M4 and the sixth resistor R6 is used for converting the voltage signal output by the envelope detection circuit into the current signal I4. It can be seen that when the first switch SW1 and the third switch SW3 are conductive, the second switch SW2 is closed and vice versa. First, when the first switch SW1 and the third switch SW3 are turned on and the second switch SW2 is turned off, the second transistor M2, i.e., the PFET M2, conducts the current I3Copied to the digital-to-analog converter 103, the output current of the digital-to-analog converter 103 is:。
wherein,is the gain of the digital-to-analog converter 103, the value of which varies from 0 to 255/256 under the control of the counter 104.
Current flows through the seventh resistor R7 and the eighth resistor R8 to form a voltage (denoted as）：Since the third switch SW3 is also turned on at this time,is sampled and held on the fifth capacitor C5 ifThen:
。
the clock signal CLK is generated by comparing the second comparator 108 with the reference voltage Vref2, and the output of the counter 104 is updated at each falling edge of the CLK clock signal through the UP/DN portWhen the voltage is higher than Vref1, the first comparator 107 outputs to the first flip-flop 110, and the first flip-flop 110 outputs to the UP/DN port of the counter 104 to increase the count of the counter 104, and conversely, the count of the counter 104 decreases. The counter 104 output controls the digital to analog converter 103. When the digital-to-analog converter 103 is connected,When the negative feedback loop of the first comparator 107, the first flip-flop 110 and the counter 104 reaches an equilibrium,。
when the first switch SW1 and the third switch SW3 are turned off, the second switch SW2 is turned on, and the second transistor M2, i.e., the PFET M2, conducts the current I4Copied to the digital-to-analog converter 103, the output current of the digital-to-analog converter 103 is:，
here, in this text，。
As shown in fig. 3, the peak current of the primary power switch M1 is sampled by the fourth resistor R4 to form a feedback voltage, which enters through the CS port, and after passing through the leading edge blanking circuit 115, the feedback voltage is compared with the reference voltage Vref3, when the voltage is higher than Vref3, the third comparator 111 outputs a high signal to the D port of the second flip-flop 112, the second flip-flop 112 outputs a low signal to the gate driver 113, and the gate driver 113 outputs a low signal to turn off the primary power switch M1. When the output voltage sampled by the auxiliary winding is divided by the second resistor R2 and the third resistor R3 and then input to the DEMAG port, the voltage is compared with the reference voltage Vref4 by the fourth comparator 114, when the voltage is higher than the reference voltage Vref4, the fourth comparator 114 outputs a high signal to the D port of the second flip-flop 112, the second flip-flop 112 outputs a high signal to the gate driver 113, the gate driver 113 outputs a high signal to turn on the primary power switch M1, and then the cycle starts again and again every cycle. The resulting load LED average output current can be expressed as:
。
second alternative embodiment fig. 4 is a circuit diagram of a flyback LED driving circuit based on primary feedback, which includes a second alternative embodiment of the present invention, and the diagram is merely an example of the first sampling circuit 101 and the second sampling circuit 118 in the circuit for implementing thyristor dimming and high power factor, and it does not limit the scope of the claims. In fig. 4, the first sampling circuit 101 includes: a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11 and a sixth capacitor C6, wherein one end of the tenth resistor R10 is connected to the drain of the external first transistor M1, the other end of the tenth resistor R10 is connected to one end of the eleventh resistor R11 and one end of the ninth resistor R9 respectively, the other end of the eleventh resistor R11 is grounded, the other end of the ninth resistor R9 is connected to one end of the sixth capacitor C6 and the positive input end of the second operational amplifier 106 respectively, and the other end of the sixth capacitor C6 is grounded; the second sampling circuit 118 includes: a twelfth resistor R12, a thirteenth resistor R13, a fourteenth resistor R14, a fifth transistor M5 and a seventh capacitor C7, wherein one end of the twelfth resistor R12 is connected to the output end of the external LC filter, the other end of the twelfth resistor R12 is connected to one end of the fifth transistor M5, one end of the thirteenth resistor R13 and one end of the fourteenth resistor R14, the other end of the thirteenth resistor R13 is grounded, the other end of the fifth transistor M5 is grounded, the gate of the fifth transistor M5 is connected to the gate of the external first transistor M1, the other end of the fourteenth resistor R14 is connected to the positive input end of the first operational amplifier 105 and one end of the seventh capacitor C7, and the other end of the seventh capacitor C7 is grounded.
As shown in fig. 4, the operation process of the circuit for implementing thyristor dimming and high power factor of the present invention is as follows: the primary voltages VC2 and VC1 are sampled and then divided to obtain the reference voltage Vref3 required by the system. In fig. 4: a sampling circuit of VC2 is composed of a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, and a sixth capacitor C6, the sampling circuit functions as low-pass filtering, the sampled signal is a voltage signal (denoted as Vdrain) at the drain of the primary power switch tube M1, and the output result is:wherein, k is a constant in the present text,the input voltage of the primary winding, N is the turn ratio of the primary winding and the secondary winding of the transformer,d is the output voltage across the secondary LED, and d is a section of the integrated output voltage. The VC1 sampling circuit is composed of a twelfth resistor R12, a thirteenth resistor R13, a fourteenth resistor R14, a seventh capacitor C7 and a fifth transistor M5, namely an N-type field effect transistor M5, and plays a role of chopping, and the sampled signal is a primary input voltage signal (denoted as Vin) The output result is:. The circuit formed by the first operational amplifier 105, the third transistor M3 and the fifth resistor R5 is used for converting the voltage signal output by the chopper circuit into a current signal I3The second operational amplifier 106, the fourth transistor M4 and the sixth resistor R6 are used to convert the voltage signal outputted from the low pass filter circuit into the current signal I4. It can be seen that when the first switch SW1 and the third switch SW3 are conductive, the second switch SW2 is closed and vice versa. First, when the first switch SW1 and the third switch SW3 are turned on and the second switch SW2 is turned off, the second transistor M2, i.e., the PFET M2, conducts the current I3Copied to the digital-to-analog converter 103, the output current of the digital-to-analog converter 103 is:。
whereinWhich is the gain of the digital-to-analog converter, the value of which varies from 0 to 255/256 under the control of the counter 104.
Current flows through the seventh resistor R7 and the eighth resistor R8 to form a voltage (denoted as V)DAC）：Since the third switch SW3 is also turned on at this time,is sampled and held on the fifth capacitor C5 ifThen:
。
the clock signal CLK is generated by comparing the second comparator 108 with the reference voltage Vref2, and the output of the counter 104 is updated at each falling edge of the CLK clock signal through the UP/DN portWhen the voltage is higher than Vref1, the first comparator 107 outputs to the first flip-flop 110, and the first flip-flop 110 outputs to the UP/DN port of the counter 104 to increase the count of the counter 104, and conversely, the count of the counter 104 decreases. The counter 104 outputs to the control digital-to-analog converter 103. When the digital-to-analog converter 103 is connected,When the negative feedback loop of the first comparator 107, the first flip-flop 110 and the counter 104 reaches an equilibrium,。
when the first switch SW1 and the third switch SW3 are turned off, the second switch SW2 is turned on, and the second transistor M2, i.e., the PFET M2, conducts the current I4Copied to the digital-to-analog converter 103, the output current of the digital-to-analog converter 103 is:，
here, ,，。
as shown in fig. 4, the peak current of the primary power switch M1 is sampled by the fourth resistor R4 to form a feedback voltage, which enters through the CS port, and after passing through the leading edge blanking circuit 115, the feedback voltage is compared with the reference voltage Vref3, when the voltage is higher than the reference voltage Vref3, the third comparator 111 outputs a high signal to the D port of the second flip-flop 112, the second flip-flop 112 outputs a low signal to the gate driver 113, and the gate driver 113 outputs a low signal to turn off the primary power switch M1. When the output voltage sampled by the auxiliary winding is divided by the second resistor R2 and the third resistor R3 and then input to the DEMAG port, the voltage is compared with the reference voltage Vref4 by the fourth comparator 114, when the voltage is higher than the reference voltage Vref4, the fourth comparator 114 outputs a high signal to the D port of the second flip-flop 112, the second flip-flop 112 outputs a high signal to the gate driver 113, the gate driver 113 outputs a high signal to turn on the primary power switch M1, and then the cycle starts again and again every cycle. The resulting load LED average output current can be expressed as:
。
third alternative embodiment fig. 5 is a circuit diagram of a flyback LED driving circuit based on primary feedback, which includes a third alternative embodiment of the present invention, and the diagram is merely an example of the first sampling circuit 101 and the second sampling circuit 118 in the circuit for implementing thyristor dimming and high power factor, and it does not limit the scope of the claims. In fig. 5, the first sampling circuit 101 includes: a tenth resistor R10 and an eleventh resistor R11, wherein one end of the tenth resistor R10 is connected to the output end of the external LC filter, the other end of the tenth resistor R10 is connected to one end of the eleventh resistor R11 and the positive input end of the second operational amplifier 106, and the other end of the eleventh resistor R11 is grounded; the second sampling circuit 118 includes: a twelfth resistor R12, a thirteenth resistor R13, a fourteenth resistor R14, a fifth transistor M5 and a seventh capacitor C7, wherein one end of the twelfth resistor R12 is connected to the output end of the external LC filter, the other end of the twelfth resistor R12 is connected to one end of the fifth transistor M5, one end of the thirteenth resistor R13 and one end of the fourteenth resistor R14, the other end of the thirteenth resistor R13 is grounded, the other end of the fifth transistor M5 is grounded, the gate of the fifth transistor M5 is connected to the gate of the external first transistor M1, the other end of the fourteenth resistor R14 is connected to the positive input end of the first operational amplifier 105 and one end of the seventh capacitor C7, and the other end of the seventh capacitor C7 is grounded.
As shown in fig. 5, the operation process of the circuit for implementing thyristor dimming and high power factor of the present invention is as follows: the primary voltages VC2 and VC1 are sampled and then divided to obtain the reference voltage Vref3 required by the system. In fig. 5: the sampling circuit of VC2 is composed of the ninth resistor R9 and the tenth resistor R10, the circuit is used for voltage division detection, the sampled signal is a primary input voltage signal (recorded as: Vin), and the output result is:wherein k is a constant, and wherein,a voltage is input to the primary winding. The VC1 sampling circuit is composed of a twelfth resistor R12, a thirteenth resistor R13, a fourteenth resistor R14, a seventh capacitor C7 and a fifth transistor M5, namely an N-type field effect transistor M5, and plays a role of chopping, and the sampled signal is a primary input voltage signal (denoted as Vin) The output result is:. The circuit formed by the first operational amplifier 105, the third transistor M3 and the fifth resistor R5 is used for converting the voltage signal output by the chopper circuit into a current signal I3The circuit function of the second operational amplifier 106, the fourth transistor M4 and the sixth resistor R6Converting the voltage signal output by the voltage division detection circuit into a current signal I4. It can be seen that when the first switch SW1 and the third switch SW3 are conductive, the second switch SW2 is closed and vice versa. First, when the first switch SW1 and the third switch SW3 are turned on and the second switch SW2 is turned off, the second transistor M2, i.e., the PFET M2, conducts the current I3Copied to the digital-to-analog converter 103, the output current of the digital-to-analog converter 103 is:
whereinWhich is the gain of the digital-to-analog converter, the value of which varies from 0 to 255/256 under the control of the counter 104.
Current flows through the seventh resistor R7 and the eighth resistor R8 to form a voltage (denoted as V)DAC）：Since the third switch SW3 is also turned on at this time,is sampled and held on the fifth capacitor C5 ifThen:
。
the clock signal CLK is generated by the comparison of the second comparator 108 with the reference voltage Vref2,the output of counter 104 is updated on each falling edge of the CLK clock signal through the UP/DN port when the rising edge of the CLK clock signal reaches the end of the clock cycleWhen the voltage is higher than Vref1, the first comparator 107 outputs to the first flip-flop 110, and the first flip-flop 110 outputs to the UP/DN port of the counter 104 to increase the count of the counter 104, and conversely, the count of the counter 104 decreases. The counter 104 outputs to the control digital-to-analog converter 103. When the digital-to-analog converter 103 is connected,When the negative feedback loop of the first comparator 107, the first flip-flop 110 and the counter 104 reaches an equilibrium,。
when the first switch SW1 and the third switch SW3 are turned off, the second switch SW2 is turned on, and the second transistor M2, i.e., the PFET M2, conducts the current I4Copied to the digital-to-analog converter 103, the output current of the digital-to-analog converter 103 is:。
here, ,，。
as shown in fig. 5, the peak current of the primary power switch M1 is sampled by the fourth resistor R4 to form a feedback voltage, which enters through the CS port, and after passing through the leading edge blanking circuit 115, the feedback voltage is compared with the reference voltage Vref3, when the voltage is higher than the reference voltage Vref3, the third comparator 111 outputs a high signal to the D port of the second flip-flop 112, the second flip-flop 112 outputs a low signal to the gate driver 113, and the gate driver 113 outputs a low signal to turn off the primary power switch M1. When the output voltage sampled by the auxiliary winding is divided by the second resistor R2 and the third resistor R3 and then input to the DEMAG port, the voltage is compared with the reference voltage Vref4 by the fourth comparator 114, when the voltage is higher than the reference voltage Vref4, the fourth comparator 114 outputs a high signal to the D port of the second flip-flop 112, the second flip-flop 112 outputs a high signal to the gate driver 113, the gate driver 113 outputs a high signal to turn on the primary power switch M1, and then the cycle starts again and again every cycle. The resulting load LED average output current can be expressed as:
。
fourth alternative embodiment fig. 6 is a circuit diagram of a flyback LED driving circuit based on primary feedback according to a fourth alternative embodiment of the present invention, which is merely an example of the first sampling circuit 101 and the second sampling circuit 118 in the circuit for implementing thyristor dimming and high power factor according to the present invention, and does not limit the scope of the claims. In fig. 6, the first sampling circuit 101 includes: a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a fifth transistor M5, a sixth capacitor C6 and a second inverter, wherein one end of the tenth resistor R10 is connected to the drain of the external first transistor M1, the other end of the tenth resistor R10 is respectively connected to one end of the eleventh resistor R11 and one end of a ninth resistor R9, the other end of the eleventh resistor R11 is grounded, the other end of the ninth resistor R9 is connected to one end of the fifth transistor M5, the other end of the fifth transistor M5 is respectively connected to one end of the sixth capacitor C6 and the positive input end of the second operational amplifier 106, the gate of the fifth transistor M5 is connected to the output end of the second inverter, the input end of the second inverter is connected to the gate of the external first transistor M1, and the other end of the sixth capacitor C6 is grounded; the second sampling circuit 118 includes: a twelfth resistor R12, a thirteenth resistor R13, a fourteenth resistor R14 and a seventh capacitor C7, wherein one end of the twelfth resistor R12 is connected to the drain of the external first transistor M1, the other end of the twelfth resistor R12 is connected to one end of the thirteenth resistor R13 and one end of the fourteenth resistor R14, the other end of the thirteenth resistor R13 is grounded, the other end of the fourteenth resistor R14 is connected to the positive input end of the first operational amplifier 105 and one end of the seventh capacitor C7, and the other end of the seventh capacitor C7 is grounded.
As shown in fig. 6, the operation process of the circuit for implementing thyristor dimming and high power factor of the present invention is as follows: the primary voltages VC2 and VC1 are sampled and then divided to obtain the reference voltage Vref3 required by the system. In fig. 6: the primary voltages VC2 and VC1 are sampled and then divided to obtain the reference voltage Vref3 required by the system. In fig. 6: the sampling circuit of the VC2 is composed of a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a fifth transistor M5, a sixth capacitor C6 and a second inverter, and the circuit plays a role of envelope detection, the sampled signal is a voltage signal (denoted as Vdrain) at the drain of the primary power switch tube M1, and the output result is:wherein k is a constant, and wherein,the input voltage of the primary winding, N is the turn ratio of the primary winding and the secondary winding of the transformer,is the output voltage across the secondary LED. The VC1 sampling circuit, which is composed of the twelfth resistor R12, the thirteenth resistor R13, the fourteenth resistor R14 and the seventh capacitor C7, functions as a low-pass filter, the sampled signal is a voltage signal (denoted as Vdrain) at the drain of the primary power switch tube M1, and the output result is:wherein k is a constant, and wherein,the input voltage of the primary winding, N is the turn ratio of the primary winding and the secondary winding of the transformer,is the output voltage across the secondary LED. The first operational amplifier 105, the third transistor M3 and the fifth resistor R5 are used to convert the voltage signal output from the low pass filter circuit into the current signal I3The circuit formed by the second operational amplifier 106, the fourth transistor M4 and the sixth resistor R6 is used for converting the voltage signal output by the envelope detection circuit into the current signal I4. It can be seen that when the first switch SW1 and the third switch SW3 are conductive, the second switch SW2 is closed and vice versa. First, when the first switch SW1 and the third switch SW3 are turned on and the second switch SW2 is turned off, the second transistor M2, i.e., the PFET M2, conducts the current I3Copied to the digital-to-analog converter 103, the output current of the digital-to-analog converter 103 is:
whereinWhich is the gain of the digital-to-analog converter, the value of which varies from 0 to 255/256 under the control of the counter 104.
Current flows through the seventh resistor R7 and the eighth resistor R8 to form a voltage (denoted as V)DAC）：Since the third switch SW3 is also turned on at this time,is sampled and held on the fifth capacitor C5 ifThen:
。
the clock signal CLK is generated by comparing the second comparator 108 with the reference voltage Vref2, and the output of the counter 104 is updated at each falling edge of the CLK clock signal through the UP/DN portWhen the voltage is higher than Vref1, the first comparator 107 outputs to the first flip-flop 110, and the first flip-flop 110 outputs to the UP/DN port of the counter 104 to increase the count of the counter 104, and conversely, the count of the counter 104 decreases. The counter 104 outputs to the control digital-to-analog converter 103. When the digital-to-analog converter 103 is connected,When the negative feedback loop of the first comparator 107, the first flip-flop 110 and the counter 104 reaches an equilibrium,。
when the first switch SW1 and the third switch SW3 are turned off, the second switch SW2 is turned on, and the second transistor M2, i.e., the PFET M2, conducts the current I4Copied to the digital-to-analog converter 103, the output current of the digital-to-analog converter 103 is:。
here, ,，。
as shown in fig. 6, the peak current of the primary power switch M1 is sampled by the fourth resistor R4 to form a feedback voltage, which enters through the CS port, and after passing through the leading edge blanking circuit 115, the feedback voltage is compared with the reference voltage Vref3, when the voltage is higher than the reference voltage Vref3, the third comparator 111 outputs a high signal to the D port of the second flip-flop 112, the second flip-flop 112 outputs a low signal to the gate driver 113, and the gate driver 113 outputs a low signal to turn off the primary power switch M1. When the output voltage sampled by the auxiliary winding is divided by the second resistor R2 and the third resistor R3 and then input to the DEMAG port, the voltage is compared with the reference voltage Vref4 by the fourth comparator 114, when the voltage is higher than the reference voltage Vref4, the fourth comparator 114 outputs a high signal to the D port of the second flip-flop 112, the second flip-flop 112 outputs a high signal to the gate driver 113, the gate driver 113 outputs a high signal to turn on the primary power switch M1, and then the cycle starts again and again every cycle. The resulting load LED average output current can be expressed as:
。
based on the above analysis, compared with the existing flyback LED driving circuit based on primary side feedback, after the peak current reference generator module is added, that is, the circuit of the present invention for realizing silicon controlled rectifier dimming and high power factor is used, as shown in fig. 2, the output of the rectifier bridge does not need a capacitor with a large capacitance value for filtering, and the output Vin of the rectifier bridge tracks the ac input sine waveform, which can be expressed as:
(1)
thus, the load LED average output current can be expressed as:
（2）
wherein,the average output current of the load LED is N is the turns ratio of the primary winding and the secondary winding of the transformer, IpkIs the primary peak current.
The function of the peak current reference generator module in fig. 2 is to sample VC1 and VC2 signals and perform division operation, and the divided Vref3 signal is compared with the sampled voltage signal of the switching tube current sampling resistor R4, so as to obtain:
（3）
k is constant, which yields:
（4）
from the above, it can be found that: the average output current of the load LED is irrelevant to the output voltage and the load, so that a better input voltage regulation rate and a better load regulation rate can be obtained, and the constant current control of the output LED is realized.
From equation (3), the primary sample current can be expressed as:
（5）
if VC2 samples the rectified output signal Vin, it can be obtained by substituting equation (1) into equation (5):
(6)
wherein,being constant, the primary input current can track the ac input sinusoidal waveform found by equation (6), which can achieve a high power factor.
Assuming that the thyristor dimmer is capable of controlling the current fromToAdjusting its firing angle, equation (4) can be derived:
(7)
it can be seen from equation (7) that the average output current of the load LED must follow the trigger angle of the thyristorSo that input thyristor dimming can be realized.
In summary, after the flyback LED driving circuit based on the primary feedback is added with the circuit for realizing the thyristor dimming and the high power factor, the flyback LED driving circuit can display the high power factor and the thyristor dimming while satisfying the better input voltage regulation characteristic and the load regulation characteristic.
The basic idea and the basic principle of the invention have been explained above by way of an introduction to the embodiments listed. The present invention is not limited to the above-mentioned embodiments, and all equivalent changes, modifications and deliberate deterioration actions based on the technical solution of the present invention should fall within the protection scope of the present invention.
Claims (10)
1. A circuit for implementing thyristor dimming and high power factor, the circuit comprising: a first sampling circuit (101); a second sampling circuit (118); a first switch (SW 1), the first switch (SW 1) including a first gate, a first terminal, and a second terminal; a second switch (SW 2), the second switch (SW 2) including a second gate, a third terminal, and a fourth terminal; a third switch (SW 3), the third switch (SW 3) including a third gate, a fifth terminal, and a sixth terminal; a second transistor (M2), the second transistor (M2) including a fourth gate, a seventh terminal, and an eighth terminal; a third transistor (M3), the third transistor (M3) including a fifth gate, a ninth terminal, and a tenth terminal; a fourth transistor (M4), the fourth transistor (M4) including a sixth gate, an eleventh terminal, and a twelfth terminal; a digital-to-analog converter (103); a counter (104); an inverter (102); a first operational amplifier (105); a second operational amplifier (106); a seventh resistor (R7); a fifth capacitance (C5); a first comparator (107); a first flip-flop (110); a delay circuit (109); a fifth resistor (R5); a sixth resistor (R6); an eighth resistor (R8); a second comparator (108); wherein, the first sampling circuit (101) samples and processes the voltage signal of the primary winding of the external flyback LED driving circuit and transmits the voltage signal to the positive input terminal of the second operational amplifier (106), the negative input terminal of the second operational amplifier (106) is connected to the twelfth terminal, the output terminal of the second operational amplifier (106) is connected to the sixth gate, the second sampling circuit (118) samples and processes the voltage signal of the primary winding of the external flyback LED driving circuit and transmits the voltage signal to the positive input terminal of the first operational amplifier (105), the negative input terminal of the first operational amplifier (105) is connected to the tenth terminal, the output terminal of the first operational amplifier (105) is connected to the fifth gate, the ninth terminal is connected to the second terminal, and the eleventh terminal is connected to the fourth terminal, the first terminal and the third terminal are combined and then connected to the eighth terminal, the seventh terminal receives an external supply voltage, the fourth gate is connected to the eighth terminal and the digital-to-analog converter (103), the first gate is connected to the input terminal of the inverter (102), the third gate and the QNOT terminal of an external second flip-flop (112), the second gate is connected to the output terminal of the inverter (102), the tenth terminal is connected to the positive input terminal of the second comparator (108), the tenth terminal and the twelfth terminal are grounded through the fifth resistor (R5) and the sixth resistor (R6), the digital-to-analog converter (103) is connected to one end of the counter (104), the fifth terminal and the seventh resistor (R7), the other end of the seventh resistor (R7) is connected to one end of the eighth resistor (R8) and the negative input terminal of the external third comparator (111), respectively, the other end of the eighth resistor (R8) is grounded, the sixth terminal is connected to one end of the fifth capacitor (C5) and the negative input terminal of the first comparator (107), respectively, the other end of the fifth capacitor (C5) is grounded, the positive input end of the first comparator (107) is connected to a first reference voltage (Vref 1), a negative input of the second comparator (108) is connected to a second reference voltage (Vref 2), the first comparator (107) outputs to the first flip-flop (110), the output terminal of the second comparator (108) is connected to the CLK terminal of the counter (104) and one terminal of a delay circuit (109), respectively, the D end of the first flip-flop (110) receives an external power supply voltage, the Q-not end of the first flip-flop (110) is connected to the UP/DN end of the counter (104), the CLR terminal of the first flip-flop (110) is connected to the other terminal of the delay circuit (109).
2. The circuit for enabling thyristor dimming and high power factor according to claim 1, wherein the first sampling circuit (101) comprises: a ninth resistor (R9), a tenth resistor (R10), an eleventh resistor (R11), a fifth transistor (M5), a sixth capacitor (C6), and a second inverter, one end of the tenth resistor (R10) is connected to the drain of the external first transistor (M1), the other end of the tenth resistor (R10) is connected to one end of the eleventh resistor (R11) and one end of the ninth resistor (R9), respectively, the other end of the eleventh resistor (R11) is grounded, the other end of the ninth resistor (R9) is connected to one end of the fifth transistor (M5), the other end of the fifth transistor (M39 5) is connected to one end of the sixth capacitor (C6) and the positive input terminal of the second operational amplifier (106), the gate of the fifth transistor (M5) is connected to the output terminal of the second inverter, the input terminal of the second inverter is connected to the gate of the external first transistor (M1), the other end of the sixth capacitor (C6) is grounded; the second sampling circuit (118) comprises: a twelfth resistor (R12) and a thirteenth resistor (R13), one end of the twelfth resistor (R12) is connected to the output end of the external LC filter, the other end of the twelfth resistor (R12) is connected to the positive input end of the first operational amplifier (105) and one end of the thirteenth resistor (R13), respectively, and the other end of the thirteenth resistor (R13) is grounded.
3. The circuit for enabling scr dimming and high power factor according to claim 2, wherein the fifth transistor (M5) is an N-type fet.
4. The circuit for enabling thyristor dimming and high power factor according to claim 1, wherein the first sampling circuit (101) comprises: a ninth resistor (R9), a tenth resistor (R10), an eleventh resistor (R11) and a sixth capacitor (C6), wherein one end of the tenth resistor (R10) is connected to the drain of the external first transistor (M1), the other end of the tenth resistor (R10) is respectively connected to one end of the eleventh resistor (R11) and one end of the ninth resistor (R9), the other end of the eleventh resistor (R11) is grounded, the other end of the ninth resistor (R9) is respectively connected to one end of the sixth capacitor (C6) and the positive input end of the second operational amplifier (106), and the other end of the sixth capacitor (C6) is grounded; the second sampling circuit (118) comprises: a twelfth resistor (R12), a thirteenth resistor (R13), a fourteenth resistor (R14), a fifth transistor (M5) and a seventh capacitor (C7), one end of the twelfth resistor (R12) is connected to an output terminal of an external LC filter, and the other end of the twelfth resistor (R12) is connected to one end of the fifth transistor (M5), one end of a thirteenth resistor (R13), and one end of a fourteenth resistor (R14), respectively, the other end of the thirteenth resistor (R13) is grounded, the other end of the fifth transistor (M5) is grounded, a gate of the fifth transistor (M5) is connected to a gate of the external first transistor (M1), the other end of the fourteenth resistor (R14) is connected to the positive input terminal of the first operational amplifier (105) and one end of a seventh capacitor (C7), respectively, and the other end of the seventh capacitor (C7) is grounded.
5. The circuit for enabling thyristor dimming and high power factor according to claim 1, wherein the first sampling circuit (101) comprises: a tenth resistor (R10) and an eleventh resistor (R11), one end of the tenth resistor (R10) is connected to the output end of the external LC filter, the other end of the tenth resistor (R10) is connected to one end of the eleventh resistor (R11) and the positive input end of the second operational amplifier (106), respectively, and the other end of the eleventh resistor (R11) is grounded; the second sampling circuit (118) comprises: a twelfth resistor (R12), a thirteenth resistor (R13), a fourteenth resistor (R14), a fifth transistor (M5) and a seventh capacitor (C7), one end of the twelfth resistor (R12) is connected to an output terminal of an external LC filter, and the other end of the twelfth resistor (R12) is connected to one end of the fifth transistor (M5), one end of a thirteenth resistor (R13), and one end of a fourteenth resistor (R14), respectively, the other end of the thirteenth resistor (R13) is grounded, the other end of the fifth transistor (M5) is grounded, a gate of the fifth transistor (M5) is connected to a gate of the external first transistor (M1), the other end of the fourteenth resistor (R14) is connected to the positive input terminal of the first operational amplifier (105) and one end of a seventh capacitor (C7), respectively, and the other end of the seventh capacitor (C7) is grounded.
6. The circuit for enabling thyristor dimming and high power factor according to claim 1, wherein the first sampling circuit (101) comprises: a ninth resistor (R9), a tenth resistor (R10), an eleventh resistor (R11), a fifth transistor (M5), a sixth capacitor (C6), and a second inverter, one end of the tenth resistor (R10) is connected to the drain of the external first transistor (M1), the other end of the tenth resistor (R10) is connected to one end of the eleventh resistor (R11) and one end of the ninth resistor (R9), respectively, the other end of the eleventh resistor (R11) is grounded, the other end of the ninth resistor (R9) is connected to one end of the fifth transistor (M5), the other end of the fifth transistor (M39 5) is connected to one end of the sixth capacitor (C6) and the positive input terminal of the second operational amplifier (106), the gate of the fifth transistor (M5) is connected to the output terminal of the second inverter, the input terminal of the second inverter is connected to the gate of the external first transistor (M1), the other end of the sixth capacitor (C6) is grounded; the second sampling circuit (118) comprises: the circuit comprises a twelfth resistor (R12), a thirteenth resistor (R13), a fourteenth resistor (R14) and a seventh capacitor (C7), wherein one end of the twelfth resistor (R12) is connected to the drain electrode of the external first transistor (M1), the other end of the twelfth resistor (R12) is respectively connected with one end of the thirteenth resistor (R13) and one end of the fourteenth resistor (R14), the other end of the thirteenth resistor (R13) is grounded, the other end of the fourteenth resistor (R14) is respectively connected to the positive input end of the first operational amplifier (105) and one end of the seventh capacitor (C7), and the other end of the seventh capacitor (C7) is grounded.
7. The circuit of claim 1, further comprising: a critical conduction mode flyback constant current control module, the module comprising: a third comparator (111), a second trigger (112), a gate drive (113), a fourth comparator (114) and a leading edge blanking circuit (115); wherein a negative input terminal of the third comparator (111) is connected to a junction point of the seventh resistor (R7) and an eighth resistor (R8), a positive input terminal of the third comparator (111) is connected to one terminal of the leading edge blanking circuit (115), an output terminal of the third comparator (111) is connected to a D terminal of the second flip-flop (112), an S terminal of the second flip-flop (112) is connected to an output terminal of the fourth comparator (114), a Q terminal of the second flip-flop (112) is connected to an input terminal of the gate driver (113), a Qnon terminal of the second flip-flop (112) is connected to the first gate, a negative input terminal of the fourth comparator (114) is used for sampling a voltage division signal of an external auxiliary winding, a positive input terminal of the fourth comparator (114) receives a fourth reference voltage (Vref 4), an output terminal of the gate driver (113) is connected to a gate of an external first transistor (M1), the other end of the leading edge blanking circuit (115) is connected to the source of the external first transistor (M1).
8. The circuit of claim 7, further comprising: a rectifier bridge; an LC filter; a primary absorption circuit; a transformer composed of a primary winding, a secondary winding and an auxiliary winding; a secondary circuit connected to the secondary winding; an auxiliary power supply circuit connected to the auxiliary winding; a first transistor (M1); a fourth resistor (R4); the rectifier bridge, the LC filter, the primary absorption circuit and the transformer are sequentially connected in series, the drain electrode of the first transistor (M1) is connected to the primary winding, and the source electrode of the first transistor (M1) is grounded through a fourth resistor (R4).
9. The circuit of claim 8, further comprising: a thyristor dimmer (117), the thyristor dimmer (117) connected to a front end of the rectifier bridge.
10. The circuit of claim 9, further comprising: an AC power source (116), the AC power source (116) connected to a front end of the thyristor dimmer (117).
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| CN104682707A (en) * | 2013-11-28 | 2015-06-03 | 深圳市海洋王照明工程有限公司 | Switching power supply for selectable output of voltage |
| CN104159357B (en) * | 2014-06-20 | 2016-03-30 | 东南大学 | A control method and control system for output current effective value and power factor of LED lighting circuit |
| CN105792433B (en) * | 2016-04-19 | 2017-08-25 | 深圳市明微电子股份有限公司 | Switching Power Supply driving chip and controllable silicon light modulation LED drive circuit |
| CN108770132B (en) * | 2018-07-23 | 2023-11-03 | 深圳市明微电子股份有限公司 | LED full-voltage high-efficiency linear driving circuit |
| CN111511074B (en) * | 2020-05-04 | 2021-11-23 | 陕西亚成微电子股份有限公司 | LED driving circuit and control method |
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| CN201438773U (en) * | 2009-07-31 | 2010-04-14 | 深圳市通普科技有限公司 | LED dimming device |
| CN103248207A (en) * | 2013-05-21 | 2013-08-14 | 苏州智浦芯联电子科技有限公司 | Constant-current and constant-voltage fly-back converter based on primary side feedback |
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| EP2609790A2 (en) * | 2010-08-24 | 2013-07-03 | Cirrus Logic, Inc. | Multi-mode dimmer interfacing including attach state control |
| CN203467027U (en) * | 2013-09-02 | 2014-03-05 | 陈畅 | Circuit used for realizing controllable silicon dimming and high power factor |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN201438773U (en) * | 2009-07-31 | 2010-04-14 | 深圳市通普科技有限公司 | LED dimming device |
| CN103248207A (en) * | 2013-05-21 | 2013-08-14 | 苏州智浦芯联电子科技有限公司 | Constant-current and constant-voltage fly-back converter based on primary side feedback |
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Address after: Suzhou City, Jiangsu province 215000 Industrial Park Suzhou Xinping Street No. 388 Suzhou innovation park off the 23 building 3 layer 09, 10 unit Patentee after: SUZHOU INTELLI-CHIPLINK ELECTRONICS TECHNOLOGY CO., LTD. Address before: Suzhou City, Jiangsu province 215000 Industrial Park Suzhou Xinping Street No. 388 Suzhou innovation park off the 23 building 3 layer 09, 10 unit Patentee before: Suzhou Zhipu Xinlian Electronic Technology Co., Ltd. |