CN103412427B - A kind of display panels - Google Patents
A kind of display panels Download PDFInfo
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- CN103412427B CN103412427B CN201310351378.1A CN201310351378A CN103412427B CN 103412427 B CN103412427 B CN 103412427B CN 201310351378 A CN201310351378 A CN 201310351378A CN 103412427 B CN103412427 B CN 103412427B
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- 239000010409 thin film Substances 0.000 claims abstract description 51
- 229910052982 molybdenum disulfide Inorganic materials 0.000 claims description 30
- 238000006243 chemical reaction Methods 0.000 claims description 17
- 239000010408 film Substances 0.000 claims description 15
- 239000012528 membrane Substances 0.000 claims description 13
- 239000004973 liquid crystal related substance Substances 0.000 claims description 11
- 239000000758 substrate Substances 0.000 claims description 9
- 101100102598 Mus musculus Vgll2 gene Proteins 0.000 claims description 6
- 101100102583 Schizosaccharomyces pombe (strain 972 / ATCC 24843) vgl1 gene Proteins 0.000 claims description 6
- 102100023478 Transcription cofactor vestigial-like protein 1 Human genes 0.000 claims description 6
- 102100023477 Transcription cofactor vestigial-like protein 2 Human genes 0.000 claims description 6
- 230000014759 maintenance of location Effects 0.000 abstract description 14
- 238000010586 diagram Methods 0.000 description 10
- 238000000034 method Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
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- Liquid Crystal (AREA)
- Liquid Crystal Display Device Control (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The invention provides a kind of display panels, the non-display area away from gate drivers side is also provided with multiple second thin film transistor (TFT) TFT, and each second thin film transistor (TFT) TFT is corresponding with every scan line of viewing area; Second source electrode of the second thin film transistor (TFT) TFT is connected to the corresponding sweep trace of viewing area, together with the second grid of the second thin film transistor (TFT) TFT and corresponding second drain electrode are connected to each other, and the second gate of the second all thin film transistor (TFT) TFT is extremely connected, display panels is an external circuit board also, and the second gate of all second thin film transistor (TFT) TFT is extremely connected on this circuit board via cabling.The present invention is by increasing multiple thin film transistor (TFT) and an external circuit board at non-display area, circuit is set on circuit boards, by on thin film transistor (TFT) in the signal input on circuit, open the closedown of the thin film transistor (TFT) controlling non-display area or open, thus make the pixel voltage rapid discharge of viewing area, solve shutdown image retention problem.
Description
Technical field
The present invention relates to a kind of for solving the display panels storing image retention when liquid crystal display is shut down.
Background technology
When the dump of display panels, because all external voltages make zero all rapidly, source electrode and gate drivers stop action, the pixel voltage of display panels is only by the Ioff(leakage current of TFT) discharge, because Ioff is very little, so pixel voltage cannot fully discharge, and residual a large amount of electric charge is in pixel, and this phenomenon is referred to as the image retention that shuts down.
Fig. 1 is the drives schematic diagram of available liquid crystal display panel, and display panels comprises the array base palte and color membrane substrates that are oppositely arranged and the liquid crystal be located between array base palte and color membrane substrates, and color membrane substrates is provided with color membrane electrode; Suppose that array base palte horizontal direction has m bar sweep trace G(to be respectively G1, G2, G3 ... Gm), vertical direction has n bar data line S(S1, S2, S3 ... Sn) and public electrode wire (not shown), the liquid crystal display of a n*m pixel is combined into.Sweep trace is all connected to gate drivers 10, data line S is all connected to source electrode driver 20; And sweep trace G intersects with data line S and limits multiple pixel cell, in each pixel cell, be equipped with pixel electrode and film crystal pipe unit TFT.
Public electrode wire is by forming memory capacitance Cs between fixed voltage Vcom and corresponding pixel cell; Liquid crystal capacitance Clc is formed between color membrane electrode and corresponding pixel electrode.
When the power supply of display panels disconnects (Poweroff), can produce a control signal XAO, this control signal XAO is as the input signal of gate drivers 10.When gate drivers 10 receives XAO signal, as shown in Figure 2, if when XAO is low level (Low), then all passages of gate drivers 10 (channel) will export high levle (VGH), TFT all in display panels can open (turnon) by VGH voltage, now pixel voltage just externally can be discharged by the TFT be opened fast, reaches the object improving shutdown image retention.
When LCD board size is more and more large, resolution is more and more high, power supply turn off after in display panels each pixel want rapid discharge more and more difficult, be easy to cause display panels interior incomplete away from the pixel discharge of the IC side of gate drivers, even if output HIGH voltage (VGH) is to all gate channels when shutting down, still can there is so-called shutdown image retention, be illustrated in figure 3 display panels shutdown image retention schematic diagram.
Existingly solve shutdown image retention problem by control signal XAO, XAO signal is high levle under normal circumstances, and when circuit detecting shuts down to power supply, XAO signal can transfer low level to by high levle, this XAO signal by circuit board via COF(ChipOnFlex, or, ChipOnFilm, normal title covers brilliant film) and glass cabling be connected to the IC of gate drivers, after the IC of gate drivers receives XAO signal, XAO must be converted to more high levle, and then export a high voltage (VGH) to all gate channels (Gatechannels), the process of transmission so and conversion, there is regular hour postponement, be unfavorable for solving shutdown image retention.
Therefore need a kind of new driving circuit of design to solve shutdown image retention problem.
Summary of the invention
The object of the invention is to the display panels solving shutdown image retention.
The invention provides a kind of display panels, comprise the liquid crystal during the array base palte and color membrane substrates and sandwiched be oppositely arranged, described array base palte is provided with viewing area and non-display area, array base palte arranges crisscross some sweep traces and data line, sweep trace and intersects with data line and limit multiple pixel cell, be equipped with pixel electrode and the first film transistor TFT in each pixel cell, this first film transistor TFT is positioned at viewing area; The side of display panels is also provided with the gate drivers be connected with sweep trace, the source electrode driver be connected with data line; Non-display area away from gate drivers side is also provided with multiple second thin film transistor (TFT) TFT, and each second thin film transistor (TFT) TFT is corresponding with every scan line of viewing area; Second thin film transistor (TFT) TFT is provided with second grid, the second source electrode and the second drain electrode, second source electrode of the second thin film transistor (TFT) TFT is connected to the corresponding sweep trace of viewing area, together with the second grid of the second thin film transistor (TFT) TFT and corresponding second drain electrode are connected to each other, and the second gate of the second all thin film transistor (TFT) TFT is extremely connected.
Wherein, display panels is an external circuit board also, and the second gate of all second thin film transistor (TFT) TFT is extremely connected on this circuit board via cabling.
Wherein, on described gate drivers, input has control signal XAO.
Wherein, described circuit board is provided with voltage conversion circuit, and the second gate that the output signal end of this voltage conversion circuit is connected to the second thin film transistor (TFT) TFT is extreme.
Wherein, when input control signal is high levle, the output signal of voltage conversion circuit is low level, and the second thin film transistor (TFT) TFT all closes, and display panels maintains regular event; When shutting down at power supply, input control signal is low level, and the output signal of voltage conversion circuit is high levle, and the second thin film transistor (TFT) TFT all opens, and high levle voltage inputs on the sweep trace of viewing area, is opened by the first film transistor TFT.
Wherein, described voltage conversion circuit comprises supply voltage VDD, high voltage VGH, the first low-voltage VGL1, the second low-voltage VGL2, input signal XAO, input signal
xAO, output signal OUT, four P-MOS pipe, four N-MOS pipes, be respectively: P-MOS1, P-MOS2, P-MOS3, P-MOS4, N-MOS1, N-MOS2, N-MOS3, N-MOS4, wherein, input signal XAO and input signal
xAOfor contrary two signals, P-MOS1 with
xAOsignal connects, and P-MOS2 and XAO signal connects; Be connected with supply voltage VDD after P-MOS1 and P-MOS2 parallel connection, P-MOS3 with and P-MOS4 parallel connection after be connected with high voltage VGH, be connected with the first low-voltage VGL1 after N-MOS1 and N-MOS2 parallel connection, after N-MOS3 and N-MOS4 parallel connection, the second low-voltage VGL2 connects, P-MOS1 is also connected in series with N-MOS1, N-MOS2 and N-MOS4 respectively, P-MOS2 is also connected in series with N-MOS1, N-MOS2 and N-MOS3 respectively, and P-MOS3 and N-MOS4 is connected in series, and P-MOS4 and N-MOS3 is connected in series; And P-MOS3, P-MOS4, N-MOS4 are all connected to output signal OUT.
Wherein, when XAO is high levle High, P-MOS1, N-MOS2, P-MOS3, N-MOS4 conducting, output signal OUT is low-voltage VGL; When XAO is low level LOW, P-MOS2, N-MOS1, P-MOS4, N-MOS3 conducting, output signal OUT is high voltage VGH.
The present invention is by increasing multiple thin film transistor (TFT) and an external circuit board at non-display area, circuit is set on circuit boards, by on thin film transistor (TFT) in the signal input on circuit, open the closedown of the thin film transistor (TFT) controlling non-display area or open, thus make the pixel voltage rapid discharge of viewing area, solve shutdown image retention problem.
Accompanying drawing explanation
Figure 1 shows that the drives schematic diagram for available liquid crystal display panel;
Figure 2 shows that the waveform schematic diagram of the sweep trace of the display panels of Fig. 1;
Figure 3 shows that display panels shutdown image retention schematic diagram;
Figure 4 shows that the drives schematic diagram of display panels of the present invention;
Figure 5 shows that Nverter circuit figure;
Figure 6 shows that the voltage conversion circuit figure of display panels of the present invention;
Figure 7 shows that the present invention be XAO signal,
xAOsignal and output signal OUT waveform schematic diagram.
Embodiment
Below in conjunction with the drawings and specific embodiments, illustrate the present invention further, these embodiments should be understood only be not used in for illustration of the present invention and limit the scope of the invention, after having read the present invention, the amendment of those skilled in the art to the various equivalent form of value of the present invention has all fallen within the application's claims limited range.
Figure 4 shows that the drives schematic diagram of display panels of the present invention, display panels comprises the array base palte and color membrane substrates that are oppositely arranged and the liquid crystal be located between array base palte and color membrane substrates, and color membrane substrates is provided with color membrane electrode; Array base palte is provided with viewing area and non-display area, suppose that array base palte horizontal direction has m bar sweep trace G11(to be respectively G1, G2, G3 ... Gm), vertical direction has n bar data line S21(S1, S2, S3 ... and public electrode wire (not shown) Sn), be combined into the liquid crystal display of a n*m pixel, and sweep trace 11 and data line 21 crisscross.The side of display panels is also provided with the gate drivers 10 be connected with sweep trace G, the source electrode driver 20 be connected with data line S; And sweep trace G intersects with data line S and limits multiple pixel cell, be equipped with pixel electrode and the first film transistor TFT30 in each pixel cell, described the first film transistor TFT30 is positioned at viewing area.
Public electrode wire is by forming memory capacitance Cs between fixed voltage Vcom and corresponding pixel cell; Liquid crystal capacitance Clc is formed between color membrane electrode and corresponding pixel electrode.
Display panels away from the non-display area (Non-ActiveArea) of gate drivers 10 side being also provided with multiple second thin film transistor (TFT) TFT (ThinFilmTransistor), and is equipped with one second thin film transistor (TFT) TFT40 on each root sweep trace 11 of non-display area.
If the resolution of this display panels is 1920RGB*1080, represent this display panels and have 1080 sweep traces 11, then all need increase by one second thin film transistor (TFT) TFT40 at these 1080 sweep traces 11, also namely: the second thin film transistor (TFT) TFT40 has 1080.
The first film transistor TFT30 of newly-increased the second thin film transistor (TFT) TFT40 and viewing area that are positioned at non-display area uses same process and parameter, therefore the second newly-increased thin film transistor (TFT) TFT40 can't cause the complicated of processing procedure also can not increase cost.
Described first, second thin film transistor (TFT) TFT is three terminal components, and it includes grid (Gate), source electrode (Source) and drain electrode (Drain).The first grid of described the first film transistor TFT30 connects corresponding sweep trace 11, first source electrode of described the first film transistor TFT30 connects corresponding data line 21, and first drain electrode of described the first film transistor TFT30 connects corresponding pixel electrode; Second source electrode of the second thin film transistor (TFT) TFT40 is connected to the corresponding sweep trace 11 of viewing area, together with the second grid of the second thin film transistor (TFT) TFT40 and corresponding second drain electrode are connected to each other, and the second gate of the second all thin film transistor (TFT) TFT40 is extremely connected, the second gate of all second thin film transistor (TFT) TFT40 is extremely connected on external circuit board 100 via cabling.
The drives schematic diagram of the display panels shown in Fig. 1 of prior art, the control signal XAO inputted, by after a reverser, can obtain the signal contrary with control signal XAO, become
xAO.As shown in Figure 5, Nverter circuit is provided with a P type metal-oxide-semiconductor (P-MOS) and a N-type metal-oxide-semiconductor (N-MOS) to this Nverter circuit, and P-MOS is connected with supply voltage VDD, and N-MOS is connected with ground voltage GND.
When
xAOduring for Low (low level), XAO is High (high levle), and works as
xAOduring for High (high levle), XAO is Low (low level).
By XAO,
xAObe combined to form a voltage conversion circuit with 4 P-MOS, 4 N-MOS, this voltage conversion circuit as shown in Figure 6, by the level of XAO signal by original GND to VDD, can be transformed into VGL(low-voltage) to VGH(high voltage) level.
Described voltage conversion circuit is arranged on external circuit board 100, and voltage conversion circuit exports OUT signal has the second thin film transistor (TFT) TFT40 second grid to display panels.
Voltage conversion circuit comprises supply voltage VDD, high voltage VGH, the first low-voltage VGL1, the second low-voltage VGL2, input signal XAO, input signal
xAO, output signal OUT, four P-MOS pipe, four N-MOS pipes, be respectively: P-MOS1, P-MOS2, P-MOS3 and P-MOS4; N-MOS1, N-MOS2, N-MOS3 and N-MOS4, wherein, be connected with supply voltage VDD after P-MOS1 and P-MOS2 parallel connection, P-MOS3 with and P-MOS4 parallel connection after be connected with high voltage VGH, be connected with the first low-voltage VGL1 after N-MOS1 and N-MOS2 parallel connection, after N-MOS3 and N-MOS4 parallel connection, the second low-voltage VGL2 connects, P-MOS1 is also connected in series with N-MOS1, N-MOS2 and N-MOS4 respectively, P-MOS2 is also connected in series with N-MOS1, N-MOS2 and N-MOS3 respectively, P-MOS3 and N-MOS4 is connected in series, and P-MOS4 and N-MOS3 is connected in series.And P-MOS3, P-MOS4, N-MOS4 are all connected to output signal OUT.
P-MOS1 with
xAOsignal connects, and P-MOS2 and XAO signal connects.
When XAO is High (high levle), P-MOS1, N-MOS2, P-MOS3, N-MOS4 conducting, output OUT is VGL (low-voltage).And when XAO is LOW, P-MOS2, N-MOS1, P-MOS4, N-MOS3 conducting, output OUT is VGH (high voltage), Figure 7 shows that XAO signal,
xAOsignal and output signal OUT waveform schematic diagram.
Under driven, when XAO signal be High, to export OUT signal be VGL time, the second thin film transistor (TFT) TFT40 shown in Fig. 4, because gate electrode side is all connected to minimum voltage (VGL), therefore all second thin film transistor (TFT) TFT40 all close, display panels maintains regular event; And when power supply shuts down, because XAO transfers Low to, so export OUT signal to become VGH, now because the gate electrode side of the second thin film transistor (TFT) TFT40 is ceiling voltage (VGH), therefore all second thin film transistor (TFT) TFT40 all open, VGH voltage can input on the grid cabling of viewing area (ActiveArea), upper to viewing area (ActiveArea) all the first film transistor TFT30 are opened, now pixel voltage rapid discharge, solves shutdown image retention problem.
The present invention is by increasing multiple thin film transistor (TFT) and an external circuit board at non-display area, circuit is set on circuit boards, by on thin film transistor (TFT) in the signal input on circuit, open the closedown of the thin film transistor (TFT) controlling non-display area or open, thus make the pixel voltage rapid discharge of viewing area, solve shutdown image retention problem.
Claims (4)
1. a display panels, comprise the array base palte and color membrane substrates that are oppositely arranged and the liquid crystal between sandwiched array base palte and color membrane substrates, described array base palte is provided with viewing area and non-display area, array base palte arranges crisscross some sweep traces and data line, sweep trace and intersects with data line and limit multiple pixel cell, be equipped with pixel electrode and the first film transistor TFT in each pixel cell, this first film transistor TFT is positioned at viewing area; The side of display panels is also provided with the gate drivers be connected with sweep trace, the source electrode driver be connected with data line; It is characterized in that: on the non-display area away from gate drivers side, be also provided with multiple second thin film transistor (TFT) TFT, and each second thin film transistor (TFT) TFT is corresponding with every scan line of viewing area; Second thin film transistor (TFT) TFT is provided with second grid, the second source electrode and the second drain electrode, second source electrode of the second thin film transistor (TFT) TFT is connected to the corresponding sweep trace of viewing area, together with the second grid of the second thin film transistor (TFT) TFT and corresponding second drain electrode are connected to each other, and the second gate of the second all thin film transistor (TFT) TFT is extremely connected; Display panels is an external circuit board also, the second gate of all second thin film transistor (TFT) TFT is extremely connected on this circuit board via cabling, on described gate drivers, input has control signal XAO, described circuit board is provided with voltage conversion circuit, and the second gate that the output signal end of this voltage conversion circuit is connected to the second thin film transistor (TFT) TFT is extreme.
2. display panels according to claim 1, is characterized in that: when input control signal is high levle, and the output signal of voltage conversion circuit is low level, and the second thin film transistor (TFT) TFT all closes, and display panels maintains regular event; When shutting down at power supply, input control signal is low level, and the output signal of voltage conversion circuit is high levle, and the second thin film transistor (TFT) TFT all opens, and high levle voltage inputs on the sweep trace of viewing area, is opened by the first film transistor TFT.
3. display panels according to claim 2, is characterized in that: described voltage conversion circuit comprises supply voltage VDD, high voltage VGH, the first low-voltage VGL1, the second low-voltage VGL2, input signal XAO, input signal
xAO, output signal OUT, four P-MOS pipe, four N-MOS pipes, be respectively: P-MOS1, P-MOS2, P-MOS3, P-MOS4, N-MOS1, N-MOS2, N-MOS3, N-MOS4, wherein, input signal XAO and input signal
xAOfor contrary two signals, P-MOS1 with
xAOsignal connects, and P-MOS2 and XAO signal connects; Be connected with supply voltage VDD after P-MOS1 and P-MOS2 parallel connection, P-MOS3 with and P-MOS4 parallel connection after be connected with high voltage VGH, be connected with the first low-voltage VGL1 after N-MOS1 and N-MOS2 parallel connection, after N-MOS3 and N-MOS4 parallel connection, the second low-voltage VGL2 connects, P-MOS1 is also connected in series with N-MOS1, N-MOS2 and N-MOS4 respectively, P-MOS2 is also connected in series with N-MOS1, N-MOS2 and N-MOS3 respectively, and P-MOS3 and N-MOS4 is connected in series, and P-MOS4 and N-MOS3 is connected in series; And P-MOS3, P-MOS4, N-MOS4 are all connected to output signal OUT.
4. display panels according to claim 3, is characterized in that: when XAO is high levle High, P-MOS1, N-MOS2, P-MOS3, N-MOS4 conducting, and output signal OUT is low-voltage VGL; When XAO is low level LOW, P-MOS2, N-MOS1, P-MOS4, N-MOS3 conducting, output signal OUT is high voltage VGH.
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| CN201310351378.1A CN103412427B (en) | 2013-08-13 | 2013-08-13 | A kind of display panels |
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| CN201310351378.1A CN103412427B (en) | 2013-08-13 | 2013-08-13 | A kind of display panels |
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| CN103412427A CN103412427A (en) | 2013-11-27 |
| CN103412427B true CN103412427B (en) | 2016-03-16 |
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| CN201310351378.1A Expired - Fee Related CN103412427B (en) | 2013-08-13 | 2013-08-13 | A kind of display panels |
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Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103869516B (en) | 2014-03-12 | 2016-04-06 | 京东方科技集团股份有限公司 | display panel discharge circuit and display device |
| CN105096888B (en) * | 2015-08-28 | 2017-06-23 | 京东方科技集团股份有限公司 | Array base palte, display panel and its driving method |
| CN206370279U (en) * | 2017-01-03 | 2017-08-01 | 京东方科技集团股份有限公司 | Electric charge release circuit, display base plate, display panel and display device |
| CN108281118A (en) * | 2018-01-09 | 2018-07-13 | 昆山龙腾光电有限公司 | Display panel and liquid crystal display device |
| CN110068970B (en) * | 2019-04-18 | 2020-09-11 | 深圳市华星光电半导体显示技术有限公司 | TFT array substrate and display panel |
| CN112255849A (en) | 2020-11-10 | 2021-01-22 | 合肥京东方光电科技有限公司 | Display substrate and electronic device |
| CN112669782A (en) | 2020-12-28 | 2021-04-16 | Tcl华星光电技术有限公司 | Driving circuit of display panel and display device |
| CN113257134B (en) * | 2021-05-28 | 2022-06-10 | 武汉华星光电技术有限公司 | Display panel and display device |
| CN115240583A (en) * | 2022-09-23 | 2022-10-25 | 广州华星光电半导体显示技术有限公司 | Residual charge releasing circuit and display panel |
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| CN2840251Y (en) * | 2005-05-17 | 2006-11-22 | 宏齐科技股份有限公司 | display drive circuit |
| CN1945682A (en) * | 2006-10-27 | 2007-04-11 | 上海广电Nec液晶显示器有限公司 | Control device for quick clearing liquid crystal display panel ghost |
| TW200923896A (en) * | 2007-11-30 | 2009-06-01 | Au Optronics Corp | Liquid crystal display device and method for decaying residual image thereof |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2840251Y (en) * | 2005-05-17 | 2006-11-22 | 宏齐科技股份有限公司 | display drive circuit |
| CN1945682A (en) * | 2006-10-27 | 2007-04-11 | 上海广电Nec液晶显示器有限公司 | Control device for quick clearing liquid crystal display panel ghost |
| TW200923896A (en) * | 2007-11-30 | 2009-06-01 | Au Optronics Corp | Liquid crystal display device and method for decaying residual image thereof |
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