CN103413571B - Storer and utilize this storer to realize the method for error-detection error-correction - Google Patents

Abstract

The invention discloses a memory and a method for realizing error detection and correction by using the memory, which are used to solve the technical problem of poor reliability of the existing memory. The technical solution is that an address error detection circuit and a data inversion control circuit are added to the memory. The memory cell array is arranged in a bit-crossed manner. The method of using the memory to realize error detection and error correction is to increase the input data setup time of the memory and the access time of the memory read data to integrate the error detection and error correction function into the memory; since the memory cell array adopts a bit-interleaved arrangement, it reduces The probability of multiple bit inversions in the same word is guaranteed; the data inversion control circuit is convenient for the single event inversion simulation test of the error detection and error correction circuit. Due to the combination of the error detection and correction circuit and the data storage method of bit crossing, the anti-single event effect level of the memory is further improved, thereby improving the reliability of the memory.

Description

Memory and method for implementing error detection and error correction using the memory

technical field

The present invention relates to a memory. It also relates to a method for realizing error detection and correction by using the memory.

Background technique

Refer to Figure 1. Memory is an information carrier commonly used in electronic systems, and its structure includes input address registers, input data registers, output data registers, memory cell arrays, and other peripheral access circuits. Under the control of the peripheral access circuit, the input data is stored in the position corresponding to the input address in the memory cell array or the data in the position corresponding to the input address in the memory cell array is read out. With the development of space science and nuclear science and technology, memory is widely used as an information storage device for aerospace electronic systems, nuclear detection instruments, high-energy physics experiments, and nuclear medical imaging systems. There are many cosmic rays or high-energy particles in these application environments, and the memory is susceptible to radiation effects such as single-event flipping, single-event latch-up, and total ionizing dose due to the radiation of these particles. With the development of semiconductor integrated circuit manufacturing technology to the deep submicron and nanometer level, the power supply voltage is reduced, the capacitance of circuit nodes is reduced, and the single event flipping effect of memory is becoming more and more serious. Radiation hardening must be carried out through circuit design.

Refer to Figure 2-3. The document "Robert W. James, Arthur H. Waldie, and Timothy John Canales, Internal storage memory with EDAC protection, 2001, US20020147955A1" discloses a memory with an error detection and correction module. In the storage system of this memory, all input data are first generated by a check digit generation circuit to generate a check code and then input to the input data register and stored in the storage unit array together with the check code, using a common data storage format arranged in words; At the same time, the data containing the check code is restored to n-bit output data through the error detection and correction circuit, and the error mark is given at the same time, and the write-back operation is automatically performed.

The main defect of the existing memory and its error detection and correction method is that the single event radiation will cause the data of multiple adjacent storage units to flip, that is, multiple bits flip in the same data word, which will lead to the error detection and correction of one error detection and one error correction. error algorithm fails, or requires the use of more complex error detection and error correction algorithms that can detect and correct multi-bit errors. In addition, in the existing error detection and correction methods, the inversion of the input address cannot be effectively detected, and there is no test interface for simulating single event inversion.

Contents of the invention

In order to overcome the disadvantage of poor reliability of the existing memory, the present invention provides a memory. The memory includes an input data register, an output data register, an input address register, a memory cell array, a peripheral access circuit, a parity generation circuit, an error detection and correction circuit, an address error detection circuit and a data reversal control circuit. The memory cell array is arranged in a bit-crossed manner. The method of using the memory to realize error detection and error correction is to increase the input data setup time of the memory and the access time of the memory read data to integrate the error detection and correction function into the memory; since the memory cell array adopts a bit-interleaved arrangement, it can Reduce the probability of multiple bit flips in the same word; the data flip control circuit facilitates the single event flip simulation test of the error detection and correction circuit. Due to the combination of the error detection and correction circuit and the bit-interleaved data storage method, the anti-single event effect level of the memory can be further improved, thereby improving the reliability of the memory.

The present invention also provides a method for realizing error detection and correction by using the memory.

The technical solution adopted by the present invention to solve the technical problem is: a kind of memory, including input data register, output data register, input address register, storage cell array, peripheral access circuit, parity generation circuit and error detection and correction circuit , which is characterized by: it also includes address error detection circuit and data flipping control circuit. The storage cell array adopts a bit-interleaved structure to store n-bit input data in the input data register, and the n-bit input data passes through a check bit generation circuit to generate a k-bit check code and outputs it together with the check code to the m-bit input data register Middle; under the control of the peripheral access circuit, the data in the input data register is separately written into the position corresponding to the input address in the memory cell array or the data corresponding to the input address position in the memory cell array is read out to the output data register; The m-bit data in the output data register is restored to n-bit output data through the error detection and correction circuit, and an error flag is output at the same time; the input address error detection circuit gives the address error flag in the input address register. The m-bit data generated by the parity generation circuit is entered into the data inversion control circuit to simulate the single event radiation effect, and then output to the error detection and correction circuit for inspection.

A method for implementing error detection and error correction by using the above-mentioned memory is characterized in that it includes the following steps:

Increase the data setup time of the memory and wait for the generation of the check digit, and the input data will generate new data with the check digit through the check digit generation circuit, and the data will be stored in the input data register as the input data of the memory cell array;

The original data and parity bits in the data register are stored in the memory cell array using a bit-interleaved structure;

Increase the data access time of the memory, and output the data of the output data register after being corrected by the error detection and correction circuit;

The output of the parity generation circuit is selected by the data inversion control circuit and some of the bits are inverted, and then enters the error detection and correction circuit;

The address error detection circuit and the data error detection and correction circuit provide address error flags and data error flags, and whether to write back is controlled by the system.

The beneficial effects of the present invention are: the memory includes an input data register, an output data register, an input address register, a memory cell array, a peripheral access circuit, a check bit generation circuit, an error detection and correction circuit, an address error detection circuit and a data flip Control circuit. The memory cell array is arranged in a bit-crossed manner. The method of using the memory to realize error detection and error correction is to increase the input data setup time of the memory and the access time of the memory read data to integrate the error detection and error correction function into the memory; since the memory cell array adopts a bit-interleaved arrangement, it reduces The probability of multi-bit flipping in the same word is realized; the data flipping control circuit is convenient for the single event flipping simulation test of the error detection and correction circuit. Due to the combination of the error detection and correction circuit and the data storage method of bit crossing, the anti-single event effect level of the memory is further improved, thereby improving the reliability of the memory.

The present invention will be described in detail below in conjunction with the accompanying drawings and embodiments.

Description of drawings

FIG. 1 is a schematic structural diagram of a memory in the background technology.

FIG. 2 is a schematic structural diagram of a memory with an error detection and correction module in the background art document.

FIG. 3 is a schematic diagram of a data storage format of the memory cell array in FIG. 2 .

Fig. 4 is a schematic structural diagram of the memory of the present invention.

FIG. 5 is a schematic diagram of a data storage format of the memory cell array in FIG. 4 .

FIG. 6 is a schematic diagram of a data path of the data inversion control circuit in FIG. 4 .

detailed description

Refer to Figure 4-6. The memory of the present invention includes a storage cell array, peripheral access circuits, input address registers, input data registers, output data registers, parity generation circuits, error detection and correction circuits, data reversal control circuits and address error detection circuits. The input data generates new data with a check bit through the check bit generation circuit, and the data will be stored in the input data register as the input data of the memory cell array, and the data of the output data register will be output after being corrected by the error detection and error correction circuit, and Give data error flag. In addition, the input address error detection circuit flags a flip in the input address register, ie, an address error flag. The data error flag and the address error flag will provide basis for other main control modules whether to write back, resend data and so on.

Assuming that there are j words in the same row of the memory, the bit-interleaved data storage format arranges bit 0 to bit m of all j data words in order to realize bit-wise interleaved storage of m-bit data.

When the memory is used to realize the error detection and correction function, only 1-2ns data establishment time and 1-3ns data reading time need to be added, which are respectively used for waiting for generation of parity bits and data correction. The more precise timing depends on the delay of parity bit generation and data correction logic.

In this embodiment, the parity bit generation circuit and the error detection and correction circuit adopt Hamming code (13, 8) and are realized by combinational logic. Suppose the 13-bit data format output from the encoder is {d1, d2, d3, d4, d5, d6, d7, c4, c3, c2, c1, c0}. Where 'di' is the original data, 'ci' is the calibration The code is checked and given by:

c0=d6^d4^d3^d1^d0;

c1=d6^d5^d3^d2^d0;

c2=d7^d3^d2^d1;

c3=d7^d6^d5^d4;

c4=d7^d6^d5^d4^d3^d2^d1^c1^c2^c3.

Store the 13-bit data in memory. If some of the bits are flipped, they need to be corrected when decoding. In the decoder, an adjoint matrix {s4, s3, s2, s1, s0} for locating errors is generated. Where

s4=d7^d6^d5^d4^d3^d2^d1^c1^c2^c3^c4

s3=d7^d6^d5^d4^c3;

s2=d7^d3^d2^d1^c2;

s1=d6^d5^d3^d2^d0^c1;

s0=d6^d4^d3^d1^d0^c0.

The companion matrix {s4, s3, s2, s1, s0} represents the error situation and the error location. If there is only one error, it will be changed to reverse output, and if there are more than two errors, only an error mark will be given. The example algorithm is capable of correcting one-bit errors and detecting two-bit errors.

Each data bit in the data inversion control circuit has two optional paths: data buffering and data inversion. Error-injected bits pass through the data inversion unit, while the remaining bits are directly data-buffered into the following modules. When the memory is in normal operation, the data inversion control circuit can be disconnected by a control signal. In the simulated single event flipping experiment, the output of the check bit generating circuit is selected by the data flipping control circuit to flip some bits, and then enters the error detection and correction circuit.

The method for implementing error detection and error correction by utilizing the above-mentioned storage device specifically includes the following steps:

Increase the data setup time of the memory and wait for the generation of the check digit, and the input data will generate new data with the check digit through the check digit generation circuit, and the data will be stored in the input data register as the input data of the memory cell array;

The original data and parity bits in the data register are stored in the memory cell array using a bit-interleaved structure;

Increase the data access time of the memory, and output the data of the output data register after being corrected by the error detection and correction circuit;

The output of the check bit generation circuit is selected by the data flip control circuit and flips some of the bits, and then enters the error detection and correction circuit;

The address error detection circuit and the data error detection and correction circuit provide address error flags and data error flags, and whether to write back is controlled by the system.

Claims (2)

1. A memory, comprising an input data register, an output data register, an input address register, a memory cell array, a peripheral access circuit, a parity generation circuit and an error detection and correction circuit, characterized in that: it also includes an address error detection circuit and a data flip control circuit; the storage cell array adopts a bit-interleaved structure to store n-bit input data in the input data register, and the n-bit input data generates a k-bit check code through a check bit generation circuit and outputs it together with the check code into the m-bit input data register; under the control of the peripheral access circuit, the data in the input data register is separately written into the position corresponding to the input address in the memory cell array or the data corresponding to the input address position in the memory cell array is read out to the output data register; the m-bit data in the output data register is restored to n-bit output data through an error detection and correction circuit, and an error mark is output at the same time; the input address error detection circuit gives an address error mark in the input address register; the parity bit The m-bit data generated by the generation circuit enters the data inversion control circuit to simulate the single event radiation effect, and then outputs to the error detection and correction circuit for inspection. 2. a method utilizing the memory described in claim 1 to realize error detection and error correction, is characterized in that comprising the following steps: Increase the data setup time of the memory and wait for the generation of the check digit, and the input data will generate new data with the check digit through the check digit generation circuit, and the data will be stored in the input data register as the input data of the memory cell array; The original data and parity bits in the data register are stored in the memory cell array using a bit-interleaved structure; Increase the data access time of the memory, and output the data of the output data register after being corrected by the error detection and correction circuit; The output of the parity generation circuit is selected by the data inversion control circuit and some of the bits are inverted, and then enters the error detection and correction circuit; The address error detection circuit and the data error detection and correction circuit provide address error flags and data error flags, and whether to write back is controlled by the system.