CN103474428B - The two-way ultra-low capacitance TVS device of integrated form and manufacture method thereof - Google Patents
The two-way ultra-low capacitance TVS device of integrated form and manufacture method thereof Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 122
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 38
- 238000002955 isolation Methods 0.000 claims abstract description 37
- 239000000758 substrate Substances 0.000 claims abstract description 34
- 239000002184 metal Substances 0.000 claims abstract description 30
- 238000000137 annealing Methods 0.000 claims description 64
- -1 boron ion Chemical class 0.000 claims description 38
- 229910052796 boron Inorganic materials 0.000 claims description 25
- 238000002513 implantation Methods 0.000 claims description 15
- 229910001439 antimony ion Inorganic materials 0.000 claims description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 3
- 229920005591 polysilicon Polymers 0.000 claims description 3
- 238000005538 encapsulation Methods 0.000 abstract description 8
- 230000007547 defect Effects 0.000 abstract description 5
- 230000015572 biosynthetic process Effects 0.000 abstract description 2
- 230000015556 catabolic process Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 238000004806 packaging method and process Methods 0.000 description 3
- 230000003213 activating effect Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000004151 rapid thermal annealing Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 230000002457 bidirectional effect Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
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Abstract
The invention provides the two-way ultra-low capacitance TVS device of a kind of integrated form and manufacture method, comprising: the first conductivity type substrate is provided; Formation first conductive type epitaxial layer on it; First conductive type epitaxial layer is formed the second conductive type epitaxial layer, forms diode D2; Form isolation structure, and form first area, second area and the 3rd region; Form the first conduction type isolation in the first region, it is connected with the first conductivity type substrate; The second conductive type of trap is formed in the 3rd region; Form the second conductivity type implanted region in the first region, it is isolated with the first conduction type and is connected, and forms diode Z1; In second area and the second conductive type of trap, all form the first conductivity type implanted region, form diode D1 and diode Z2; Form the first metal wire and the second metal wire, connect diode Z1 and diode D1, diode D1 and diode Z2 respectively.Thus the defect avoided in encapsulation, improve device quality.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly the two-way ultra-low capacitance TVS device of a kind of integrated form and manufacture method thereof.
Background technology
Relative to one-way ultra-low capacitance TVS device; two-way ultra-low capacitance TVS device is owing to having the feature of the classical electrical I-V curve (see figure 1) almost symmetry of positive and negative both direction; thus in actual applications, the both direction of protective circuit while of energy, so range of application is wider.Common, in two-way ultra-low capacitance TVS device, power supply electric capacity over the ground can be less than 0.3pF, and the ESD ability of positive and negative both direction can reach and is greater than 8kV.The structure of two-way ultra-low capacitance TVS device in the market roughly has three classes.
Two groups of separation, the duplicate one-way ultra-low capacitance TVS device of performance are connected according to the mode of Fig. 2 by the first kind.Due to VDD-to-VSS two ends full symmetric, two-way ultra-low capacitance performance can be realized.But this structure has the following disadvantages:
1, need two groups of chip to connect, cost is higher;
2, for less packaging body, two groups of chip cannot encapsulate simultaneously;
3, when electric current flows through VDD-to-VSS two ends, because needs are through three diodes, power consumption is comparatively large, easily reduces the peak current capability of device.
Equations of The Second Kind directly the tunnel ends of the one-way ultra-low capacitance TVS device of two passages is drawn, respectively as power end and ground end (see figure 3), due to two tunnel ends full symmetrics, two-way ultra-low capacitance performance can be realized, but this structure has the following disadvantages:
1, two tunnel ends must be drawn from front simultaneously, thus cause chip area comparatively large, and cost is higher on the one hand, is not suitable for less packaging body on the other hand;
2, during encapsulation, two tunnel ends respectively must make a call to a wires, and cost is higher;
3, when electric current flows through passage two ends (VDD-to-VSS two ends), because needs are through three diodes, power consumption is comparatively large, easily reduces the peak current capability of device.
3rd class is formed in parallel according to the mode of Fig. 4 at two groups of one-way ultra-low capacitance TVS device, from the I-V curve of power Vcc GND over the ground, forward and reverse characteristic almost symmetry, but the electric capacity of system line is well below the common double of identical voltage to the electric capacity of TVS diode.
The two-way ultra-low capacitance TVS device combined by two groups of one-way ultra-low capacitance TVS device, the capacitance C of its power Vcc GND over the ground
tcan be expressed as:
Here C
d1and C
d2all less, C
z1and C
z2all large than the above two order of magnitude, so the electric capacity after diode D1 and diode Z1 series connection is equal to the electric capacity of diode D1 substantially; Electric capacity after diode D2 and diode Z2 connects is equal to the electric capacity of diode D2 substantially.And the electric capacity of whole circuit is also just equal to the electric capacity sum of diode D1 and diode D2 substantially.
When power Vcc adds positive potential, when ground GND adds negative potential: because diode D2 puncture voltage is higher, diode Z1 puncture voltage is lower, so diode Z1 takes the lead in puncturing, the reverse breakdown voltage of power Vcc GND over the ground can be expressed as:
V
BR=Vf
D1+V
Z1
Wherein Vf
d1for the forward voltage drop of diode D1.
When power Vcc adds negative potential, when ground GND adds positive potential: because diode D1 puncture voltage is higher, diode Z2 puncture voltage is lower, so diode Z2 takes the lead in puncturing, ground GND can be expressed as the reverse breakdown voltage of power Vcc:
V
BR=Vf
D2+V
Z2
Wherein Vf
d2for the forward voltage drop of diode D2.
If the puncture voltage of visible Z1 with Z2 two diodes is substantially the same, the forward and reverse characteristic of two-way ultra-low capacitance TVS device combined is equivalent to a common bidirectional diode substantially, and its reverse breakdown voltage mainly controls by the puncture voltage of Z1 and Z2 two diodes; Electric capacity is mainly by C
d1and C
d2control, so in order to realize ultra-low capacitance, reality is exactly reduce C
d1and C
d2; Simultaneously the positive and negative direction ESD ability reality of power Vcc GND over the ground is also be equal to the forward ESD ability of D1, D2 two diodes respectively (reverse breakdown voltage of Z1 and Z2 two diodes is lower, general between 3.3V ~ 7.0V, its reverse ESD ability is very high, can not consider).So in order to realize high ESD ability, reality is exactly improve the forward ESD ability of D1, D2 two diodes.
The two-way ultra-low capacitance TVS device Performance comparision of the 3rd class formation is given prominence to, but is formed in parallel by two groups of one-way ultra-low capacitance TVS device due to it, still there is the certain defect in encapsulation.Therefore, the two-way ultra-low capacitance TVS device of a kind of integrated form is provided to become this area problem demanding prompt solution.
Summary of the invention
The object of the present invention is to provide the two-way ultra-low capacitance TVS device of a kind of integrated form and manufacture method thereof, be formed in parallel by two groups of one-way ultra-low capacitance TVS device to solve two-way ultra-low capacitance TVS device of the prior art, there is the problem of the certain defect in encapsulation.
For solving the problems of the technologies described above, the invention provides the manufacture method of the two-way ultra-low capacitance TVS device of a kind of integrated form, the manufacture method of the two-way ultra-low capacitance TVS device of described integrated form comprises:
First conductivity type substrate is provided;
Described first conductivity type substrate forms the first conductive type epitaxial layer;
The second conduction type buried regions is formed in described first conductive type epitaxial layer;
Described first conductive type epitaxial layer forms the second conductive type epitaxial layer, and described first conductive type epitaxial layer and the second conductive type epitaxial layer form diode D2;
Form isolation structure, described isolation structure runs through described second conductive type epitaxial layer, and in described second conductive type epitaxial layer, form first area, second area and the 3rd region;
In described first area, form the first conduction type isolation, and described first conduction type isolation is connected with described first conductivity type substrate;
The second conductive type of trap is formed in described 3rd region;
In described first area, form the second conductivity type implanted region, described second conductivity type implanted region isolates with described first conduction type and is connected, and described second conductivity type implanted region and described first conduction type are isolated and formed diode Z1;
The first conductivity type implanted region is all formed in described second area and the second conductive type of trap, wherein, the first conductivity type implanted region in described second area and the second conductive type epitaxial layer form diode D1, and the first conductivity type implanted region in described second conductive type of trap and the second conductive type of trap form diode Z2;
Form the first metal wire and the second metal wire, wherein, described first metal wire connects described diode Z1 and diode D1, and described second metal wire connects described diode D1 and diode Z2.
Optionally, in the manufacture method of the two-way ultra-low capacitance TVS device of described integrated form, described first conduction type is P type, described second conduction type is N-type; Or described first conduction type is N-type, described second conduction type is P type.
Optionally, in the manufacture method of the two-way ultra-low capacitance TVS device of described integrated form, the resistivity of described first conductivity type substrate is 0.005 Ω .cm ~ 0.2 Ω .cm.
Optionally, in the manufacture method of the two-way ultra-low capacitance TVS device of described integrated form, the resistivity of described first conductive type epitaxial layer is 2.0 Ω .cm ~ 4.0 Ω .cm, and the thickness of described first conductive type epitaxial layer is 6.0 μm ~ 14.0 μm.
Optionally, in the manufacture method of the two-way ultra-low capacitance TVS device of described integrated form, in described first conductive type epitaxial layer, form the second conduction type buried regions by following technique:
In described first conductive type epitaxial layer, inject antimony ion, the implantation dosage of described antimony ion is 2.0E15 ~ 6.0E15;
Perform annealing process to described antimony ion, the temperature of described annealing process is 1200 DEG C ~ 1250 DEG C; The time of described annealing process is 2.0h ~ 6.0h.
Optionally, in the manufacture method of the two-way ultra-low capacitance TVS device of described integrated form, the resistivity of described second conductive type epitaxial layer is 25 Ω .cm ~ 35 Ω .cm, and the thickness of described second conductive type epitaxial layer is 6.0 μm ~ 12.0 μm.
Optionally, in the manufacture method of the two-way ultra-low capacitance TVS device of described integrated form, described isolation structure is formed by following technique:
Form groove, described groove runs through described second conductive type epitaxial layer, and the degree of depth of described groove is 10 μm ~ 20 μm, cross-sectional width is 1.5 μm ~ 3.0 μm;
Fill polysilicon in the trench.
Optionally, in the manufacture method of the two-way ultra-low capacitance TVS device of described integrated form, in described first area, form the first conduction type isolation by following technique:
In described first area, inject boron ion, the implantation dosage of described boron ion is 2.0E14 ~ 4.5E15;
Perform annealing process to described boron ion, the temperature of described annealing process is 1200 DEG C ~ 1250 DEG C; The time of described annealing process is 2.0h ~ 6.0h.
Optionally, in the manufacture method of the two-way ultra-low capacitance TVS device of described integrated form, in described first area, form the second conductivity type implanted region by following technique:
In described first area, inject phosphonium ion, the implantation dosage of described phosphonium ion is 1.0E15 ~ 1.0E16;
First time annealing process is performed to described phosphonium ion, described first time the temperature of annealing process be 1100 DEG C ~ 1200 DEG C; The time of annealing process described first time is 10s ~ 20s;
Perform second time annealing process to described phosphonium ion, the temperature of described second time annealing process is 800 DEG C ~ 900 DEG C; The time of described second time annealing process is 30min ~ 60min.
Optionally, in the manufacture method of the two-way ultra-low capacitance TVS device of described integrated form, in described second area and the second conductive type of trap, all form the first conductivity type implanted region by following technique:
In described second area and the second conductive type of trap, all inject boron ion, the implantation dosage of described boron ion is 1.0E15 ~ 1.0E16;
First time annealing process is performed to described boron ion, described first time the temperature of annealing process be 1100 DEG C ~ 1200 DEG C; The time of annealing process described first time is 10s ~ 20s;
Perform second time annealing process to described boron ion, the temperature of described second time annealing process is 800 DEG C ~ 900 DEG C; The time of described second time annealing process is 30min ~ 60min.
Optionally, in the manufacture method of the two-way ultra-low capacitance TVS device of described integrated form, described first conductivity type substrate is held with being, described second metal wire is connected with power end.
The two-way ultra-low capacitance TVS device of integrated form that the present invention also provides the manufacture method of a kind of above-mentioned integrated form two-way ultra-low capacitance TVS device to be formed, the two-way ultra-low capacitance TVS device of described integrated form comprises:
First conductivity type substrate;
Be formed at the first conductive type epitaxial layer in described first conductivity type substrate;
Be formed at the second conduction type buried regions in described first conductive type epitaxial layer;
Be formed at the second conductive type epitaxial layer on described first conductive type epitaxial layer, described first conductive type epitaxial layer and the second conductive type epitaxial layer form diode D2;
Isolation structure, described isolation structure runs through described second conductive type epitaxial layer, and in described second conductive type epitaxial layer, define first area, second area and the 3rd region;
Be formed at the first conduction type isolation in described first area, described first conduction type isolation is connected with described first conductivity type substrate;
Be formed at the second conductive type of trap in described 3rd region;
Be formed at the second conductivity type implanted region in described first area, described second conductivity type implanted region isolates with described first conduction type and is connected, and described second conductivity type implanted region and described first conduction type are isolated and formed diode Z1;
Be formed at the first conductivity type implanted region in described second area and the second conductive type of trap, wherein, the first conductivity type implanted region in described second area and the second conductive type epitaxial layer form diode D1, and the first conductivity type implanted region in described second conductive type of trap and the second conductive type of trap form diode Z2; And
Connect first metal wire of described diode Z1 and diode D1, connect second metal wire of described diode D1 and diode Z2.
In the two-way ultra-low capacitance TVS device of integrated form provided by the invention and manufacture method thereof, the two-way ultra-low capacitance TVS device formed is integrated structure, thus avoids the defect in encapsulation, improves device quality.
Accompanying drawing explanation
Fig. 1 is the forward and reverse I-V curve of two-way ultra-low capacitance TVS device;
Fig. 2 is the first kind two-way ultra-low capacitance TVS circuit diagram;
Fig. 3 is Equations of The Second Kind two-way ultra-low capacitance TVS circuit diagram;
Fig. 4 is the 3rd class two-way ultra-low capacitance TVS circuit diagram;
Fig. 5 ~ 16 are the generalized sections of the device that the manufacture method of the two-way ultra-low capacitance TVS device of integrated form of the embodiment of the present invention is formed.
Embodiment
The two-way ultra-low capacitance TVS device of integrated form proposed the present invention below in conjunction with the drawings and specific embodiments and manufacture method thereof are described in further detail.According to the following describes and claims, advantages and features of the invention will be clearer.It should be noted that, accompanying drawing all adopts the form that simplifies very much and all uses non-ratio accurately, only in order to object that is convenient, the aid illustration embodiment of the present invention lucidly.
Present embodiments provide the manufacture method of the two-way ultra-low capacitance TVS device of a kind of integrated form, comprising:
S10: the first conductivity type substrate is provided;
S11: form the first conductive type epitaxial layer in described first conductivity type substrate;
S12: form the second conduction type buried regions in described first conductive type epitaxial layer;
S13: form the second conductive type epitaxial layer on described first conductive type epitaxial layer, described first conductive type epitaxial layer and the second conductive type epitaxial layer form diode D2;
S14: form isolation structure, described isolation structure runs through described second conductive type epitaxial layer, and forms first area, second area and the 3rd region in described second conductive type epitaxial layer;
S15: form the first conduction type isolation in described first area, and described first conduction type isolation is connected with described first conductivity type substrate;
S16: form the second conductive type of trap in described 3rd region;
S17: form the second conductivity type implanted region in described first area, described second conductivity type implanted region isolates with described first conduction type and is connected, and described second conductivity type implanted region and described first conduction type are isolated and formed diode Z1;
S18: all form the first conductivity type implanted region in described second area and the second conductive type of trap, wherein, the first conductivity type implanted region in described second area and the second conductive type epitaxial layer form diode D1, and the first conductivity type implanted region in described second conductive type of trap and the second conductive type of trap form diode Z2;
S19: form the first metal wire and the second metal wire, wherein, described first metal wire connects described diode Z1 and diode D1, and described second metal wire connects described diode D1 and diode Z2.
Concrete, please refer to Fig. 5 ~ 16, the generalized section of the device that the manufacture method of the two-way ultra-low capacitance TVS device of its integrated form being the embodiment of the present invention is formed.
As shown in Figure 5, provide the first conductivity type substrate 10, described first conductivity type substrate 10 can be P type substrate, also can be N-type substrate.In the present embodiment, described first conduction type is P type, and follow-up the second conduction type related to is N-type.In other embodiments of the application, also can be the first conduction type be N-type, the second conduction type be P type.The resistivity of described first conductivity type substrate 10 is 0.005 Ω .cm ~ 0.2 Ω .cm.
Then, as shown in Figure 6, described first conductivity type substrate 10 forms the first conductive type epitaxial layer 11, described first conductive type epitaxial layer 11 is P type epitaxial loayer, and it generates by chemical vapor deposition method.Preferably, the resistivity of described first conductive type epitaxial layer 11 is 2.0 Ω .cm ~ 4.0 Ω .cm, and the thickness of described first conductive type epitaxial layer 11 is 6.0 μm ~ 14.0 μm.Such as, the resistivity of described first conductive type epitaxial layer 11 is 2.2 Ω .cm, 2.4 Ω .cm, 2.7 Ω .cm, 3.0 Ω .cm, 3.3 Ω .cm, 3.5 Ω .cm or 3.7 Ω .cm; The thickness of described first conductive type epitaxial layer 11 is 6.5 μm, 7.0 μm, 7.5 μm, 8.0 μm, 9.0 μm, 10.0 μm, 11.5 μm, 12.5 μm or 13.5 μm.
As shown in Figure 7, in described first conductive type epitaxial layer 11, form the second conduction type buried regions 12, described second conduction type buried regions 12 is n type buried layer.Concrete, form described second conduction type buried regions 12 by following technique: in described first conductive type epitaxial layer 11, inject antimony ion, the implantation dosage of described antimony ion is 2.0E15 ~ 6.0E15; Perform annealing process to described antimony ion, the temperature of described annealing process is 1200 DEG C ~ 1250 DEG C; The time of described annealing process is 2.0h ~ 6.0h.Such as, in described first conductive type epitaxial layer 11, inject antimony ion, the implantation dosage of described antimony ion is 4.0E15; Perform annealing process to described antimony ion, the temperature of described annealing process is 1225 DEG C; The time of described annealing process is 4.0h.
As shown in Figure 8, described first conductive type epitaxial layer 11 forms the second conductive type epitaxial layer 13, described second conductive type epitaxial layer 13 is N-type epitaxy layer, and described first conductive type epitaxial layer 11 and the second conductive type epitaxial layer 13 form diode D2.Preferably, the resistivity of described second conductive type epitaxial layer 13 is 25 Ω .cm ~ 35 Ω .cm, and the thickness of described second conductive type epitaxial layer 13 is 6.0 μm ~ 12.0 μm.Such as, the resistivity of described second conductive type epitaxial layer 13 is 26 Ω .cm, 27 Ω .cm, 28 Ω .cm, 29 Ω .cm, 30 Ω .cm, 31 Ω .cm, 32 Ω .cm, 33 Ω .cm or 34 Ω .cm; The thickness of described second conductive type epitaxial layer 13 is 7.5 μm, 8.2 μm, 9.6 μm, 10.5 μm or 11.2 μm.Wherein, the capacitance size of described diode D2 is achieved by the area adjusting described first conductive type epitaxial layer 11 and the second conductive type epitaxial layer 13, repeats no more this application.
Then, as shown in Figure 9, form groove 14, described groove 14 runs through described second conductive type epitaxial layer 13, and forms first area A, second area B and the 3rd region C in described second conductive type epitaxial layer 13.Preferably, the degree of depth of described groove 14 is 10 μm ~ 20 μm, cross-sectional width is 1.5 μm ~ 3.0 μm.Such as, the degree of depth of described groove 14 is 12 μm, 13 μm, 15 μm, 17 μm or 19 μm; The cross-sectional width of described groove 14 is 1.7 μm, 1.9 μm, 2.2 μm, 2.5 μm, 2.7 μm or 2.9 μm.
Then, as shown in Figure 10, in described groove 14, fill polysilicon, form isolation structure 15, namely described isolation structure 15 runs through described second conductive type epitaxial layer 13, and forms first area A, second area B and the 3rd region C in described second conductive type epitaxial layer 13.
Then, as shown in figure 11, form the first conduction type isolation 16 in described first area A, described first conduction type isolation 16 is the isolation of P type, and described first conduction type isolation 16 is connected with described first conductivity type substrate 10.Concrete, form the first conduction type isolation 16 by following technique: in described first area A, inject boron ion, the implantation dosage of described boron ion is 2.0E14 ~ 4.5E15; Perform annealing process to described boron ion, the temperature of described annealing process is 1200 DEG C ~ 1250 DEG C; The time of described annealing process is 2.0h ~ 6.0h.Such as, inject boron ion in described first area, the implantation dosage of described boron ion is 2.0E15; Perform annealing process to described boron ion, the temperature of described annealing process is 1220 DEG C; The time of described annealing process is 2.5h.
As shown in figure 12, in described 3rd region C, form the second conductive type of trap 17, described second conductive type of trap 17 is N-type trap.Concrete, described second conductive type of trap 17 is formed by following technique: in described 3rd region C, inject phosphonium ion, and the implantation dosage of described phosphonium ion is 1.0E14 ~ 5.0E14.
As shown in figure 13, the second conductivity type implanted region 18 is formed in described first area A, described second conductivity type implanted region 18 is N-type injection region, described second conductivity type implanted region 18 isolates 16 with described first conduction type and is connected, and described second conductivity type implanted region 18 isolates 16 with described first conduction type and forms diode Z1.Concrete, described second conductivity type implanted region 18 is formed by following technique: in described first area A, inject phosphonium ion, and the implantation dosage of described phosphonium ion is 1.0E15 ~ 1.0E16; First time annealing process is performed to described phosphonium ion, described first time the temperature of annealing process be 1100 DEG C ~ 1200 DEG C; The time of annealing process described first time is 10s ~ 20s; Perform second time annealing process to described phosphonium ion, the temperature of described second time annealing process is 800 DEG C ~ 900 DEG C; The time of described second time annealing process is 30min ~ 60min.The diode Z1 formed by above-mentioned technique is the low pressure diode of 3.3V ~ 7.0V.Wherein, annealing process also can be called high temperature rapid thermal annealing technique for the first time, its objective is the phosphorus impurities activating all injections, while guaranteeing to form good ohmic contact, also reduces the reverse leakage current of diode Z1; Second time annealing process also can be called low temperature furnace anneal process, its objective is the junction depth and puncture voltage that control diode Z1, guarantees that puncture voltage is at about 3.3V-7.0V.
Then, as shown in figure 14, the first conductivity type implanted region is all formed in described second area B and the second conductive type of trap 17, wherein, the first conductivity type implanted region 19a in described second area B and the second conductive type epitaxial layer 13 form diode D1, and the first conductivity type implanted region 19b in described second conductive type of trap 17 and the second conductive type of trap 17 form diode Z2.Concrete, form the first conductivity type implanted region by following technique: in described second area B and the second conductive type of trap 17, all inject boron ion, the implantation dosage of described boron ion is 1.0E15 ~ 1.0E16; First time annealing process is performed to described boron ion, described first time the temperature of annealing process be 1100 DEG C ~ 1200 DEG C; The time of annealing process described first time is 10s ~ 20s; Perform second time annealing process to described boron ion, the temperature of described second time annealing process is 800 DEG C ~ 900 DEG C; The time of described second time annealing process is 30min ~ 60min.Wherein, annealing process also can be called high temperature rapid thermal annealing technique for the first time, its objective is the boron impurity activating all injections, while guaranteeing to form good ohmic contact, also reduces the reverse leakage current of diode Z2; Second time annealing process also can be called low temperature furnace anneal process; its objective is the junction depth controlling diode D1 on the one hand; guarantee that junction depth is at 0.5 μm about-1.0 μm, control junction depth and the puncture voltage of diode Z2 on the other hand, guarantee that puncture voltage is at about 3.3V-7.0V.
Then, as shown in figure 16, form the first metal wire 21a and the second metal wire 21b, wherein, described first metal wire 21a connects described diode Z1 and diode D1, and described second metal wire 21b connects described diode D1 and diode Z2.Concrete, can with reference to Figure 15, described second conductive type epitaxial layer 13 forms dielectric layer 20, and described dielectric layer 20 exposes diode Z1, diode D1 and diode Z2; Then, with reference to Figure 16, by deposited metal, the first metal wire 21a and the second metal wire 21b can be formed.
In the present embodiment, described first conductivity type substrate 10 is held with being, described second metal wire 21b is connected with power end.Namely the first conductivity type substrate 10 is directly as the electrode of ground connection GND, thus do not need to draw ground connection GND electrode, so not only can reduce the size of chip, meet the encapsulation of more small size, during encapsulation, the first conductivity type substrate 10 is directly drawn as GND electrode in addition, can reduce by 1 wires, greatly reduce packaging cost.
Please continue to refer to Figure 16, define the two-way ultra-low capacitance TVS device of following integrated form by the manufacture method of above-mentioned integrated form two-way ultra-low capacitance TVS device, specifically comprise:
First conductivity type substrate 10;
Be formed at the first conductive type epitaxial layer 11 in described first conductivity type substrate 10;
Be formed at the second conduction type buried regions 12 in described first conductive type epitaxial layer 11;
Be formed at the second conductive type epitaxial layer 13 on described first conductive type epitaxial layer 11, described first conductive type epitaxial layer 11 and the second conductive type epitaxial layer 13 form diode D2;
Isolation structure 15, described isolation structure 15 runs through described second conductive type epitaxial layer 13, and defines first area A, second area B and the 3rd region C in described second conductive type epitaxial layer 13;
Be formed at the first conduction type isolation 16 in described first area A, described first conduction type isolation 16 is connected with described first conductivity type substrate 10;
Be formed at the second conductive type of trap 17 in described 3rd region C;
Be formed at the second conductivity type implanted region 18 in described first area A, described second conductivity type implanted region 18 isolates 16 with described first conduction type and is connected, and described second conductivity type implanted region 18 isolates 16 with described first conduction type and forms diode Z1;
Be formed at the first conductivity type implanted region in described second area B and the second conductive type of trap 17, wherein, the first conductivity type implanted region 19a in described second area B and the second conductive type epitaxial layer 13 form diode D1, and the first conductivity type implanted region 19b in described second conductive type of trap 17 and the second conductive type of trap 17 form diode Z2; And
Connect the first metal wire 21a of described diode Z1 and diode D1, connect the second metal wire 21b of described diode D1 and diode Z2.
In the two-way ultra-low capacitance TVS device of integrated form provided at the present embodiment and manufacture method thereof, the two-way ultra-low capacitance TVS device formed is integrated structure, thus avoids the defect in encapsulation, improves device quality.
Foregoing description is only the description to present pre-ferred embodiments, any restriction not to the scope of the invention, and any change that the those of ordinary skill in field of the present invention does according to above-mentioned disclosure, modification, all belong to the protection range of claims.
Claims (12)
1. a manufacture method for the two-way ultra-low capacitance TVS device of integrated form, is characterized in that, comprising:
First conductivity type substrate is provided;
Described first conductivity type substrate forms the first conductive type epitaxial layer;
The second conduction type buried regions is formed in described first conductive type epitaxial layer;
Described first conductive type epitaxial layer forms the second conductive type epitaxial layer, and described first conductive type epitaxial layer and the second conductive type epitaxial layer form diode D2;
Form isolation structure, described isolation structure runs through described second conductive type epitaxial layer, and in described second conductive type epitaxial layer, form first area, second area and the 3rd region;
In described first area, form the first conduction type isolation, and described first conduction type isolation is connected with described first conductivity type substrate;
The second conductive type of trap is formed in described 3rd region;
In described first area, form the second conductivity type implanted region, described second conductivity type implanted region isolates with described first conduction type and is connected, and described second conductivity type implanted region and described first conduction type are isolated and formed diode Z1;
The first conductivity type implanted region is all formed in described second area and the second conductive type of trap, wherein, the first conductivity type implanted region in described second area and the second conductive type epitaxial layer form diode D1, and the first conductivity type implanted region in described second conductive type of trap and the second conductive type of trap form diode Z2;
Form the first metal wire and the second metal wire, wherein, described first metal wire connects described diode Z1 and diode D1, and described second metal wire connects described diode D1 and diode Z2.
2. the manufacture method of the two-way ultra-low capacitance TVS device of integrated form as claimed in claim 1, is characterized in that, described first conduction type is P type, described second conduction type is N-type; Or described first conduction type is N-type, described second conduction type is P type.
3. the manufacture method of the two-way ultra-low capacitance TVS device of integrated form as claimed in claim 1 or 2, it is characterized in that, the resistivity of described first conductivity type substrate is 0.005 Ω cm ~ 0.2 Ω cm.
4. the manufacture method of the two-way ultra-low capacitance TVS device of integrated form as claimed in claim 1 or 2, it is characterized in that, the resistivity of described first conductive type epitaxial layer is 2.0 Ω cm ~ 4.0 Ω cm, and the thickness of described first conductive type epitaxial layer is 6.0 μm ~ 14.0 μm.
5. the manufacture method of the two-way ultra-low capacitance TVS device of integrated form as claimed in claim 1 or 2, is characterized in that, form the second conduction type buried regions by following technique in described first conductive type epitaxial layer:
In described first conductive type epitaxial layer, inject antimony ion, the implantation dosage of described antimony ion is 2.0E15 ~ 6.0E15;
Perform annealing process to described antimony ion, the temperature of described annealing process is 1200 DEG C ~ 1250 DEG C; The time of described annealing process is 2.0h ~ 6.0h.
6. the manufacture method of the two-way ultra-low capacitance TVS device of integrated form as claimed in claim 1 or 2, it is characterized in that, the resistivity of described second conductive type epitaxial layer is 25 Ω cm ~ 35 Ω cm, and the thickness of described second conductive type epitaxial layer is 6.0 μm ~ 12.0 μm.
7. the manufacture method of the two-way ultra-low capacitance TVS device of integrated form as claimed in claim 1 or 2, it is characterized in that, described isolation structure is formed by following technique:
Form groove, described groove runs through described second conductive type epitaxial layer, and the degree of depth of described groove is 10 μm ~ 20 μm, cross-sectional width is 1.5 μm ~ 3.0 μm;
Fill polysilicon in the trench.
8. the manufacture method of the two-way ultra-low capacitance TVS device of integrated form as claimed in claim 1 or 2, is characterized in that, forms the first conduction type isolation by following technique in described first area:
In described first area, inject boron ion, the implantation dosage of described boron ion is 2.0E14 ~ 4.5E15;
Perform annealing process to described boron ion, the temperature of described annealing process is 1200 DEG C ~ 1250 DEG C; The time of described annealing process is 2.0h ~ 6.0h.
9. the manufacture method of the two-way ultra-low capacitance TVS device of integrated form as claimed in claim 1 or 2, is characterized in that, form the second conductivity type implanted region by following technique in described first area:
In described first area, inject phosphonium ion, the implantation dosage of described phosphonium ion is 1.0E15 ~ 1.0E16;
First time annealing process is performed to described phosphonium ion, described first time the temperature of annealing process be 1100 DEG C ~ 1200 DEG C; The time of annealing process described first time is 10s ~ 20s;
Perform second time annealing process to described phosphonium ion, the temperature of described second time annealing process is 800 DEG C ~ 900 DEG C; The time of described second time annealing process is 30min ~ 60min.
10. the manufacture method of the two-way ultra-low capacitance TVS device of integrated form as claimed in claim 1 or 2, is characterized in that, all form the first conductivity type implanted region by following technique in described second area and the second conductive type of trap:
In described second area and the second conductive type of trap, all inject boron ion, the implantation dosage of described boron ion is 1.0E15 ~ 1.0E16;
First time annealing process is performed to described boron ion, described first time the temperature of annealing process be 1100 DEG C ~ 1200 DEG C; The time of annealing process described first time is 10s ~ 20s;
Perform second time annealing process to described boron ion, the temperature of described second time annealing process is 800 DEG C ~ 900 DEG C; The time of described second time annealing process is 30min ~ 60min.
The manufacture method of the two-way ultra-low capacitance TVS device of 11. integrated form as claimed in claim 1 or 2, it is characterized in that, described first conductivity type substrate is held with being, described second metal wire is connected with power end.
The manufacture method of the 12. 1 kinds of two-way ultra-low capacitance of the integrated form according to any one of claim 1 ~ 11 TVS device the two-way ultra-low capacitance TVS device of integrated form that formed, it is characterized in that, comprising:
First conductivity type substrate;
Be formed at the first conductive type epitaxial layer in described first conductivity type substrate;
Be formed at the second conduction type buried regions in described first conductive type epitaxial layer;
Be formed at the second conductive type epitaxial layer on described first conductive type epitaxial layer, described first conductive type epitaxial layer and the second conductive type epitaxial layer form diode D2;
Isolation structure, described isolation structure runs through described second conductive type epitaxial layer, and in described second conductive type epitaxial layer, define first area, second area and the 3rd region;
Be formed at the first conduction type isolation in described first area, described first conduction type isolation is connected with described first conductivity type substrate;
Be formed at the second conductive type of trap in described 3rd region;
Be formed at the second conductivity type implanted region in described first area, described second conductivity type implanted region isolates with described first conduction type and is connected, and described second conductivity type implanted region and described first conduction type are isolated and formed diode Z1;
Be formed at the first conductivity type implanted region in described second area and the second conductive type of trap, wherein, the first conductivity type implanted region in described second area and the second conductive type epitaxial layer form diode D1, and the first conductivity type implanted region in described second conductive type of trap and the second conductive type of trap form diode Z2; And
Connect first metal wire of described diode Z1 and diode D1, connect second metal wire of described diode D1 and diode Z2.
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| KR101570217B1 (en) | 2014-07-09 | 2015-11-18 | 주식회사 케이이씨 | transient voltage suppressor and manufacturing method thereof |
| CN106129058B (en) * | 2016-08-27 | 2023-08-25 | 上海维安半导体有限公司 | Trench lead-out integrated low-voltage bidirectional transient voltage suppressor and manufacturing method thereof |
| CN106783844B (en) * | 2017-01-25 | 2023-09-01 | 杭州士兰集成电路有限公司 | Unidirectional low-capacitance TVS device and manufacturing method thereof |
| CN107170738B (en) * | 2017-05-22 | 2019-07-19 | 富芯微电子有限公司 | A kind of low-capacitance unidirectional TVS device and its manufacturing method |
| CN107919355B (en) * | 2017-08-14 | 2023-09-19 | 上海领矽半导体有限公司 | Ultralow-residual-voltage low-capacity transient voltage suppressor and manufacturing method thereof |
| CN109346465B (en) * | 2018-11-14 | 2023-11-14 | 无锡欣昱微电子有限公司 | A low clamping protection device structure and its manufacturing method |
| CN111640740A (en) * | 2020-06-03 | 2020-09-08 | 捷捷微电(上海)科技有限公司 | TVS device and manufacturing method thereof |
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| US8338854B2 (en) * | 2009-03-31 | 2012-12-25 | Alpha And Omega Semiconductor Incorporated | TVS with low capacitance and forward voltage drop with depleted SCR as steering diode |
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