CN103474432A - Array substrate and preparation method and display device of array substrate - Google Patents

Abstract

The invention provides an array substrate, its preparation method and a display device, which are used to reduce the voltage difference of the common electrode layer between different pixel units and increase the aperture ratio of the pixel at the same time. The array substrate includes: a base substrate, gate lines and data lines arranged crosswise on the base substrate, and pixel units arranged in a matrix divided by the gate lines and data lines, and a thin film is arranged in the pixel units A transistor, a pixel electrode and a common electrode layer, the thin film transistor includes a gate, a first insulating layer, a source, a drain and an active layer, and the array substrate also includes: a conductive performance black matrix, the black matrix is electrically connected to the common electrode layer; and a second insulating layer for insulating the black matrix and the common electrode layer from the thin film transistor, the second insulating layer The coverage area overlaps with those of the black matrix and the common electrode layer.

Description

A kind of array substrate and its preparation method and display device

technical field

The invention relates to the technical field of liquid crystal display, in particular to an array substrate, a preparation method thereof, and a display device.

Background technique

Thin Film Transistor Liquid Crystal Display (TFT-LCD) has the characteristics of small size, low power consumption, and no radiation. It has developed rapidly in recent years and occupies a dominant position in the current flat panel display market. TFT-LCD has been widely used in various large, medium and small size products, almost covering the main electronic products in today's information society, such as LCD TV, high-definition digital TV, computer, mobile phone, vehicle display, projection display, video camera , digital cameras, electronic watches, calculators, electronic instruments, meters, public displays and virtual displays, etc.

TFT-LCD is composed of liquid crystal display panel, driving circuit and backlight module, and liquid crystal display panel is an important part of TFT-LCD. The liquid crystal display panel is formed by injecting liquid crystal between the array substrate and the color filter substrate, sealing the surrounding area with a sealant, and then attaching polarizers whose polarization directions are perpendicular to each other on the array substrate and the color filter substrate. Wherein, matrix-arranged thin film transistors, pixel electrodes and peripheral circuits are formed on the array substrate. The color filter substrate (Color Filter, CF,) consists of three primary color resins of red (R), green (G), and blue (B) to form pixels, and a transparent common electrode is formed.

In order to block the light in the light-transmitting area, the liquid crystal panels in the prior art are all provided with a black matrix on the color filter substrate. In the design, the width of the black matrix is the sum of the width of the light leakage area and the error of the box alignment accuracy. However, due to the large error of the box alignment accuracy, the width d1 of the black matrix set on the color filter substrate is generally relatively large, resulting in TFT- LCD has defects such as low aperture ratio and low display brightness.

At the same time, in order to reduce the voltage difference of the common electrode between pixels, for the multi-dimensional electric field type TFT-LCD, there is currently a design as shown in Figure 1 below, Figure 1 is a cross-sectional structure diagram of a display panel in the prior art to reduce the resistance of the common electrode layer , so that the transparent and conductive common electrode layer 20 is directly placed on the metal layer 11 of the same layer as the grid 10, so that the materials used for the metal layer 11 set on the same layer as the grid 10 are generally chromium (Cr), tungsten (W ), titanium (Ti), (Ta), (Mo), (Al), (Cu) and other metals and their alloys, the common electrode layer 20 is generally indium tin oxide, indium zinc oxide, aluminum zinc oxide, etc., the resistance of the former The resistivity of the latter is much smaller than that of the latter, so the total resistance after the two are connected in parallel is much smaller than the resistance of the common electrode layer, which can effectively reduce the resistance value of the common electrode layer, thereby reducing the voltage difference of the common electrode between pixels. However, since the metal layer 11 on the same layer as the gate 10 is a non-transparent metal, it will cause a large loss to the aperture ratio of the pixel.

Referring to FIG. 1 and FIG. 2 , FIG. 2 is a schematic plan view of the display panel shown in FIG. 1 . 1 and 2, it can be seen that the display panel includes: a TFT array substrate, a color filter substrate, and a liquid crystal layer (not shown) arranged between the array substrate and the color filter substrate, wherein the The array substrate includes: a gate 10, a metal layer 11 and a gate line 12 arranged on the same layer and made of the same material as the gate 10, a transparent and conductive common electrode layer 20, and the common electrode layer 20 covers the metal layer 11. The first insulating layer 30, the active layer 40, the data line layer 50 (specifically including: the data line 501, the source electrode 502 and the drain electrode 503), and the pixel electrode layer 60; wherein, the gate 10, the first The insulating layer 30, the active layer 40, and the data line layer 50 form a thin film transistor, the gate line 12 is used to provide a turn-on signal to the thin film transistor, and the data line 501 is used to provide a data signal to the pixel electrode 60; wherein the pixel electrode 60 is also A transparent conductive layer is provided on the same layer as the data line layer 50 and is electrically connected to the drain electrode 503 . In order to make the electric field between the common electrode layer 20 and the pixel electrode 60 act on the liquid crystal between the array substrate and the color filter substrate, the pixel electrode 60 is generally designed as a planar hollow structure, as shown in FIG. 3 . In addition, in terms of technology, the data line layer 50 can be formed first through a patterning process, and then the pixel electrode layer 60 can be formed, or the pixel electrode layer 60 can be formed through a patterning process, and then the data line layer 50 can be formed. The patterning process mentioned here mainly includes forming film, exposure and etching processes.

The array substrate further includes a protective layer 70 disposed above the thin film transistor and the pixel electrode 60, and the protective layer 70 is used to protect the thin film transistor from being corroded. The display panel further includes a black matrix 80 disposed on the color filter substrate 200, and the black matrix 80 is used to block light leakage areas. The area bounded by the dotted line AA' and the dotted line BB' is the thin film transistor area (or called the non-display area of the pixel unit, referred to as the non-display area for short), and the area bounded by the dotted line BB' and the dotted line CC' is the display area of the pixel unit ( referred to as the display area).

In the prior art, since the metal layer 11 and the gate 10 are arranged on the same layer and are made of the same material, the materials used are generally Cr, W, Ti, Ta, Mo, Al, Cu and other metals and their alloys, so that the metal After the layer 11 is connected in parallel with the common electrode layer 20, the resistance of the common electrode layer 20 can be reduced to a certain extent, but due to the restriction of the width d1 of the black matrix 80 on the color filter substrate, and in order to prevent the A short circuit occurs, and the distance between the metal layer 11 and the gate 10 is about 5 micrometers (um), so the width d2 of the metal layer 11 is very limited, so the effect on reducing the resistance of the common electrode layer 20 is not very obvious, However, reducing the resistance of the common electrode layer 20 by increasing the length of d2 will cause d2 to enter the interior of BB′-CC′, resulting in a decrease in the pixel aperture ratio.

Contents of the invention

Embodiments of the present invention provide an array substrate, a manufacturing method thereof, and a display panel, which are used to reduce the voltage difference of the common electrode layer between different pixel units and increase the aperture ratio of the pixel at the same time.

The array substrate provided by the embodiment of the present invention includes: a base substrate, gate lines arranged crosswise on the base substrate, data lines, and pixel units arranged in a matrix divided by the gate lines and data lines, the The pixel unit is provided with a thin film transistor, a pixel electrode and a common electrode layer, the thin film transistor includes a gate, a first insulating layer, an active layer, a source and a drain, and the array substrate further includes:

a conductive black matrix disposed in the non-display area of the pixel unit, the black matrix is electrically connected to the common electrode layer; and,

A second insulating layer is used to insulate the black matrix and the common electrode layer from the thin film transistor, and the covering area of the second insulating layer overlaps with the covering area of the black matrix and the common electrode layer.

In the array substrate, a conductive black matrix is provided, and the black matrix is electrically connected to the common electrode layer, and the resistance of the black matrix in the electrically connected part is connected in parallel with the resistance of the common electrode layer, so that the total resistance after parallel connection is smaller than the common electrode layer. The resistance of the electrode layer effectively reduces the resistance value of the common electrode layer, thereby reducing the voltage difference of the common electrode layer between different pixel units; at the same time, since the black matrix is arranged on the array substrate, there is no need to consider the accuracy error of the box , and, the array substrate is provided with a second insulating layer for insulating the grid from the black matrix and the common electrode, so there is no need to set a larger separation distance between the common electrode and the grid, Therefore, the width of the black matrix in the array substrate is smaller than the width of the black matrix in the prior art, which is beneficial to increase the aperture ratio of the pixel unit.

Preferably, the black matrix is arranged between the thin film transistor and the base substrate, and the second insulating layer is arranged between the thin film transistor and the black matrix, which can effectively block the light from the backlight from reaching the active layer, which is beneficial to Dark current in thin film transistors is reduced. In addition, the black matrix can also be arranged above the thin film transistor, and the second insulating layer is arranged between the black matrix and the thin film transistor.

Preferably, the material of the black matrix is a non-transparent metal material; the black matrix made of the non-transparent metal material can have a conductive function and a light-shielding function at the same time, and the resistance of the metal material is much smaller than that of the transparent metal material used to make the common electrode layer. The resistance of the conductive material, after the two are connected in parallel, makes the parallel resistance after parallel connection much smaller than the resistance of the common electrode layer, which can effectively reduce the voltage difference caused by the resistance value of the common electrode layer.

Preferably, the black matrix is located above the common electrode layer, or the black matrix is located below the common electrode layer, so that the black matrix and the common electrode layer are electrically connected.

Preferably, the covered area of the electrical connection between the black matrix and the common electrode layer does not overlap with the covered area of the gate, so as to prevent the formation of coupling capacitance between the common electrode layer and the gate, so as to avoid affect the performance of thin film transistors.

Preferably, the array substrate further includes a passivation layer, the passivation layer is arranged above the layer where the thin film transistor is located, covering the upper area of the thin film transistor and the pixel electrode, and the passivation layer is mainly used for Protect thin film transistors from corrosion.

Preferably, the gate, the first insulating layer, the active layer, the source electrode and the drain electrode, and the pixel electrode are sequentially formed on the second insulating layer;

Alternatively, the source electrode, the drain electrode, the pixel electrode, the active layer, the first insulating layer, and the gate are sequentially formed on the second insulating layer;

The source electrode, the drain electrode and the pixel electrode are arranged in the same layer in the array substrate, so that the drain electrode and the pixel electrode are directly electrically connected, which is beneficial to reduce the manufacturing process.

An embodiment of the present invention provides a display device, which includes the above-mentioned array substrate.

An embodiment of the present invention provides a preparation method of an array substrate, the preparation method comprising:

forming a pattern comprising a common electrode layer and a conductive black matrix on the base substrate, the black matrix is electrically connected to the common electrode layer, and the black matrix is arranged in a non-display area of the pixel unit;

A second insulating layer is formed on the base substrate, the covered area of the second insulating layer overlaps with the covered area of the black matrix and the common electrode layer, and is used to connect the black matrix and the common electrode layer with the described TFT insulation;

Patterns including thin film transistors and pixel electrodes are formed on the base substrate.

The array substrate prepared by the method includes a conductive black matrix disposed above the base substrate, the black matrix is electrically connected to the common electrode layer, and the resistance of the electrically connected part of the black matrix is connected to the common electrode layer. The resistors are connected in parallel, so that the total resistance after parallel connection is smaller than the resistance of the common electrode layer, which effectively reduces the resistance value of the common electrode layer, thereby reducing the voltage difference of the common electrode layer between different pixel units; at the same time, due to the black The matrix is arranged on the array substrate, and there is no need to consider the accuracy error of the box, and the second insulating layer is arranged in the array substrate to insulate the gate from the black matrix and the common electrode, so there is no need for a common The distance between the electrode and the grid is relatively large, so the width of the black matrix is smaller than that in the prior art, which is beneficial to improve the aperture ratio of the pixel unit.

Preferably, the black matrix is arranged between the thin film transistor and the base substrate, the second insulating layer is arranged between the thin film transistor and the black matrix, and the black matrix and the common electrode layer are formed on the base substrate. graphics, including:

forming a pattern including a black matrix on the base substrate; forming a pattern including a common electrode layer above the pattern including a black matrix;

Or, forming a pattern including a common electrode layer on the base substrate; forming a pattern including a black matrix above the pattern including a common electrode layer;

Wherein, the black matrix covers the non-display area of each pixel unit.

In the process of forming the pattern including the black matrix and the common electrode layer, both the black matrix and the common electrode layer can be formed first, as long as the electrical connection between the black matrix and the common electrode layer is guaranteed; wherein, the black matrix covers The non-display area of each pixel unit is used to prevent the transmission of light in the non-display area, which is beneficial to reduce the dark current in the thin film transistor.

Preferably, a pattern comprising thin film transistors and pixel electrodes is formed on the base substrate, specifically including:

A pattern including gates and gate lines is formed on the second insulating layer;

forming a first insulating layer above the pattern including the gate and the gate line;

forming a pattern including an active layer over the first insulating layer;

A pattern including a source electrode, a drain electrode and a pixel electrode is formed above the pattern including an active layer.

Alternatively, forming a pattern including a thin film transistor and a pixel electrode on the second insulating layer, specifically including:

A pattern including a source electrode, a drain electrode and a pixel electrode is formed on the second insulating layer;

forming a pattern including an active layer above the pattern including a source electrode, a drain electrode and a pixel electrode;

forming a first insulating layer over the pattern including the active layer;

A pattern including a gate and a gate line is formed on the first insulating layer.

In the process of forming the thin film transistor and the pixel electrode, a pattern including the source, the drain and the pixel electrode is formed on the same layer, so that the drain and the pixel electrode are directly electrically connected, which is beneficial to reduce the manufacturing process.

Preferably, the method further includes: forming a passivation layer above the pattern including the thin film transistor and the pixel electrode, and the passivation layer covers the upper area of the thin film transistor and the pixel electrode to prevent the thin film transistor from Corroded.

Description of drawings

FIG. 1 is a schematic cross-sectional structure diagram of a display panel in the prior art;

FIG. 2 is a schematic plan view of the structure of the display panel shown in FIG. 1;

3 is a plan view of a pixel electrode;

FIG. 4 is a schematic cross-sectional structure diagram of an array substrate provided in Embodiment 1 of the present invention;

FIG. 5 is a schematic plan view of the array substrate shown in FIG. 4;

6 is a schematic cross-sectional structure diagram of an array substrate provided by Embodiment 2 of the present invention;

7 is a schematic cross-sectional structure diagram of an array substrate provided by Embodiment 3 of the present invention;

FIG. 8 is a schematic cross-sectional structure diagram of an array substrate provided in Embodiment 4 of the present invention;

FIG. 9 is a schematic cross-sectional structure diagram of an array substrate after the fabrication of a black matrix and a common electrode layer;

10 is a schematic cross-sectional structure diagram of the array substrate after the second insulating layer is fabricated;

FIG. 11 is a schematic cross-sectional structure diagram of an array substrate on which thin film transistors are fabricated;

12 is a schematic cross-sectional structure diagram of an array substrate on which pixel electrodes are fabricated;

FIG. 13 is a schematic cross-sectional structure diagram of the array substrate after the black matrix and the common electrode layer are fabricated during the process of preparing the array substrate provided in the second embodiment.

Detailed ways

Embodiments of the present invention provide an array substrate, a manufacturing method thereof, and a display panel, which are used to reduce the voltage difference of the common electrode layer between different pixel units and increase the aperture ratio of the pixel at the same time.

The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

Embodiment 1 of the present invention provides an array substrate, see FIG. 4 and FIG. 5 , wherein FIG. 4 is a schematic cross-sectional structure diagram of the array substrate provided in Embodiment 1 of the present invention, and FIG. 5 is a schematic plan view of the array substrate shown in FIG. 4 . 4 and 5, it can be seen that the array substrate includes: a base substrate 1001, a black matrix 80, a common electrode layer 20, a second insulating layer 90, a gate 10, a gate line 12, a first insulating layer 30, Active layer 40, data line layer 50 (specifically including: data line 501, source electrode 502, drain electrode 503) and pixel electrode 60;

Specifically, the black matrix 80 is located above the base substrate 1001, the material of the black matrix is a non-transparent metal material, and the black matrix made of a non-transparent metal material can have a conductive function and a light-shielding function at the same time, And the resistance of the metal material is much smaller than the resistance of other non-transparent conductive materials used.

The width of the black matrix 80 is d3, which covers the non-display area of each pixel unit and is used to prevent the transmission of light in the non-display area; since the black matrix 80 is arranged on the array substrate, it is necessary to design the black matrix When it is 80, there is no need to consider the accuracy error of the box alignment, which is beneficial to reduce the size of the black matrix and increase the aperture ratio of the pixel;

In addition, the black matrix 80 can also cover the channel region of the active layer 40 , so that all the light irradiated on the active layer 40 is covered, thereby reducing the leakage current of the active layer.

The common electrode layer 20 is located above the layer where the black matrix 80 is located, and is electrically connected to the black matrix 80. The material of the common electrode layer 20 is generally transparent, such as indium tin oxide, indium zinc oxide, or aluminum zinc oxide. oxide.

The width of the electrical connection portion between the black matrix 80 and the common electrode layer 20 is d4, and the coverage area of the electrical connection portion does not overlap with the coverage area of the gate 10, which is used to prevent the common electrode layer 20 from A coupling capacitor is formed with the gate 10 so as not to affect the performance of the thin film transistor. The coverage area referred to herein refers to the projected area of related structures (such as the electrical connection portion or gate between the black matrix and the common electrode layer) on the base substrate.

At the electrical connection part between the black matrix 80 and the common electrode layer 20, the resistance of the black matrix in the electrical connection part is connected in parallel with the resistance of the common electrode layer 20, because the resistance value of the electrical connection part is much smaller than the The resistance of the common electrode layer 20 , therefore, the resistance value of the total resistance after parallel connection is much smaller than the resistance value of the common electrode layer 20 , thereby reducing the voltage difference caused by the resistance of the common electrode layer 20 .

The second insulating layer 90 is disposed between the layer where the common electrode layer 20 is located and the layer where the gate 10 and the gate line 12 are located, and the covered area of the second insulating layer is compatible with the black matrix and the The coverage area of the common electrode layer overlaps, that is, the second insulating layer covers the upper area of the black matrix 80 and the common electrode layer 20, and is used to connect the gate 10 of the thin film transistor to the black matrix 80 and The common electrode layer 20 is insulated. Therefore, in the array substrate, there is no need to consider the distance between the common electrode layer 20 and the gate lines 10 . It is beneficial to further reduce the size of the black matrix and increase the aperture ratio of the pixel.

The gate 10 and the gate line 12 are arranged on the same layer, both are located between the first insulating layer 30 and the second insulating layer 90, and the gate 10 and the gate line 12 are made of the same material, and the used The production materials are generally Cr, W, Ti, Ta, Mo, Al, Cu and other opaque metals and their alloys.

The first insulating layer 30 is located above the gate 10 and the gate line 12, covering the area above the gate 10 and the gate line 12; in this embodiment, the material for making the first insulating layer 30 is The thickness of the photoresist is about 20,000 angstroms. At the same time, the first insulating layer 30 can also use other insulating layer materials, and the thickness should be determined according to actual needs.

The active layer 40 is located above the first insulating layer 30;

The data line 501, the source electrode 502 and the drain electrode 503 are arranged in the same layer, located above the layer where the active layer 40 is located, and made of the same material;

The data line 501 is electrically connected to the source electrode 502 and intersects with the gate line 12;

The source 502 and the drain 503 are located on opposite sides above the active layer 40 .

The pixel electrode 60 is set on the same layer as the data line 501, the source electrode 502, and the drain electrode 503, and the pixel electrode 60 is electrically connected to the drain electrode 503. The pixel electrode is generally made of indium tin oxide, indium oxide Made of transparent oxide materials such as zinc or aluminum zinc oxide, the pixel electrodes are in the shape of slits.

The array substrate also includes a passivation layer 70 located above the data line 501, the source electrode 502 and the drain electrode 503, the passivation layer 70 is used to protect the thin film transistor from being corroded; the passivation layer 70 is made of nitrogen Formed of transparent insulating materials such as silicon oxide or silicon oxide.

In order to better explain the influence of this design scheme on the aperture ratio of TFT pixels and the gate lines and data lines, the pixel units in the display panel shown in Figure 2 and the pixel units in the array substrate shown in Figure 5 are now used as Example to illustrate:

FIG. 2 is a schematic diagram of a pixel unit structure in a display panel designed in the prior art. Please refer to Table 1 for the material and film thickness data of each layer of thin film;

The material and film thickness data of each layer thin film in the prior art of table 1

FIG. 5 is a schematic diagram of the planar structure of the pixel unit in the array substrate provided by Embodiment 1 of the present invention. For specific material and film thickness data of each layer of thin film, please refer to Table 2;

Table 2 The material and film thickness data of each layer of thin film in the array substrate provided by Embodiment 1 of the present invention

2 and 5 are both 5.2-inch pixel structure diagrams with a resolution of 480×272, the pixel unit size is 80×240um, the gate line 12 has a line width of 6um, and the data line 501 has a line width of 4um.

After calculation, the gate line resistance and the data line 501 resistance of each pixel unit of the above two designs will not change, and in the pixel unit with the structure shown in Figure 2, the gate line capacitance C _gate =5.91×10 ^-14 F , the data line capacitance C _data =9.56×10 ^-14 F, assuming that the screen scanning frequency is 60Hz and the pixel charging rate is 99.99%, then the width and length of the thin film transistor in the pixel unit need to be designed to be 16um and 5um respectively;

Assuming that the bonding accuracy of the array substrate and the color filter substrate is 7.5um, in the pixel unit with the structure shown in Figure 5, the gate line capacitance C _gate =3.72×10 ^-13 F, the data line capacitance C _data =2.19×10 ^-13 F, when the screen scanning frequency is 60Hz and the pixel charging rate is 99.99%, the width and length of the thin film transistor in the pixel unit need to be designed to be 17um and 5um respectively.

To sum up, due to the introduction of the black matrix in the pixel unit shown in Figure 5, the gate line capacitance of each pixel unit will increase from the original 5.91×10 ^-14 F to 3.72×10 ^-13 F, each The data line capacitance of a pixel unit increases from the original 9.56×10 ^-14 F to 2.19×10 ^-13 F, and the increase in capacitance will lead to an increase in the delay of the gate line and data line, which in turn will lead to the charging time of each pixel unit Therefore, in the array substrate provided in Embodiment 1, the width and length of the thin film transistors need to be designed to be 17um and 5um respectively to increase the charging current to ensure the normal operation of the pixel unit. show. Although the introduction of the black matrix will increase the capacitance of the gate line and the data line, which will lead to an increase in the width of the thin film transistor (which will result in a decrease in the aperture ratio), but because the black matrix in parallel with the common electrode layer in the pixel unit and The grid line layer is not the same layer design, there is no need to set a large interval between the black matrix and the grid line layer, and there is no need to consider the accuracy error of the box, so the aperture ratio of the pixel unit is increased overall. The aperture ratio of the pixel is increased from 72% to 75.5%.

Embodiment 2 of the present invention also provides an array substrate, the cross-sectional structure of which is shown in Figure 6. It can be seen from Figure 6 that the structure of the array substrate is basically the same as that shown in Figure 4, and the difference between the two is The difference is that: in the array substrate shown in FIG. 4 , the black matrix 80 is located between the base substrate 1001 and the common electrode layer 20 ; while in the array substrate shown in FIG. 6 , the black matrix 80 is located in the second insulating layer 90 and the common electrode layer 20.

Embodiment 3 of the present invention also provides an array substrate, the cross-sectional structure of which is shown in FIG. 7 . It can be seen from FIG. The reason is that the array substrate shown in FIG. 4 is an array substrate with a bottom gate structure, and the array substrate shown in FIG. 7 is an array substrate with a top gate structure. Specifically, in the array substrate shown in FIG. 7 , the data line 501, the source 502 and the drain 503 are located above the second insulating layer 90, the active layer 40 is located above the pattern including the data line 501, the source 502 and the drain 503, the second An insulating layer 30 is located above the active layer 40 , and the gate 10 and gate line 12 are located above the first insulating layer 30 . Moreover, since the pixel electrode 60 is disposed on the same layer as the data line 501, the source electrode 502 and the drain electrode 503, in the array substrate shown in FIG. 7, the pixel electrode 60 is disposed on the first insulating layer 30 and 90 between the second insulating layer.

Embodiment 4 of the present invention also provides an array substrate, the cross-sectional structure of which is shown in FIG. 8. It can be seen from FIG. The difference is: in the array substrate shown in FIG. 7, the black matrix 80 is located between the base substrate 1001 and the common electrode layer 20; and in the array substrate shown in FIG. 8, the black matrix 80 is located between the second insulating layer 90 and the between the common electrode layers 20 .

The array substrates provided in Embodiment 1, Embodiment 2, Embodiment 3 and Embodiment 4 above all include a conductive black matrix disposed above the base substrate, the black matrix is electrically connected to the common electrode layer, and the electrical The resistance of the black matrix of the connection part is connected in parallel with the resistance of the common electrode layer, so that the total resistance of the electrical connection part after parallel connection is smaller than the resistance of the common electrode layer of the electrical connection part, effectively reducing the resistance value of the common electrode layer, thereby reducing The voltage difference of the common electrode layer between different pixel units is reduced; at the same time, since the black matrix is arranged on the array substrate, there is no need to consider the accuracy error of the box, which is conducive to reducing the width of the black matrix and increasing the aperture ratio of the pixel. ; Simultaneously, the array substrate is also provided with a second insulating layer, which is used to insulate the gate from the black matrix and the common electrode, so there is no need to set a larger interval between the common electrode layer and the gate The distance is used to prevent a short circuit between the grid and the common electrode layer, which is beneficial to further reducing the size of the black matrix and increasing the aperture ratio of the pixel.

It should be pointed out that the black matrix can also be arranged above the thin film transistor, specifically, the second insulating layer is arranged above the thin film crystal, the black matrix is arranged above the second insulating layer, and the common The electrode layer is arranged above/below the black matrix and is electrically connected to the black matrix, the passivation layer is arranged above the common electrode layer and the black matrix, and the pixel electrode is arranged on the passivation layer Above, wherein, the pixel electrode is in the shape of a slit, and the common electrode is in the shape of a plate or a slit;

Alternatively, the second insulating layer is arranged above the thin film transistor, the pixel electrode is arranged below the second insulating layer, the common electrode layer is arranged above the thin film transistor, and the black matrix is arranged on the second insulating layer Above, above or below the common electrode layer, and electrically connected to the common electrode layer, the passivation layer is arranged above the black matrix and the common electrode layer; wherein, the common electrode is slit-shaped, The pixel electrodes are plate-shaped or slit-shaped.

Embodiment 5 of the present invention provides a method for preparing an array substrate, the method comprising:

forming a pattern comprising a common electrode layer and a conductive black matrix on the base substrate, the black matrix is electrically connected to the common electrode layer, and the black matrix is arranged in a non-display area of the pixel unit;

Forming a second insulating layer on the base substrate, the covered area of the second insulating layer overlaps with the covered area of the black matrix and the common electrode layer, and is used to connect the black matrix and the common electrode layer with the thin film transistor insulation;

Patterns including thin film transistors and pixel electrodes are formed on the base substrate.

The array substrate prepared by the method includes a conductive black matrix disposed above the base substrate, the black matrix is electrically connected to the common electrode layer, and the resistance of the electrically connected part of the black matrix is connected to the common electrode layer. The resistors are connected in parallel, so that the total resistance after parallel connection is smaller than the resistance of the common electrode layer, which effectively reduces the resistance value of the common electrode layer, thereby reducing the voltage difference of the common electrode layer between different pixel units; at the same time, due to the black The matrix is arranged on the array substrate, and there is no need to consider the accuracy error of the box, and the array substrate is provided with a second insulating layer, which is used to insulate the gate from the black matrix and the common electrode, so there is no need to A larger distance is set between the common electrode and the gate, so the width of the black matrix is smaller than that of the prior art, which is beneficial to improve the aperture ratio of the pixel unit.

Taking the array substrate provided in Embodiment 1 of the present invention as an example, the method for preparing the array substrate in the actual preparation process is described in detail below, and the method specifically includes:

In the first step, referring to FIG. 9 , a pattern including a black matrix 80 and a common electrode layer 20 is formed on the base substrate 1001; specifically, this step includes:

Deposit a layer of non-transparent metal film on the base substrate 1001, and then process it through a patterning process to form a pattern including a black matrix 80, and the black matrix 80 covers the non-display area of each pixel unit; wherein, in this embodiment , the patterning process includes: first, forming (such as sputtering or coating, etc.) a layer of non-transparent metal film for forming a black matrix on the base substrate 1001; then, coating a layer of light on the metal film Resist; Then, the photoresist is exposed with a mask provided with a pattern including a black matrix; finally, a pattern including a black matrix 80 is formed after development and etching. In the preparation method of the array substrate in this embodiment, the preparation process related to the film layer formed by the patterning process is the same as this, and will not be described in detail hereafter.

Above the pattern including the black matrix 80, a layer of indium tin oxide transparent conductive film is deposited by magnetron sputtering, and a pattern including a common electrode layer 20 is formed through a patterning process; the common electrode layer 20 is connected with the The black matrix is electrically connected, and the width of the electrical connection part is d4. Since the interval between the common electrode layer and the grid does not need to be considered, the width d4 of the electrical connection part is greater than that of the metal layer and the common electrode line in the prior art. The width d2 of the electrical connection part.

The second step, referring to FIG. 10 , is to deposit a silicon nitride (SiN _x ) or silicon oxide (SiO _x ) layer on the pattern including the black matrix 80 and the common electrode layer 20 to form a second insulating layer 90, the The second gate insulating layer 90 is used to cover the upper regions of the black matrix 80 and the common electrode layer 20 , and is used to insulate the black matrix 80 and the common electrode layer 20 from the thin film transistors.

The third step, referring to FIG. 11 , is to form a pattern including thin film transistors on the second insulating layer 90, and this step specifically includes:

1. Deposit a metal thin film on the second insulating layer 90, and then process it through a patterning process to form a pattern including the gate 10 and the gate line 12 (see FIG. 5 ), which is used to form the metal thin film The materials used are Cr, W, Ti, Ta, Mo, Al, Cu and other opaque metals and their alloys;

Second, deposit a silicon nitride (SiN _x ) or silicon oxide (SiO _x ) layer on the pattern including the gate 10 and the gate line 12 to form a first insulating layer 30, and the first gate insulating layer 30 is used Covering the upper area of the gate line and the gate, for insulating the gate line and the gate from other layers;

3. Depositing an amorphous silicon semiconductor material on the first insulating layer 30, and then forming a pattern including the active layer 40 through a patterning process;

Fourth, forming a source-drain metal thin film on the pattern including the active layer 40, and then forming a pattern including the data line 501, the source electrode 502 and the drain electrode 503 through a patterning process.

The fourth step, referring to FIG. 12 , is to deposit a layer of transparent conductive film of indium tin oxide on the first insulating layer 30 by magnetron sputtering, and through a patterning process, a pattern including a pixel electrode 60 is formed, and the pixel electrode 60 is disposed on the same layer as the data line 501 , the source electrode 502 and the drain electrode 503 , and the pixel electrode 60 is electrically connected to the drain electrode 503 .

The fifth step, referring to FIG. 4 , is to deposit a silicon nitride or silicon oxide layer on the pattern including the pixel electrode to form a passivation layer 70 for protecting the thin film transistor from being corroded.

After the above steps, the array substrate provided by Embodiment 1 of the present invention with the structure shown in FIG. 4 is formed.

It should be noted that, in the above process of preparing the array substrate, the thin film transistor can be formed first and then the pixel electrode can be formed, or the pixel electrode can be formed first and then the thin film transistor can be formed.

For the array substrate provided in Embodiment 2 of the present invention, its preparation method is similar to the method for preparing the array substrate provided in Embodiment 1 of the present invention. The difference is that, referring to FIG. In the process, the formation of a pattern including a black matrix and a common electrode layer on the base substrate specifically includes:

1) Deposit a layer of indium tin oxide transparent conductive film on the base substrate 1001 by magnetron sputtering, and form a pattern including the common electrode layer 20 through a patterning process;

2) Deposit a layer of non-transparent metal thin film on top of the pattern including the common electrode layer 20, and then process it through a patterning process to form a pattern including a black matrix 80, the black matrix 80 covering the non-transparent Display area;

Wherein, the common electrode layer 20 is electrically connected with the black matrix, and the width of the electrical connection part is d4. Since the interval between the common electrode layer and the grid does not need to be considered, the width d4 of the electrical connection part is larger than the current one. In the prior art, the width d2 of the electrical connection part between the metal layer and the common electrode line;

For the array substrate provided by the third embodiment of the present invention, its preparation method is similar to the method for preparing the array substrate provided by the first embodiment of the present invention, the difference is that, referring to FIG. 7 , the preparation method of the array substrate provided by the third embodiment of the present invention is In the process, the formation of patterns including thin film transistors and pixel electrodes specifically includes:

a), forming a source-drain metal thin film on the second insulating layer 90, and then forming a pattern including a data line 501, a source electrode 502, and a drain electrode 503 through a patterning process;

b) Deposit a layer of indium tin oxide transparent conductive film on the second insulating layer 90 by magnetron sputtering, and form a pattern including the pixel electrode 60 through a patterning process, and the pixel electrode 60 is connected to the data The line 501, the source electrode 502, and the drain electrode 503 are arranged in the same layer, and the pixel electrode 60 is electrically connected to the drain electrode 503;

c) Depositing a semiconductor material above the pattern including the data line 501, the source electrode 502 and the drain electrode 503, and then forming a pattern including the active layer 40 through a patterning process;

d) Depositing a silicon nitride or silicon oxide layer on top of the pattern including the active layer 40 to form a first insulating layer 30, the first gate insulating layer 30 is used to cover the top of the active layer 40 a region for insulating the active layer 40 from other layers;

e) Deposit a metal thin film on the first insulating layer 30, and then process it through a patterning process to form a pattern including the gate 10 and the gate line 12 (see FIG. 4 ). The materials are Cr, W, Ti, Ta, Mo, Al, Cu and other opaque metals and their alloys.

For the array substrate provided in Embodiment 4 of the present invention, its preparation method is similar to the method for preparing the array substrate provided in Embodiment 3 of the present invention. The difference is that, referring to FIG. In the process, the formation of a pattern including a black matrix and a common electrode layer on the base substrate specifically includes:

1) Deposit a layer of indium tin oxide transparent conductive film on the base substrate 1001 by magnetron sputtering, and form a pattern including the common electrode layer 20 through a patterning process;

2) Deposit a layer of non-transparent metal thin film on top of the pattern including the common electrode layer 20, and then process it through a patterning process to form a pattern including a black matrix 80, the black matrix 80 covering the non-transparent Display area;

Wherein, the common electrode layer 20 is electrically connected with the black matrix, and the width of the electrical connection part is d4. Since the interval between the common electrode layer and the grid does not need to be considered, the width d4 of the electrical connection part is larger than the current one. The width d2 of the electrical connection portion between the metal layer and the common electrode line in the prior art.

It should be pointed out that in the present invention, the patterning process may only include a photolithography process, or may include a photolithography process and an etching step, and may also include other processes for forming predetermined patterns such as printing and inkjet. ; Photolithography process refers to the process of forming patterns by using photoresist, mask plate, exposure machine, etc., including film formation, exposure, development and other processes. The corresponding patterning process can be selected according to the structure formed in the present invention.

In addition, for the array substrate in which the black matrix, the common electrode layer and the second insulating layer are all arranged above the thin film transistor, the manufacturing method includes:

A pattern comprising a thin film transistor is formed on the base substrate, a second insulating layer and a pattern comprising a common electrode layer and a black matrix are sequentially formed above the pattern comprising a thin film transistor, and a pattern comprising a common electrode layer and a black matrix is sequentially formed on the pattern comprising a common electrode layer and a black matrix A passivation layer is formed above the pattern, and a pattern including a pixel electrode is formed above the passivation layer, wherein the pixel electrode is in the shape of a slit, and the common electrode layer is in the shape of a plate or a slit;

Alternatively, a pattern including a thin film transistor is formed on the base substrate, a pattern including a pixel electrode and a second insulating layer are sequentially formed above the pattern including a thin film transistor, and a pattern including a common electrode is formed above the second insulating layer. A passivation layer is formed above the pattern including the common electrode layer and the black matrix, wherein the pixel electrode is in the shape of a slit or a plate, and the common electrode layer is in the shape of a slit.

To sum up, the array substrate provided by the embodiment of the present invention includes a conductive black matrix disposed above the base substrate, the black matrix is electrically connected to the common electrode layer, and the resistance of the electrically connected part of the black matrix is connected to the common electrode layer. The resistance of the layers is connected in parallel, so that the total resistance of the electrical connection part after parallel connection is smaller than the resistance of the common electrode layer of the electrical connection part, which effectively reduces the resistance value of the common electrode layer, thereby reducing the resistance of the common electrode layer between different pixel units. At the same time, since the black matrix is arranged on the array substrate, there is no need to consider the accuracy error of the box, which is conducive to reducing the width of the black matrix and improving the aperture ratio of the pixel; at the same time, the array substrate is also provided with The second insulating layer is used to insulate the gate from the black matrix and the common electrode, so there is no need to set a larger separation distance between the common electrode layer and the gate to prevent the gate from contacting the common electrode layer. Short circuit is beneficial to further reduce the size of the black matrix and increase the aperture ratio of the pixel.

Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalent technologies, the present invention also intends to include these modifications and variations.

Claims (15)

1. An array substrate, the array substrate comprising a base substrate, gate lines arranged crosswise on the base substrate, data lines, and pixel units arranged in a matrix divided by the gate lines and data lines, The pixel unit is provided with a thin film transistor, a pixel electrode and a common electrode layer, and the thin film transistor includes a gate, a first insulating layer, an active layer, a source electrode and a drain electrode, and it is characterized in that the array substrate also includes : a conductive black matrix disposed in the non-display area of the pixel unit, the black matrix is electrically connected to the common electrode layer; and, A second insulating layer is used to insulate the black matrix and the common electrode layer from the thin film transistor, and the covering area of the second insulating layer overlaps with the covering area of the black matrix and the common electrode layer. 2. The array substrate according to claim 1, wherein the black matrix is arranged between the thin film transistor and the base substrate, and the second insulating layer is arranged between the thin film transistor and the between black matrices. 3. The array substrate according to claim 1, wherein the black matrix is disposed above the thin film transistor, and the second insulating layer is disposed between the black matrix and the thin film transistor. 4. The array substrate according to claim 2, wherein the material of the black matrix is a non-transparent metal material. 5. The array substrate according to claim 2, wherein the black matrix is located above the common electrode layer, or the black matrix is located below the common electrode layer. 6 . The array substrate according to claim 2 , wherein a covered area of the electrical connection portion between the black matrix and the common electrode layer does not overlap with a covered area of the gate. 7. The array substrate according to claim 1, wherein the array substrate further comprises a passivation layer, the passivation layer is arranged above the layer where the thin film transistor is located, covering the thin film transistor and the pixel electrode the upper area of . 8. The array substrate according to claim 7, wherein the gate, the first insulating layer, the active layer, the source and drain and the pixel electrode. 9. The array substrate according to claim 7, wherein the source electrode, the drain electrode, the pixel electrode, the active layer, and the first insulating layer are sequentially formed on the second insulating layer. layer, the gate. 10. A display device, characterized in that the display device comprises the array substrate according to any one of claims 1-9. 11. A preparation method for an array substrate, characterized in that the preparation method comprises: forming a pattern comprising a common electrode layer and a conductive black matrix on the base substrate, the black matrix is electrically connected to the common electrode layer, and the black matrix is arranged in a non-display area of the pixel unit; A second insulating layer is formed on the base substrate, the covered area of the second insulating layer overlaps with the covered area of the black matrix and the common electrode layer, and is used to connect the black matrix and the common electrode layer with the described TFT insulation; Patterns including thin film transistors and pixel electrodes are formed on the base substrate. 12. The preparation method according to claim 11, wherein the black matrix is arranged between the thin film transistor and the base substrate, and the second insulating layer is arranged between the thin film transistor and the Between the black matrix, the formation of a pattern comprising a black matrix and a common electrode layer on the base substrate specifically includes: forming a pattern including a black matrix on the base substrate; forming a pattern including a common electrode layer above the pattern including a black matrix; Or, forming a pattern including a common electrode layer on the base substrate; forming a pattern including a black matrix above the pattern including a common electrode layer; Wherein, the black matrix covers the non-display area of each pixel unit. 13. The preparation method according to claim 12, wherein a pattern comprising a thin film transistor and a pixel electrode is formed on the base substrate, specifically comprising: A pattern including a gate and a gate line is formed on the second insulating layer; forming a first insulating layer above the pattern including the gate and the gate line; forming a pattern including an active layer over the first insulating layer; A pattern including a source electrode, a drain electrode and a pixel electrode is formed above the pattern including an active layer. 14. The preparation method according to claim 12, wherein a pattern comprising a thin film transistor and a pixel electrode is formed on the base substrate, specifically comprising: A pattern including a source electrode, a drain electrode and a pixel electrode is formed on the second insulating layer; forming a pattern including an active layer above the pattern including a source electrode, a drain electrode and a pixel electrode; forming a first insulating layer over the pattern including the active layer; A pattern including a gate and a gate line is formed on the first insulating layer. 15. preparation method as claimed in claim 12, is characterized in that, described method also comprises: A passivation layer is formed above the pattern including the thin film transistor and the pixel electrode, and the passivation layer covers the upper region of the thin film transistor and the pixel electrode.

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