CN103500797B - Random access memory unit and manufacture method thereof - Google Patents

Abstract

Disclosed are a resistance variable memory unit and a manufacturing method thereof. The resistive memory cell includes: a bottom electrode; a top electrode; and a resistive material stack between the bottom electrode and the top electrode, wherein the resistive material stack includes different resistive materials that are in direct contact with each other. At least two layers. The resistive variable memory unit can be used for non-volatile memory with high switch resistance ratio and high stability.

Description

Resistive memory cell and manufacturing method thereof

technical field

The invention belongs to the technical field of microelectronics, and in particular relates to a resistance variable memory unit and a manufacturing method thereof.

Background technique

Non-volatile memory has the characteristic of long-term preservation of internal storage data after power failure, making it widely used in various handheld terminal communication and multimedia equipment. At present, the mainstream non-volatile memory in the market is Flash memory. Flash memory has the advantages of simple structure, high storage density, electrical erasability, reprogrammability, low cost, high erasing speed and high reliability. There are obvious defects and problems in Flash memory. On the one hand, due to the high writing voltage of the Flash memory, the reading and writing speed is slow (reading and writing/erasing time: 1ms/0.1ms), and the erasable times are relatively low > 10 ⁵ times. On the other hand, the basic principle of Flash memory is to use floating gate charge storage technology to change the threshold characteristics of MOS transistors to realize data storage. Further reduction in size will lead to the corresponding gate insulating layer thickness being too small, resulting in the gradual emergence of electron tunneling effect and leakage current. increases sharply, thus affecting the stability of the device.

At present, the new non-volatile memory that is most likely to replace the traditional Flash memory mainly includes: ferroelectric memory (FRAM), magnetic memory (MRAM), phase change memory (PRAM) and resistive memory (RRAM). Resistive RAM (RRAM) is developed based on the transition effect of resistance of some oxide materials induced by DC voltage or pulse voltage.

RRAM typically includes a bottom electrode, a top electrode, and a layer of resistive switching material sandwiched between the two electrodes. Resistive switching materials are generally transition metal oxides, such as HfO ₂ , NiO, TiO ₂ , ZrO ₂ , ZnO, MgO, WO ₃ , Ta ₂ O ₅ , Al ₂ O ₃ , MoO _x , CeO _x , La ₂ O ₃ , Pr _0.7 Ca _0.3 MnO ₃ , La _1-x Ca _x MnO ₃ , etc., and can be doped with elements such as Al, Gd, La, Sr, Ti, etc. Resistive switching materials can exhibit two stable states, namely high resistance state and low resistance state, corresponding to the numbers "0" and "1" respectively. RRAM uses voltage pulses to change the resistance state of the resistive material and keeps the resistance state unchanged after power is turned off. RRAM has the advantages of simple structure, high storage density, fast read and write speed, stable information, low power consumption, non-volatility, and easy to realize three-dimensional integration and multi-value storage.

However, it is desired to further improve the resistance transition characteristics of RRAM for good application prospects.

Contents of the invention

The object of the present invention is to provide a resistive variable memory unit with high switch resistance ratio and high stability and a manufacturing method thereof.

According to an aspect of the present invention, there is provided a resistive variable memory unit, comprising: a bottom electrode; a top electrode; and a resistive material stack between the bottom electrode and the top electrode, wherein the resistive material stack includes different At least two layers composed of resistive material and in direct contact.

According to another aspect of the present invention, there is provided a method for manufacturing a resistive variable memory unit, including: forming a bottom electrode; forming a resistive material stack on the bottom electrode, the resistive material stack comprising , and at least two layers in direct contact; and forming a top electrode on the resistive material stack.

Preferably, one of said at least two layers consists of a binary metal oxide.

Preferably, the other of said at least two layers consists of perovskite oxide.

Preferably, the binary metal oxide includes any of the following: HfO ₂ , NiO, TiO ₂ , ZrO ₂ , ZnO, MgO, WO ₃ , Ta ₂ O ₅ , Al ₂ O ₃ , MoO _x , CeO _x , La ₂ O ₃ and any combination thereof, wherein x=0-1.

Preferably, the perovskite oxide includes any one of the following: Pr _0.7 Ca _0.3 MnO ₃ , La _1-x Ca _x MnO ₃ and any combination thereof, wherein x=0-1.

The memory cell exhibits two resistive states.

The advantages of the present invention are:

According to the resistive switching memory unit of the present invention, a composite resistive switching material layer is used instead of a single layer of resistive switching material layer. Due to the interface effect of the two layers of resistive switching materials, the leakage current of the device is reduced, and the resistance switching performance of the device is improved. stability. The resistive variable memory unit exhibits excellent transition characteristics between high and low resistance states, exhibits two resistance states, and the difference between the high and low resistance states can be greater than 10 ⁴ times. The difference is stable after multiple transitions of the resistive memory unit, and compared with the resistive memory with a single resistive material layer, the writing performance and erasable times are improved, and the service life of the memory is prolonged. The resistive memory unit also reduces the resistance transition voltage, thereby reducing the power consumption of the device. In a preferred embodiment, the composite film has good light transmittance to visible light and can be applied to non-volatile transparent memory.

Thin films can be prepared by magnetron sputtering, pulsed laser deposition and other preparation methods, which have broad development space and market prospects.

Description of drawings

FIG. 1 is a schematic structural diagram of a resistive memory cell according to an embodiment of the present invention.

FIG. 2 is an I-V characteristic diagram of a resistive memory cell according to an embodiment of the present invention.

FIG. 3 is a graph showing the variation of the resistance values of the resistive variable memory unit in the high resistance state and the low resistance state with the number of switching cycles according to an embodiment of the present invention.

FIG. 4 is the transmittance to visible light of a resistive memory cell according to an embodiment of the present invention.

detailed description

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings. For the sake of clarity, various parts in the drawings have not been drawn to scale.

It should be understood that when describing the structure of a device, when a layer or a region is referred to as being "on" or "over" another layer or another region, it may mean being directly on another layer or another region, or Other layers or regions are also included between it and another layer or another region. And, if the device is turned over, the layer, one region, will be "below" or "beneath" the other layer, another region. If it is to describe the situation directly on another layer or another area, the expression "directly on" or "on and adjacent to" will be used herein.

In the following, many specific details of the present invention are described, such as device structures, materials, dimensions, processing techniques and techniques, for a clearer understanding of the present invention. However, the invention may be practiced without these specific details, as will be understood by those skilled in the art. Unless otherwise noted below, various parts of the memory cell may be constructed of materials known to those skilled in the art. The invention can be embodied in various forms, some examples of which are described below.

FIG. 1 is a schematic structural diagram of a resistive memory cell 100 according to an embodiment of the present invention. The resistive memory cell 100 includes a substrate 101, a bottom electrode 102 on the substrate 101, a first resistive material layer 103 on the bottom electrode 102, and a second resistive material layer on the first resistive material layer 103. 104 , and the top electrode 105 located on the second resistive material layer 104 .

The substrate 101 can be a transparent flexible or non-flexible substrate, such as polyethylene terephthalate (PET) and glass.

The bottom electrode 102 can be a transparent conductive oxide ITO or FTO film with a thickness of 100-200 nanometers.

The first resistive material layer 103 and the second resistive material layer 104 may be composed of binary metal oxide and perovskite oxide respectively. The binary metal oxide includes any of the following: HfO ₂ , NiO, TiO ₂ , ZrO ₂ , ZnO, MgO, WO ₃ , Ta ₂ O ₅ , Al ₂ O ₃ , MoO _x , CeO _x , La ₂ O ₃ and any combination thereof, where x=0-1. The perovskite oxide includes any one of the following: Pr _0.7 Ca _0.3 MnO ₃ , La _1-x Ca _x MnO ₃ and any combination thereof, wherein x=0-1.

In one example, the first resistive material layer 103 may be composed of ZnO or MgO with a thickness of 50-100 nanometers. The second resistive material layer 104 may be composed of Pr _0.7 Ca _0.3 MnO ₃ with a thickness of 50-200 nm.

The top electrode 105 can be a transparent conductive oxide ITO or FTO film with a thickness of 100-200 nm.

In a preferred embodiment, layers 101 - 105 are all transparent, so that together they form a transparent resistive memory cell 100 . However, it should be understood that any one or more of the layers 101-105 may be non-transparent and still be applicable to resistive random access memory. In addition, the resistive switch material stack includes a first resistive switch material layer 103 and a second resistive switch material layer 104 in direct contact. However, it should be understood that the resistive switch material stack may also include more resistive switch material layers.

According to a preferred embodiment, the method for manufacturing the resistive memory cell 100 according to the embodiment of the present invention includes the following steps.

A transparent flexible or non-flexible material is used as the substrate 101 . The used substrate 101 was ultrasonically cleaned three times with alcohol, ten minutes each time, and finally cleaned with deionized water.

Then, a bottom electrode 102 is formed on the substrate 101 . The bottom electrode 102 can be prepared by laser pulse deposition. The background vacuum of the deposition chamber must be higher than 10 ^-4 Pa, the oxygen pressure is 5Pa-10Pa, the deposition temperature is room temperature, the energy during deposition is 100mJ-400mJ, and the pulse number is 100-3000 pulses. The bottom electrode 102 is, for example, a conductive oxide film with a thickness of 100 nm˜200 nm.

Then, a first resistive material layer 103 is formed on the bottom electrode 102 . The first resistive material layer 103 can be prepared by pulsed laser deposition. The background vacuum of the deposition chamber must be higher than 10 ^-4 Pa, the oxygen pressure is 1Pa-10Pa, the deposition temperature is room temperature, the energy during deposition is 100mJ-400mJ, and the pulse number is 100-3000 pulses. The first resistive material layer 103 is, for example, a binary metal oxide thin film with a thickness of 50 nm˜100 nm.

Then, a second resistive material layer 104 is formed on the first resistive material layer 103 . The second resistive material layer 104 can be prepared by pulsed laser deposition. The background vacuum of the deposition chamber must be higher than 10 ^-4 Pa, the oxygen pressure during sputtering is 5-20Pa, the deposition temperature is room temperature, the energy during deposition is 100mJ-400mJ, and the pulse number is 100-3000 pulses. The second resistive material layer 104 is, for example, a Pr _0.7 Ca _0.3 MnO ₃ film with a thickness of 50-200 nm.

Then, a top electrode 105 is formed on the second resistive material layer 104 . The preparation method of the top electrode 105 may be magnetron sputtering. The background vacuum of the sputtering chamber must be higher than 10 ^-5 Pa, the sputtering temperature is room temperature, and the sputtering pressure is 0.1-1Pa. The top electrode 105 is, for example, an ITO film with a thickness of 1000-200 nm.

In one example, the bottom electrode 102 (zinc oxide thin film) is deposited on the substrate 101 (ITO/glass) using pulsed laser deposition. When the background vacuum of the deposition chamber is 5×10 ^-4 Pa, oxygen is introduced to make the deposition chamber reach the working pressure of 10 Pa, the deposition temperature is room temperature, the energy during deposition is 300mJ, and the pulse number is 3000 pulses, thus forming the first resistive switch The material layer 103 (zinc oxide thin film) has a thickness of 80 nm. Then, the second resistive material layer 104 (Pr _0.7 Ca _0.3 MnO ₃ thin film) was further deposited by pulsed laser, the deposition pressure was 10 Pa, the deposition temperature was room temperature, the deposition energy was 300 mJ, and the pulse number was 4000 pulses. The thickness of the second resistive material layer 104 is 100 nm. Then, a top electrode 105 (ITO thin film) is formed on the second resistive material layer 104 by using magnetron sputtering and masking method. The top electrode 105 has, for example, a circular shape with a diameter of 0.2 mm and a thickness of 200 nm.

FIG. 2 is an I-V characteristic diagram of the resistive memory cell 100 manufactured by the method of the above example. When the scanning voltage is -2.2V, the memory cell changes from high resistance to low resistance; when the scanning voltage is 2V, the memory cell changes from low resistance to high resistance, and the absolute value of the transition voltage is around 2V, which greatly reduces the power consumption.

FIG. 3 shows the variation of the resistance values (respectively denoted as R _H and _RL ) in the high resistance state and low resistance state of the RRAM cell 100 manufactured by the method of the above example with the number of switching cycles. It can be seen from this figure that the high switch resistance ratio of this new type of resistive memory can be greater than 10 ⁴ times under continuous scanning of DC voltage. In the process of 250 consecutive cycles of high and low resistance values, the high and low resistance values still show good stability. Therefore, compared with the resistive memory with a single resistive material layer, both the write performance and the erasable times are significantly improved.

FIG. 4 shows the transmittance to visible light of the resistive memory cell 100 manufactured by the method of the above example. It can be seen from this figure that the light transmittance of the storage unit can reach up to 84.6% under visible light with a wavelength of 590nm, and the average light transmittance is 80.6% under visible light with a wavelength of 450-750nm, which has good light transmittance. Therefore, the present invention has potential application value in non-volatile transparent memory.

The foregoing embodiments are only examples of the present invention. Although the embodiments of the present invention and the accompanying drawings are disclosed for the purpose of illustration, those skilled in the art can understand that: without departing from the spirit and scope of the present invention and the appended claims, Various alternatives, changes and modifications are possible. Therefore, the present invention should not be limited to what is disclosed in the embodiments and drawings.

Claims (4)

1. a random access memory unit, including:

Transparent flexible substrate；

It is positioned at the hearth electrode on transparent flexible substrate；

The resistive material laminate being positioned on hearth electrode；And

It is positioned at the top electrode on resistive material laminate,

Wherein said resistive material laminate includes being made up of different resistive materials and directly contact At least two-layer,

Described hearth electrode and described resistive material laminate all use pulsed laser deposition, described top electrode Employing magnetron sputtering is formed, and described hearth electrode, described resistive material laminate and described top electrode It is transparent,

One layer in described at least two-layer is made up of binary metal oxide, and another layer is by perovskite oxygen Compound forms,

Wherein, the thickness of described a layer in described at least two-layer is 50-100 nanometer, described at least The thickness of another layer described in two-layer is 50-200 nanometer.

Random access memory unit the most according to claim 1, wherein said memory cell table Existing two Resistance states.

3. the method manufacturing random access memory unit, including:

Transparent flexible substrate is formed hearth electrode；

Forming resistive material laminate on hearth electrode, described resistive material laminate includes by different resistives Material composition and at least two-layer directly contacted；And

Resistive material laminate is formed top electrode,

Wherein, described hearth electrode and described resistive material laminate all use pulsed laser deposition, described Top electrode uses magnetron sputtering to be formed, and described hearth electrode, described resistive material laminate and described Top electrode is transparent,

One layer in described at least two-layer is made up of binary metal oxide, and another layer is by perovskite oxygen Compound forms,

The thickness of described a layer in described at least two-layer is 50-100 nanometer, in described at least two-layer The thickness of another layer described be 50-200 nanometer.

Method the most according to claim 3, wherein said memory cell two resistance of performance State.