CN103546232A - Data processing method and device - Google Patents

Abstract

The invention discloses a data processing method and a data processing device. The method includes performing interlaced write-in on to-be-processed data according to a preset sequence, wherein the preset sequence is arranged by taking an output data line order as an input line order; coding the to-be-processed data after being subjected to interlaced write-in and the to-be-processed data according to a preset TURBO coding mode. By applying the data processing method and the data processing device, the problem that processing speed already cannot meet requirements due to low data processing capability when facing a lot of data caused by the fact that a lot of operation needs to be performed on a data output side during data coding is solved, so that operation on an output side is reduced, and processing capability of a system is improved.

Description

Data processing method and device

technical field

The present invention relates to the communication field, in particular, to a data processing method and device.

Background technique

In the field of wireless communication, due to the unstable quality of the communication channel, the bit error rate of transmission is relatively high. In order to reduce the bit error rate, we need a coding method that can automatically correct errors. During the decoding process, it can correctly Restore the transferred data. The TURBO encoding is a very good encoding method, which can repair the received data in the decoding stage very well.

The 3GPP TS 25.212 protocol introduces the TURBO coding method. The specific structure is shown in Figure 1. The overall TURBO coding is mainly composed of two identical coding operation units and an interleaver. The coding rate is 1/3, that is, every received 1-bit data, encoded into 3-bit data. Let's look at the encoding operation unit:

Y(i)=(x(i)+(d2+d3)+d1)+d3;

d1`=x(i)+(d2+d3);

d2`=d1;

d3`=d2;

Among them, Y is the encoded bit, X is the input data, d1, d2, d3 are the status bits in the encoder, d1`, d2`, d3` are the updated encoder status bits after encoding one bit of input data. Among them, the state bit is related to the initial state of the encoder and its processed input value. Therefore, according to the structure of this encoder, at most each clock cycle can only process one data to be encoded.

With the continuous popularization and improvement of wireless networks, wireless services are booming, and some new technologies appear, such as MIMO multi-antenna technology, 64QAM high-order modulation technology, etc., and the coding performance requirements for wireless transmission are also constantly improving. For encoders The processing power is also required to be higher and higher. The current TURBO encoding method is limited by the clock frequency, and the room for performance improvement is very limited. Especially in the field of interference cancellation systems, a large number of users and a large amount of data need to be re-encoded within a very limited period of time, and the performance requirements for encoding are two orders of magnitude higher than those for mobile terminals. higher requirement. However, related technologies need to do a lot of calculations on the data output side. When faced with a lot of data, the data processing capability is low, and the processing speed can no longer meet the requirements. When processing data, only one bit of data can be processed at a time due to the strong bit correlation of the data to be processed.

Contents of the invention

The present invention provides a data processing method and device to at least solve the problem that when coding data in related technologies, a large number of calculations need to be done on the data output side. Processing speed has been unable to meet the requirements of the problem.

According to one aspect of the present invention, a data processing method is provided, including: interleaving and writing the data to be processed according to a predetermined sequence, wherein the predetermined sequence is to set the sequence of output data rows as the sequence of input rows; The data to be processed after the interleaving and writing and the data to be processed are respectively coded in a predetermined TURBO coding manner.

Preferably, after interleaving and writing the data to be processed in a predetermined sequence, the method further includes: storing the data to be processed and the data to be processed after interleaving and writing in the input data buffer space.

Preferably, storing the data to be processed and the data to be processed after interleaving and writing in the input data buffer space includes: obtaining inter-row interleaving addresses and intra-row column interleaving addresses; The data is stored in the input data buffer space in the order of interleaving between rows; the data to be encoded after interleaving and written is stored in the input data buffer space in the order of interleaving in rows and columns according to the interleaving address in the rows.

Preferably, obtaining the inter-row interleaving address and the intra-row column interleaving address includes: determining the interleaving matrix according to the bit size of the data to be processed; determining the inter-row interleaving address of the interleaving matrix according to the predetermined sequence; according to the prime number sequence and the The reservation sequence determines the column address in the row of the interleaving matrix.

Preferably, encoding the interleaved and written data to be processed and the data to be processed respectively according to a predetermined TURBO encoding method includes: accessing the input data buffer space according to the inter-row interleaving address to obtain the data to be processed; The interleaving address in the row accesses the input data buffer space to obtain the data to be processed after interleaving and writing; the sequential branch data and the interleaved branch data are respectively encoded according to a predetermined TURBO encoding method, wherein the The predetermined TURBO encoding method is multi-bit parallel processing.

Preferably, the predetermined TURBO encoding method includes: inputting a corresponding number of bit data according to the preset processing bit width; adding all one or more bit data before the current bit data to the currently processed bit data for processing to obtain the current bit data Data operation results; output the operation results of multiple current bit data processed in parallel.

Preferably, after obtaining the operation result of the current bit data, the method further includes: updating the state of the encoder.

Preferably, after encoding the interleaved and written data to be processed and the data to be processed respectively according to a predetermined TURBO coding method, the method further includes: separately storing the data encoded and calculated according to a predetermined TURBO coding method.

According to another aspect of the present invention, a data processing device is provided, including: an interleaving module, configured to interleave and write the data to be processed according to a predetermined sequence, wherein the predetermined sequence takes the sequence of output data rows as input The sequence of rows is set; the encoding module is used to encode the data to be processed and the data to be processed after interleaving and writing respectively according to a predetermined TURBO encoding method.

Preferably, the device further includes: a first storage module, configured to store the data to be processed and the data to be processed after interleaving and writing in the input data buffer space.

Preferably, the first storage module includes: an acquisition unit, configured to acquire an inter-row interleave address and an intra-row column interleave address; a first storage unit, configured to write interleaved data to be coded by row according to the inter-row interleave address The interleaving sequence is stored in the input data buffer space; the second storage unit is used to store the data to be encoded after interleaving and writing into the input data buffer space according to the in-row column interleaving order according to the in-row column interleaving address.

Preferably, the obtaining unit obtains the inter-row interleaving address and the intra-row column interleaving address in the following manner: determine the interleaving matrix according to the bit number of the data to be processed; determine the inter-row interleaving address of the interleaving matrix according to the predetermined sequence ; Determine the in-row column address of the interleaving matrix according to the prime number sequence and the predetermined sequence.

Preferably, the encoding module includes: a first access unit, configured to access the input data buffer space according to the inter-row interleaving address to obtain data to be processed; a second access unit, configured to access the interleaving address within the row Accessing the input data buffer space to obtain data to be processed after interleaving and writing; an encoding operation unit for encoding and calculating the sequential branch data and the interleaved branch data according to a predetermined TURBO encoding method, wherein, The predetermined TURBO encoding method is multi-bit parallel processing.

Preferably, the encoding operation unit includes: an input subunit for inputting a corresponding number of bit data according to a preset processing bit width; an encoding operation subunit for converting all one or more bit data before the current bit data It is added to the currently processed bit data for processing to obtain the operation result of the current bit data; the output subunit is used to output the operation results of multiple current bit data processed in parallel.

Preferably, the encoding operation unit further includes: an update subunit, configured to update the state of the encoder.

Preferably, the device further includes: a second storage module, configured to separately store the data encoded by the TURBO encoding unit.

The present invention adopts the following method: the data to be processed is interleaved and written according to a predetermined sequence, and the predetermined sequence is set according to the sequence of output data rows as the sequence of input rows, and the method of inputting data according to the sequence of output rows reduces data A large number of calculations on the output side reduce the calculation of the output, and encode the data according to the predetermined TURBO encoding method, further reducing the calculation on the output side. By using the present invention, when encoding data, a large number of calculations need to be done on the data output side. When faced with more data, the data processing capability is low, and the processing speed can no longer meet the requirements, thereby reducing The operation on the output side is simplified, and the processing capability of the system is improved.

Description of drawings

The accompanying drawings described here are used to provide a further understanding of the present invention and constitute a part of the application. The schematic embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute improper limitations to the present invention. In the attached picture:

FIG. 1 is a schematic structural diagram of a TURBO encoding method according to the related art;

Fig. 2 is a flowchart of a data processing method according to an embodiment of the present invention;

Fig. 3 is a structural block diagram 1 of a data processing device according to an embodiment of the present invention;

FIG. 4 is a second structural block diagram of a data processing device according to an embodiment of the present invention;

Fig. 5 is a structural block diagram three of a data processing device according to an embodiment of the present invention;

FIG. 6 is a fourth structural block diagram of a data processing device according to an embodiment of the present invention;

Fig. 7 is a structural block diagram five of a data processing device according to an embodiment of the present invention;

FIG. 8 is a sixth structural block diagram of a data processing device according to an embodiment of the present invention;

FIG. 9 is a flowchart of a data processing method according to a preferred embodiment 1 of the present invention;

FIG. 10 is a schematic structural diagram of a TURBO encoding device according to a preferred embodiment 1 of the present invention;

Fig. 11 is a schematic diagram of data input according to related technologies;

Fig. 12 is a schematic diagram of data input according to the preferred embodiment 1 of the present invention;

Fig. 13 is a schematic diagram of data storage and extraction according to the preferred embodiment 1 of the present invention;

Fig. 14 is a schematic structural diagram of a TURBO encoding operation unit according to a preferred embodiment 1 of the present invention;

Fig. 15 is a flowchart of a data processing method according to the second preferred embodiment of the present invention.

Detailed ways

Hereinafter, the present invention will be described in detail with reference to the drawings and examples. It should be noted that, in the case of no conflict, the embodiments in the present application and the features in the embodiments can be combined with each other.

When encoding data based on related technologies, a large number of calculations need to be done on the data output side. When faced with a lot of data, the data processing capability is low, and the processing speed can no longer meet the requirements. The embodiment of the present invention provides A data processing method, the flow of the method is shown in Figure 2, including steps S202 to S204:

Step S202, interleaving and writing the data to be processed according to a predetermined sequence, wherein the predetermined sequence is to set the sequence of output data rows as the sequence of input rows;

In step S204, the data to be processed and the data to be processed after interleaving and writing are respectively coded according to a predetermined TURBO coding method.

The embodiment of the present invention adopts the following method: the data to be processed is interleaved and written according to a predetermined sequence, and the predetermined sequence is set according to the sequence of the output data rows as the sequence of the input rows, and by inputting the data according to the sequence of the output rows, reducing It eliminates a large number of calculations on the data output side, reduces the calculation of the output, and encodes the data according to the predetermined TURBO encoding method, further reducing the calculation on the output side. By using this embodiment, when encoding data, a large number of calculations need to be done on the data output side. When faced with more data, the data processing capability is low, and the processing speed can no longer meet the requirements. Further, The operation on the output side is reduced, and the processing capability of the system is improved.

During the implementation process, when the data to be processed is interleaved and written according to the predetermined sequence, the predetermined sequence is set as a T sequence. During the implementation process, the T sequence is generated according to the sequence of the output data rows as the sequence of the input rows, for example, T sequence can be <4, 3, 2, 1, 0> or <9, 8, 7, 6, 5, 4, 3, 2, 1, 0>, etc., among them, <4, 3, 2, 1, 0> indicates that the input of T sequence is 5 lines, and <9, 8, 7, 6, 5, 4, 3, 2, 1, 0> indicates that the input of T sequence is 10 lines.

After interleaving and writing the data to be processed according to a predetermined sequence, the data to be processed and the data to be processed after interleaving and writing may also be stored in the input data buffer space. In the implementation process, it can be divided into the following processing steps:

(1) Obtain inter-row interleaving address and intra-row column interleaving address;

(2) According to the address of interleaving between lines, the data to be encoded after interleaving is stored in the input data buffer space in the order of interleaving between lines;

(3) According to the intra-row and column interleaving addresses, the data to be encoded after interleaving and writing is stored in the input data buffer space in the order of in-row and column interleaving.

When obtaining the interleaving address between rows and the column interleaving address in a row, the interleaving matrix can be determined according to the bit number of the data to be processed. If the number of bits of the data to be processed is large, the input rows of the interleaving matrix can be more, such as 20 rows, If the number of bits of the data to be processed is small, the input rows of the interleaving matrix can be less, for example, 5 rows; the inter-row interleaving address of the interleaving matrix is determined according to the predetermined sequence; the intra-row column address of the interleaving matrix is determined according to the prime number sequence and the predetermined sequence.

Data is stored according to the interleaved address between rows and the interleaved address within a row. The rows and columns can be processed and stored separately, and complex 2-dimensional operations can be decomposed into two independent 1-dimensional operations. The complexity of using storage is reduced geometrically. .

The process of encoding the data to be processed and the data to be processed after interleaving and writing according to a predetermined TURBO encoding method may include: accessing the input data buffer space according to the interleaving address between rows to obtain the data to be processed; The input data buffer space is accessed to obtain the data to be processed after interleaving and writing; the sequential branch data and the interleaving branch data are respectively encoded and operated according to a predetermined TURBO coding method, wherein the predetermined TURBO coding method is multi-bit parallel processing.

In the implementation process, the predetermined TURBO encoding method may include: inputting a corresponding number of bit data according to the preset processing bit width; adding all one or more bit data before the current bit data to the currently processed bit data for processing, Obtain the operation result of the current bit data; output the operation results of multiple current bit data processed in parallel. For example, if the number of bits of data to be processed together is 5, according to iterative calculation, a predetermined TURBO encoding method can be designed according to 5 bits, and its processing performance can be 5 times higher than that of the traditional one.

After the operation result of the current bit data is obtained, the state of the encoder can also be updated. This update process can simplify the encoding structure of the predetermined TURBO encoding mode and facilitate the bit calculation in the next calculation cycle.

After the interleaved and written data to be processed and the data to be processed are respectively coded according to a predetermined TURBO coding method, the data after coding operation according to a predetermined TURBO coding method are respectively stored. For example, the coded sequential branch data and the interleaved branch data are stored in different FIFOs respectively.

The embodiment of the present invention also provides a data processing device. The structural block diagram of the processing device is shown in FIG. The output data line order is set as the input line order; the encoding module 20 is coupled with the interleaving module 10, and is used to encode the data to be processed and the data to be processed after interleaving and writing according to a predetermined TURBO encoding method.

In a preferred embodiment, the device can also include a first storage module 30, as shown in FIG. 4, coupled with the interleaving module 10, for storing the data to be processed and the data to be processed after interleaving and writing in the input data buffer space.

Wherein, the first storage module 30 may include the acquisition unit 302 and the storage unit 304 shown in FIG. 5 . Wherein, the acquisition unit 302 is used to obtain the interleaving address between rows and the column interleaving address in the row; the storage unit 304 is coupled with the acquisition unit 302, and is used to interleave and write the data to be encoded according to the interleaving order between rows according to the interleaving address between rows storing in the input data buffer space; and storing the data to be encoded after the interleaving and writing into the input data buffer space according to the in-row column interleaving order according to the in-row column interleaving address.

In the implementation process, the obtaining unit 302 obtains the inter-row interleaving address and the intra-row interleaving address in the following manner: determine the interleaving matrix according to the number of bits of the data to be processed; determine the inter-row interleaving address of the interleaving matrix according to the predetermined sequence; The reservation sequence determines the in-row column addresses of the interleaving matrix.

Preferably, the above-mentioned device can also be shown in FIG. 6 , the encoding module 20 includes: a first access unit 202, configured to access the input data buffer space according to the inter-row interleaving address, to obtain data to be processed; a second access unit 204, It is used to access the input data buffer space according to the interleaving address in the row to obtain the data to be processed after interleaving and writing; the encoding operation unit 206 is coupled with the first access unit 202 and the second access unit 204, and is used to sequentially branch data Encoding operations are performed on the interleaved branch data according to a predetermined TURBO encoding method, wherein the predetermined TURBO encoding method is multi-bit parallel processing.

In the implementation process, the encoding operation unit 206 can be shown in Figure 7, including: an input subunit 2062, which is used to input a corresponding number of bit data according to the preset processing bit width; an encoding operation subunit 2064, which is used to convert the current bit All one or more bit data before the data are added to the currently processed bit data for processing to obtain the operation result of the current bit data; the output subunit 2066 is used to output the operation results of multiple current bit data processed in parallel; The update subunit 2068 is used to update the state of the encoder. The above subunits are coupled in sequence.

Fig. 8 shows a preferred implementation of the above device, the device further includes: a second storage module 40, coupled with the encoding module 20, for storing the two channels of data encoded by the TURBO encoding unit respectively.

The embodiment of the present invention will be described below in conjunction with the accompanying drawings and preferred embodiments. In the following preferred embodiments, the naming of each module of the device provided is slightly different from the naming of each module in the above-mentioned embodiment, but the combination of each module of the following device The same effects as those of the above-mentioned device can be achieved.

Preferred embodiment one

With the continuous popularization and improvement of 3G network and the rapid development of data communication, new requirements are also put forward for the codec of the channel. Especially in the field of interference cancellation, it is necessary to perform reconfiguration and cancellation for a large number of users within a certain period of time. Therefore, it is necessary to perform TURBO encoding on a large number of users within a certain period of time. The current agreement stipulates the TURBO encoding method, which has gradually been unable to support high-performance interference cancellation chips. For the current TURBO coding, the coding bits are strongly correlated before and after, and theoretically only one bit can be coded at a time. This preferred embodiment provides a TURBO coding method, which can code multiple bits at one time, greatly improving the performance of TURBO coding .

In the implementation process, the TURBO encoding method may be shown in FIG. 9, and the method is executed in the device shown in FIG. 10, including steps S902 to S916.

Step S902: Determine the size of the interleaving matrix according to the size of the input TURBO block, and determine the inter-row interleaving address of the interleaving matrix according to the T sequence.

Step S904, according to the sequence q, T, etc., and the p, v lookup table, calculate the column address in the row of the interleaving matrix.

Step S906, according to the interleaving address, store the encoded data into the input data buffer space in the order of interleaving.

During the implementation of this step, the coded data is stored according to the address interleaved between rows, among which, according to the size of the TURBO block, there are at most 4 interleaving methods:

<4,3,2,1,0>;<9,8,7,6,5,4,3,2,1,0>;<19,9,14,4,0,2,5,7 ,12,18,16,13,17,15,3,1,6,11,8,10>;<19,9,14,4,0,2,5,7,12,18,10,8 ,13,17,3,1,16,6,15,11>.

When storing input data, except at the row boundary, each clock writes adjacent 5-bit data in the row, and the row boundary writes the valid bits of the column number C modulo 5. FIG. 11 shows the traditional input when the number of rows is 5 in the related art. Compared with the traditional input, FIG. 12 shows the input sequence of this embodiment.

Step S908, accessing the input data buffer space according to the interleaving address between rows to obtain sequential branch data. Since the input data is stored in the row order of the interleaving matrix, when reading data, after each row of data is read, it must be linked to the next row according to the T sequence. This process can also be referred to in Figure 12. . Perform row interleaved sequential reading to obtain sequential sequence data.

Step S910, perform column access to the input data buffer space according to the column interleave address in the row, and obtain interleaved branch data. Since the input data is input in the row order of the interleaving matrix when saving the input data, it is not necessary to convert the rows and columns at the same time when reading the data, only the intra-row index is required, and no inter-row conversion is required. Rows are accumulated sequentially, adding 5 rows each time, the total row number R of the modulo interleaving matrix.

During the implementation of step S908 and step S910, the processing process is different from the common data storage method, and the schematic diagram of the storage can be shown in FIG. 13 . In the figure, the data stored by row number is on the left, and the data stored by column number is on the right. When reading, the data on the left is read through the row address, and the data on the right is read through the column address in the row. Its processing process decomposes complex 2-dimensional operations into two independent 1-dimensional operations, and the complexity of decoding circuits using storage space is reduced geometrically.

In step S912, the obtained sequential branch and interleaved branch data are respectively sent to two TURBO operation units.

Step S914, performing TURBO operation on the input data.

During the implementation process, the encoding operation unit can be set according to the result of the iterative operation. The structure of the encoding operation unit designed in this embodiment is shown in FIG. 14 . Because TURBO coding has a strong front-to-back correlation, the parallel method of directly repeating single-bit coding must be very troublesome. Assume that at the end of a specific moment, the register values of the TURBO encoder are d1, d2, and d3 respectively. The input data at the current moment is x(i), and the calculation formula of the corresponding output y(i) is as follows:

Y(i)=(x(i)+(d2+d3)+d1)+d3;

=x(i)+d2+d1;

After the first calculation cycle, the status register of the TURBO code is updated as follows: D1=x(i)+(d2+d3); D2=d1; D3=d2;

Y(i+1)=(x(i+1)+(d1+d2)+x(i)+(d2+d3))+d2;

=x(i+1)+x(i)+d1+d2+d3;

After the second calculation cycle, the status register of TURBO encoding is updated as follows: D1=x(i+1)+d1+d2; D2=x(i)+(d2+d3); D3=d1;

Y(i+2)=x(i+2)+x(i)+(d2+d3)+x(i+1)+d1+d2

=x(i+2)+x(i+1)+x(i)+d3+d1;

After the third calculation cycle, the status register of TURBO encoding is updated as: D1=x(i+2)+x(i)+(d2+d3)+d1; D2=x(i+1)+d1+d2 ;D3=x(i)+(d2+d3);

Y(i+3)=x(i+3)+x(i+2)+x(i)+(d2+d3)+d1+x(i+1)+d1+d2;

=x(i+3)+x(i+2)+x(i+1)+x(i)+d3;

After the fourth calculation cycle, the status register of TURBO code is updated as: D1=x(i+3)+x(i+1)+d1+d2+x(i)+(d2+d3)=x(i +3)+x(i+1)+x(i)+d1+d3; D2=x(i+2)+x(i)+(d2+d3)+d1; D3=x(i+1) +d1+d2;

Y(i+4)=x(i+4)+x(i+3)+x(i+1)+x(i)+d1+d3+x(i+2)+x(i)+( d2+d3)+d1

=x(i+4)+x(i+3)+x(i+1)+x(i+2)+d2;

After the fifth calculation cycle, the status register of TURBO encoding is updated as: D1=x(i+4)+x(i+2)+x(i)+(d2+d3)+d1+x(i+1 )+d1+d2=x(i+4)+x(i+2)+x(i+1)+x(i)+d3; D2=x(i+3)+x(i+1)+ x(i)+d1+d3; D3=x(i+2)+x(i)+(d2+d3)+d1;

Y(i+5)=x(i+5)+x(i+4)+x(i+2)+x(i+1)+x(i)+d3+x(i+3)+x (i+1)+x(i)+d1+d3

=x(i+5)+x(i+4)+x(i+3)+x(i+2)+d1;

Through the above iterative operation, an encoding operation unit for parallel processing of 5-bit input can be designed. This encoding operation unit can solve the problem of strong correlation between each bit of data before and after, and can increase the encoding speed by 5 times. Of course, in the actual implementation process, the number of bits processed in parallel can be 10 bits, and then the input port of 10 bits of data can be set, and the design can be made according to the iteration result.

In step S916, the two channels of encoded output data are respectively stored in two different channels of FIFO, waiting for downstream operations.

In the implementation process, the data of each branch is stored in different FIFOs, which is beneficial to the downstream rate matching operation, and because it is stored in different FIFOs, the two encoding rates do not need to be kept consistent at all times, further reducing the two TURBO calculation units relevance.

The TURBO encoding device of Fig. 10 is further described below:

Among them, the q sequence, the r sequence, and the T sequence are storage units, which are used to store their respective sequence data. The data volume of these sequences is not large, and they can be built with registers.

The reordering operation unit is mainly used to calculate the r sequence, mainly to reorder the position of the data of the q sequence according to the position indication of the T sequence, and obtain a new sequence r.

The index calculation unit of the S sequence is different from the related art, and this embodiment is used to calculate the index address of the S sequence. According to normal calculation, the index address is equal to the product of the column number of the interleaving matrix and the value corresponding to the r sequence. Due to the high cost of multiplication and poor timing performance, this unit is combined with the index storage unit of the S sequence to replace the multiplier in the mode of an adder plus a storage unit.

According to the protocol U _i (j)=s((j× _ri )mod(p-1)), multiplication is required to complete the product of j and r. j represents the column number, and the r value within a row is the same. We calculate in the order of columns, and store the calculation results of the previous column in a storage space, then when calculating the current (j+1)*r, we only need to take out the value stored in the last calculation from the storage space, and add Adding the current r can achieve the purpose of replacing multiplication with addition, and each point in a column is irrelevant, so the column can be used as the unit, and the points in the column can be operated in parallel.

The in-row column address storage space is used to store the in-row column information in the interleaving address. Each address space stores 5 interleaving address information. The calculation of the column address in the row is calculated according to the order of the interleaving matrix, and calculated according to the order of the columns. After calculating 5 interleaving addresses, use the 5 interleaving addresses as a basic storage unit and store them in the RAM. When reading the interleaving address, 5 interleaving addresses are also regarded as a unit, and one unit is taken at a time.

In the embodiment of the present invention, the input data storage space is used to store input data and provide TURBO encoded data. To read irrelevant N-bit data in the storage space, traditionally, when storing data, N copies of data are copied for storage, so that the stored data is expanded to N times, and each piece of data is stored in a separate RAM. A total of N RAMs are required. When N-bit data needs to be read, it is only necessary to read data from N RAMs at the same time, and this device only needs one copy of the storage space shown in FIG. 13 . Among them, the space shown in Figure 13 can use registers as storage units. According to the maximum demand, the size of the planned storage space is 260X20. As shown in the figure: the sequential branch data decoding circuit and the interleaved branch data decoding circuit. Sequential branch data is read column by column within a row, and 5 adjacent data of the same row are acquired each time. Therefore, a simple row decoding circuit and column decoding circuit are included. The interleaving branch data needs to perform row and column transformation according to the rules of the interleaving matrix to read the data. However, when the input data is stored, it has been stored in the order of row transformation, so when reading the interleaved branch data, only the column transformation is required, and the rows are read sequentially.

In this preferred embodiment, the parallel encoding unit is used to perform TURBO encoding operation, and can seamlessly support 4-bit and 5-bit parallel pipeline switching. Moreover, due to the effective planning for the reading of the data to be encoded, the reading of the interleaving branch reads at most one bit of data, so the invalid bit obtained each time is at most 1 bit, and the TURBO operation unit can perform 4, 5 bit Switch seamlessly without any additional overhead. The mismatch between the sequential branch and the interleaved branch operation rate can be shielded by the FIFO downstream of the operation unit.

Due to the characteristics of TURBO coding and its interleaving sequences filled with invalid bits, the improvement of TURBO is greatly limited. Through this preferred embodiment, the encoding performance is improved by 5 times, and according to actual needs, the performance can be easily expanded to 20 times. In terms of storage and management of the input data to be encoded, the traditional method requires 5 sets of storage space (if a single-port RAM is not a dual-port RAM, 10 sets of storage space are required), 10 sets of row decoding circuits, and 10 sets of columns Decoding circuitry to provide 5 bits of data for the sequential branch, and 5 bits of data for the interleaved branch. However, the device of this embodiment only needs 1 set of storage space, 2 column decoding circuits, and 6 row decoding circuits. The storage space is 1/5 of the traditional method, and the decoding circuit scale is 2/5 of the traditional method. Significantly reduces resource overhead. And when storing data, the data is stored according to the row transformation of the interleaving matrix, so that when the interleaving branch data is read, the two-dimensional row-column interleaving operation is converted into a one-dimensional row-column interleaving operation, and the data reading control is complicated. The degree decreases at a geometric level.

Preferred embodiment two

The implementation of this preferred embodiment is based on the device shown in FIG. 10 , and the implementation process is shown in FIG. 15 , including steps S1502 to S1524.

Step S1502, pre-store the prepared prime number series q in the internal storage space for use in the following steps.

In this step, the maximum number of prime number series is the number of rows of the interleaving matrix, and the maximum number of rows of the largest interleaving matrix is 20, so the maximum number of this sequence is 20, which can be stored in registers. The sequence is as follows:

1, 7, 11, 13, 17, 19, 23, 29, 31, 37, 41, 43, 47, 53, 59, 61, 67, 71, 73, 79.

In step S1504, the root protocol stipulates that the four T series are pre-stored in the internal storage space for use in the following steps.

4 groups of T-sequences, each sequence has a maximum of 20 numbers, which can also be stored in registers, as follows:

T1: <4,3,2,1,0>;

T2: <9,8,7,6,5,4,3,2,1,0>;

T3: <19,9,14,4,0,2,5,7,12,18,16,13,17,15,3,1,6,11,8,10>;

T4: <19,9,14,4,0,2,5,7,12,18,10,8,13,17,3,1,16,6,15,11>.

Step S1506, according to the encoded income reference K (the size of the encoded block), select a corresponding group of T series according to the protocol requirements. And calculate the number of rows R and the number of columns C, and obtain p and v parameters according to the protocol query table.

This step selects a set of corresponding T sequences according to the range of the K value, calculates the number of rows R and the number of columns C according to the protocol specification, and queries the table to obtain p and v parameters.

Step S1508, generate r-sequence according to the selected T-sequence and the pre-prepared q-sequence.

It is very difficult to implement the national policy to read the q sequence and the T sequence in order, and use the value of the q sequence as the write data, and the value of the T sequence as the write address, and perform the write operation on the r sequence storage unit.

Step S1510, according to the T sequence, interleave the input data row by row according to the row transformation rule of the interleaving matrix, and input row by row into the input data storage space.

Step S1512, according to the parameters C, p, sequence r, and its internal counter, calculate the address index of the S series.

The execution of this step calculates the column address. Directly access the r sequence, and read the corresponding r value according to the counter. If it is not the first column after interleaving, read the data at the same row position of the S sequence index RAM, then perform an addition operation on the read r data and the S index, and compare the value of the result of the addition operation with p-1, if If it is greater than p-1, the subtraction operation is performed, and p-1 is subtracted, otherwise it remains unchanged. Calculate the index of the S sequence, and update the calculated new S index to the position corresponding to the same row in the S sequence index RAM.

Step S1514, according to the address index of the S sequence, access the storage space of the S sequence, and obtain the position information of the corresponding row of the interleaving matrix.

During implementation, the pre-calculated S sequence is stored in the S sequence space, and the corresponding S sequence value is read according to the calculated S sequence and v parameter.

Step S1516, according to the C, R parameters and their internal counters, calculate the column position information of the interleaving matrix. Calculate the interleaved column address according to the read S sequence data and the column number C of the interleaving matrix of this TURBO block, and then calculate the row address according to the counter and its r sequence.

Step S1518, according to the row and column information of the interleaving matrix, access the input data storage space, and obtain the interleaved data.

Step S1520, according to the internal counter, sequentially access the data storage space, and obtain sequential data.

When the above steps are implemented, the data to be encoded is stored in parallel in the encoded data buffer space, and then the data is read in parallel according to the interleaved address and the sequential address. Wherein, the storage unit is a specially designed register array, planned according to the largest interleaving matrix, with a size of 20 rows and 256 columns. If the matrix to be coded is smaller than the maximum interleaving matrix, then the matrix to be coded and the left vertex of the maximum matrix coincide and are stored in the storage space in the order of row transformation.

Among them, the addressing of the storage space adopts the method of joint addressing of rows and columns. Sequential matrix operations have a set of row and column decoding units respectively, and the column decoding circuit uses one column decoding port for 5 data. For example, if the column decoding circuit is selected as 0, it means that the data in columns 0, 1, 2, 3, and 4 are selected. The interleaving matrix operation has a group of row and column decoding units respectively, and the row decoding circuit uses one row decoding port for 5 data. For example, if the line decoding circuit is selected as 0, it means that the data in the data lines 0, 1, 2, 3, and 4 are selected.

When storing the input data, the input data is written row by row in the sequence after row conversion. In the last address unit of each row, valid data is not necessarily an integer multiple of 5. Therefore, when writing, valid bit positions are filled with input data, and invalid bit positions are filled with arbitrary values. When the sequential branch data is read, the interleave conversion is also performed, and the row-by-row read operation is performed. Each address unit is read to obtain 5-bit data. If there is currently valid 5-bit data, TURBO encoding is performed. If not, wait for the data to be encoded to be read next time, combine the currently acquired effective bits with the last acquired effective bits, and take the combined first 5 bits for TURBO encoding.

When reading the interleaving branch data, the 5 rows of data are sequentially read in units of 5 consecutive rows, and the corresponding 5-bit data is selected from the sequential 5 rows according to the interleaving address. Since in the process of reading the interleaving branch data, the read data part is invalid data, and at most only one data is invalid, so we have a status indication register to instruct TURBO to perform 5-bit encoding or 4-bit encoding. And 4-bit and 5-bit coding can be seamlessly piped.

Since the input data is stored by row transformation, the original multi-dimensional interleaving of row and column transformation at the same time is converted into one branch with only row transformation and one branch with only column transformation. The complexity is reduced from two latitudes to one latitude, and the complexity is reduced at a geometric level.

In step S1522, the acquired input data is input to a parallel TURBO encoder, and the encoding operation is performed in parallel.

The tenth step is to perform TURBO operation, which can be used for 4-bit or 5-bit encoding, and 4-bit encoding and 5-bit encoding can be seamlessly switched, and seamless pipeline can be performed.

In step S1524, the output of the TURBO operation unit is divided into sequential and interleaved channels, which are stored in different FIFOs respectively.

The output is stored in different FIFOs, mainly to reduce the coupling degree of the two encoding operation units, so as to facilitate the independent operation of the two encoding units. In the sequence sequence branch, when the sequence matrix row is switched, there is a situation of pausing a clock cycle, and in the interleaving sequence branch, there is a situation of invalid bits, so the encoding rate of the two branches must be consistent, which will increase a lot the complexity. Therefore, the outputs are stored in different FIFOs, which can cut off the relevant lines of the two sets of sequence codes and reduce the complexity of the code control.

From the above description, it can be seen that the present invention achieves the following technical effects:

The embodiment of the present invention adopts the following method: the data to be processed is interleaved and written according to a predetermined sequence, and the predetermined sequence is set according to the sequence of the output data rows as the sequence of the input rows, and by inputting the data according to the sequence of the output rows, reducing It eliminates a large number of calculations on the data output side, reduces the calculation of the output, and encodes the data according to the predetermined TURBO encoding method, further reducing the calculation on the output side. By using this embodiment, when encoding data, a large number of calculations need to be done on the data output side. When faced with more data, the data processing capability is low, and the processing speed can no longer meet the requirements. Further, The operation on the output side is reduced, and the processing capability of the system is improved.

Obviously, those skilled in the art should understand that each module or each step of the above-mentioned present invention can be realized by a general-purpose computing device, and they can be concentrated on a single computing device, or distributed in a network formed by multiple computing devices Alternatively, they may be implemented in program code executable by a computing device so that they may be stored in a storage device to be executed by a computing device, and in some cases in an order different from that shown here The steps shown or described are carried out, or they are separately fabricated into individual integrated circuit modules, or multiple modules or steps among them are fabricated into a single integrated circuit module for implementation. As such, the present invention is not limited to any specific combination of hardware and software.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and changes. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included within the protection scope of the present invention.

Claims (16)

1. A data processing method, characterized in that, comprising: Interleaving and writing the data to be processed according to a predetermined sequence, wherein the predetermined sequence is to set the sequence of output data rows as the sequence of input rows; The data to be processed after the interleaving and writing and the data to be processed are respectively coded in a predetermined TURBO coding manner. 2. The method according to claim 1, further comprising: The data to be processed and the data to be processed after interleaving and writing are stored in the input data buffer space. 3. The method according to claim 2, wherein storing the data to be processed and the data to be processed after interleaving and writing in the input data buffer space comprises: Obtain inter-row interleaving address and intra-row column interleaving address; According to the address of interleaving between lines, the data to be encoded after interleaving and writing is stored in the input data buffer space in the order of interleaving between lines; The interleaved and written data to be encoded is stored in the input data buffer space according to the intra-row and column interleaving order according to the intra-row and column interleaving address. 4. The method according to claim 3, wherein obtaining interleaved address between rows and column interleaved address in row comprises: determining an interleaving matrix according to the number of bits of the data to be processed; determining an inter-row interleaving address of the interleaving matrix according to the reservation sequence; Determine the column address in the row of the interleaving matrix according to the prime number sequence and the predetermined sequence. 5. The method according to any one of claims 1 to 4, wherein encoding the data to be processed and the data to be processed after interleaving and writing respectively according to a predetermined TURBO encoding method comprises: Accessing the input data buffer space according to the inter-row interleaving address to obtain the data to be processed; Accessing the input data buffer space according to the in-row column interleaving address to obtain the data to be processed after interleaving and writing; The sequential branch data and the interleaved branch data are respectively encoded according to a predetermined TURBO coding method, wherein the predetermined TURBO coding method is multi-bit parallel processing. 6. The method according to claim 5, wherein the predetermined TURBO encoding method comprises: Input the corresponding number of bit data according to the preset processing bit width; Add all one or more bit data before the current bit data to the currently processed bit data for processing, and obtain the operation result of the current bit data; Output the operation results of multiple current bit data processed in parallel. 7. The method according to claim 6, further comprising: updating the encoder state after obtaining the operation result of the current bit data. 8. The method according to claim 7, characterized in that, after encoding the data to be processed and the data to be processed after interleaving and writing respectively according to a predetermined TURBO encoding method, further comprising: The data encoded and calculated according to the predetermined TURBO encoding method are stored separately. 9. A data processing device, characterized in that it comprises: An interleaving module, configured to interleave and write the data to be processed in a predetermined sequence, wherein the predetermined sequence is to set the sequence of output data rows as the sequence of input rows; The encoding module is used to encode the data to be processed and the data to be processed after interleaving and writing respectively according to a predetermined TURBO encoding method. 10. The device according to claim 9, further comprising: The first storage module is configured to store the data to be processed and the data to be processed after interleaving and writing in the input data buffer space. 11. The device according to claim 10, wherein the first storage module comprises: An acquisition unit, configured to acquire inter-row interleaving addresses and intra-row column interleaving addresses; The storage unit is used to store the data to be encoded after interleaving and writing into the input data buffer space according to the interleaving address between rows according to the interleaving address between rows; The data is stored in the input data buffer space in an interleaved order within a row and column. 12. The device according to claim 11, wherein the acquisition unit acquires the inter-row interleaving address and the intra-row column interleaving address in the following manner: determining an interleaving matrix according to the number of bits of the data to be processed; determining inter-row interleaving addresses of the interleaving matrix according to the reservation sequence; Determine the column address in the row of the interleaving matrix according to the prime number sequence and the predetermined sequence. 13. The device according to any one of claims 9 to 12, wherein the encoding module comprises: The first access unit is used to access the input data buffer space according to the inter-row interleaving address to obtain data to be processed; The second access unit is configured to access the input data buffer space according to the in-row column interleaving address, and obtain the data to be processed after interleaving and writing; An encoding operation unit, configured to perform an encoding operation on the sequential branch data and the interleaved branch data according to a predetermined TURBO encoding method, wherein the predetermined TURBO encoding method is multi-bit parallel processing. 14. The device according to claim 13, wherein the encoding operation unit comprises: The input subunit is used to input a corresponding number of bit data according to the preset processing bit width; The encoding operation subunit is used to add all one or more bit data before the current bit data to the currently processed bit data for processing, and obtain the operation result of the current bit data; The output subunit is used to output the operation results of multiple current bit data processed in parallel. 15. The device according to claim 14, wherein the encoding operation unit further comprises: The update subunit is used to update the encoder state. 16. The device according to claim 15, further comprising: The second storage module is used to separately store the data encoded by the TURBO encoding unit.

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