CN103546394A - Communication device - Google Patents
Communication device Download PDFInfo
- Publication number
- CN103546394A CN103546394A CN201310514176.4A CN201310514176A CN103546394A CN 103546394 A CN103546394 A CN 103546394A CN 201310514176 A CN201310514176 A CN 201310514176A CN 103546394 A CN103546394 A CN 103546394A
- Authority
- CN
- China
- Prior art keywords
- logical device
- buffer zone
- message
- buffer
- data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004891 communication Methods 0.000 title abstract description 7
- 230000005540 biological transmission Effects 0.000 claims description 49
- 238000012790 confirmation Methods 0.000 claims description 6
- 230000004044 response Effects 0.000 claims description 2
- 238000011144 upstream manufacturing Methods 0.000 description 6
- 101100325756 Arabidopsis thaliana BAM5 gene Proteins 0.000 description 5
- 101150046378 RAM1 gene Proteins 0.000 description 5
- 101100476489 Rattus norvegicus Slc20a2 gene Proteins 0.000 description 5
- 238000000034 method Methods 0.000 description 3
- 238000012546 transfer Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 230000003993 interaction Effects 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 101000823103 Equus caballus Alpha-1-antiproteinase 4 Proteins 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
Images
Landscapes
- Bus Control (AREA)
- Information Transfer Systems (AREA)
Abstract
The invention provides a communication device which comprises a CPU, a first logic device, a second logic device, a PCIE, an Switch and a service interface card. The first logic device and the second logic device comprise cache units and analysis units respectively. After receiving a message sent by the CPU, the first logic device strips control information, stores the data information in a first cache area, and analyzes the BD corresponding to a structure of the control information. When the first cache area is full, the data information in the first cache area and the corresponding BD is sent to the second logic device. After the second logic device receives the data information, one or more data messages are restored according to the BD and are sent through the service interface card. After the data messages are sent, a confirmed BD message is replied to the first logic device. The communication device reduces the quantity of TLP messages and improves effective data bandwidth of a PCIE bus.
Description
Technical field
The present invention relates to the communication technology, relate in particular to a kind of communicator.
Background technology
Current, for the universal and diversified application of network enabled, the high speed of communication equipment, efficient, extensibility are paid close attention to by people more and more.Because bus is with the feature such as good compatibility, transmission speed be fast, well met the diversified demand of user.The demand that wherein PCI-Express (hereinafter to be referred as PCIE) bussing technique can provide high bandwidth to meet system, thereby by people's extensive use.But the effective bandwidth utilance of PCIE bus is lower, does not reach higher transmission rate.
Common PCIE bus structures as shown in Figure 1, cpu chip is by an inner integrated root controller Root Complex or an external Root Complex, through a slice or multi-disc exchange chip PCIE Switch, both can be connected with a plurality of PCIE Endpoint terminal equipments, also can be connected with the equipment of a plurality of traditional PCI/PCI-X interfaces, for user expands abundant business interface.Data interaction between CPU and PCIE terminal equipment is undertaken by the TLP message of PCIE standard defined.As shown in Figure 2, the control information expense of a TLP message is 24 bytes.Such as, CPU writes the data of 4 bytes to some PCIE equipment, and what finally in PCIE bus, transmit will be the TLP message of 28 bytes, and wherein, real valid data are the Data part shown in Fig. 2, only 4 bytes.As can be seen here, when there is this scrappy data interaction frequently between CPU and PCIE equipment, the bandwidth availability ratio of PCIE can reduce, because the expense of TLP control information has accounted for very most bandwidth.
Conventionally, people using cpu chip integrated a PCIE controller as Root Complex, be directly connected with the upstream port Up Stream of a PCIE Switch.PCIE Switch also goes out a plurality of downstream port Down Stream, and each Down Stream can connect a Service Interface Card with PCIE interface.Structured flowchart is as shown in Figure 3: between CPU and concrete Service Interface Card, in the mode of BD, realize reception and the transmission of message.The content of BD as shown in Figure 4, each BD8 byte., unified CPU is referred to as descending to the message direction of transfer of Service Interface Card herein, the message direction of transfer that business interface is snapped into CPU is referred to as up.
CPU received all BD corresponding to buffer memory by self and sends to Service Interface Card before receiving uplink message, when receiving uplink message: Service Interface Card is received a message, to CPU, send a up TLP message, the 64 byte messages of take are example, and TLP message total length is 24+64=88 byte; Service Interface Card is write a BD that message is corresponding to CPU, corresponding a up TLP message, and TLP message total length is 24+8=32 byte; Afterwards, CPU responds idle BD of Service Interface Card, corresponding a descending TLP message 24+8=32 byte.
When sending downlink message: CPU writes a busy BD to interface card, and CPU sends a descending TLP message, and data total length is 24+8=32 byte; Interface card parses message address and the length information of this BD, to CPU, initiates read request, corresponding a up TLP message, 24 bytes; CPU responds this read request returned packet data, corresponding a descending TLP message, and TLP message total length is 24+64=88 byte; Interface card sends the backward CPU of message and writes one and be sent completely BD, corresponding a up TLP message, and TLP message total length is 24+8=32 byte.
The transmitting-receiving flow process of 64 byte messages recited above of take is example, real valid data bandwidth is each 64 bytes of uplink and downlink, consume altogether downlink bandwidth 152 bytes, upstream bandwidth 176 bytes, for the ease of calculating, upstream bandwidth is also slightly counted as to 152 bytes, and valid data bandwidth only accounts for the 64/152=42% of total bandwidth.
As can be seen here, even if the PCIE link of a 5G * 4Lane, its physics total bandwidth has 20G, through the decoded actual physical bandwidth of 10b/8b, is 16G.But when the such small messages of transmission 64 bytes, can only reach the speed of 6.72G bps.Cannot support the surface speed forwarding of 8Gbps or other interface of 10Gbps speed level.
Summary of the invention
In view of this, the invention provides a kind of communicator, comprise CPU, described device further comprises the first logical device, the second logical device, PCIE Switch and Service Interface Card, wherein said the second logical device is on Service Interface Card, the first logical device is connected with CPU by point-to-point bus, the first logical device is connected by PCIE Switch with the second logical device, the first logical device and the second logical device all comprise buffer unit and resolution unit, and wherein the buffer unit of the first logical device comprises the first buffer zone and the second buffer zone; The buffer unit of the first logical device receives after the downlink data message of CPU transmission, peel off control information, data message is existed to the first buffer zone, and resolution unit is resolved control information, and the descending transmission buffer memory descriptor BD that structure is corresponding deposits the second buffer zone of buffer unit in; When the first buffer zone is filled with, data message in the first buffer zone is sent to the buffer unit of the second logical device, and descending transmission BD corresponding to data message sent to the buffer unit of the second logical device by BD message, wherein, described BD message comprises an above BD; The buffer unit of the second logical device receives after data message, according to the BD information of descending transmission BD message, data message is reduced to one or more data messages and is sent by Service Interface Card; After being sent completely, replying one and confirm that BD message is to the first logical device, wherein, described confirmation BD message comprises the confirmation BD for a described above BD.
Accompanying drawing explanation
Fig. 1 is a kind of building-block of logic of communicator;
Fig. 2 is the structural representation of TLP message;
Fig. 3 is the building-block of logic of another kind of communicator;
Fig. 4 is the content schematic diagram of BD;
Fig. 5 is the building-block of logic of a kind of communicator of the embodiment of the present invention;
Fig. 6 is the building-block of logic of the another kind of communicator of the embodiment of the present invention;
Fig. 7 is the building-block of logic of another communicator of the embodiment of the present invention.
Embodiment
In order to address this problem, the embodiment of the present invention provides a kind of communicator.Please refer to Fig. 5, the embodiment of the present invention provides a kind of communicator, comprises CPU11, the first logical device 12, PCIESwitch13, the second logical device 14 and Service Interface Card 15.Wherein the first logical device 12 is connected with CPU11 by point-to-point bus, the second logical device 14 is on Service Interface Card 15, the first logical device 12 is connected with Down Stream with the Up Stream on PCIE Switch13 by PCIE bus respectively with the second logical device 14, the first logical device 12 comprises resolution unit 121 and buffer unit 122, and wherein said buffer unit comprises the first buffer zone 1221 and the second buffer zone 1222.The second logical device comprises resolution unit 141 and buffer unit 142.
Between the first logical device 12 and CPU11, be as SPI4(System Packet Interface Level4 by point-to-point bus) be connected, its feature is that both sides can be by data-message transmission to opposite end without addressing operation.Described data message is to transmit with the form of data flow, in the header SOP/ telegram end EOP indication that the control information of data message (as message length, SOP/EOP sign and VALID sign) is included in data flow.
In the processing of downlink message, when the buffer unit 122 of the first logical device 12 receives the downlink data message that CPU11 sends, because the first logical device 12 is connected by PCIE bus with the second logical device 14, the data message of its transmission is carried on TLP message.During described data-message transmission, also need BD message to carry out the control information of data of description message.If data message is sent to the second logical device 14, need so the BD message that data message is corresponding.Therefore the first logical device 12 is first peeled off the control information (as message length, SOP/EOP sign and VALID sign) of described data message from the header SOP/ telegram end EOP indication of data message, then data message be there is to the first buffer zone 1221, resolution unit 121 is resolved described control information, as message length, SOP/EOP sign and VALID identification information, the descending transmission BD that the control information obtaining according to parsing structure is corresponding deposits the second buffer zone 1222 of buffer unit 122 in.
When the first buffer zone 1221 is filled with, data message in the first buffer zone 1221 is sent to the buffer unit 142 of the second logical device 14, and descending transmission BD corresponding to data message sent to the buffer unit 142 of the second logical device 14 by BD message.
It should be noted that: described BD message comprises BD corresponding to all data messages in described the first buffer zone 1221, because the first buffer zone 1221 at least can hold a data message, in a corresponding BD message, also comprise more than one BD.For example CPU issues three data messages and is cached in the first buffer zone 1221 to the first logical device 12, corresponding the first logical device 12 can three descending transmission BD of structure, each BD is 8 bytes, when now the first buffer zone 1221 is filled with, by a BD message, send, the BD that sends described three data messages needs 8 * 3+24=48 byte altogether.But in prior art, normally send three BD messages, need (8+24) * 3=96 byte.Only in the transmission of BD message, the present invention just can promote 50 percent effective bandwidth utilance as can be seen here.
The buffer unit 142 of the second logical device 14 receives after data message, according to the BD information of descending transmission BD message (comprising, message length, SOP/EOP sign and VALID identification information) data message is reduced into one or more data messages, described reduction is normally first carried out cutting according to the message length in BD information and SOP/EOP sign by data message, obtains each data message.Then by Service Interface Card 15, sent.After being sent completely, the second logical device 14 is replied one and is confirmed that BD message is to the first logical device, and wherein, described confirmation BD message comprises the confirmation BD for a described above BD.
As can be seen here, by the buffer unit 122 of the first logical device 12, realize the fully loaded transmission of TLP message in PCIE bus.Reduce the quantity of descending TLP message, promoted the valid data bandwidth of PCIE bus.
In embodiments of the present invention, described logical device can be made up of multiple elements to realize logic function, also can be programmable logical device, the on-site programmable gate array FPGA of take in the present embodiment describes as example, the first logical device is FPGA1, and the second logical device is FPGA2.FPGA1,2 common built-in random access memory ram pieces or external RAM piece are realized buffer memory message.Because FPGA1 connects CPU, the message of transmitting-receiving is many, needs larger buffer unit, and therefore, conventionally can the more external capacity larger RAM of FPGA1 is as its buffer unit.But FPGA2 serves Service Interface Card, traffic carrying capacity is less relatively, and in order to save an only built-in less RAM of cost FPGA2, certainly, FPGA2 also can a built-in larger RAM.Therefore for the size of the RAM capacity of FPGA2, the mode that FPGA1 sends message to FPGA2 is some difference also, is generally divided into master-slave mode and Peer.
For FPGA1, the larger situation of 2 buffer memory difference, adopts master-slave mode conventionally, is specially, and the FPGA1 that spatial cache is large is main, the FPGA2 that spatial cache is little be from.Because FPGA2 does not possess enough large spatial cache, cannot store mass data information, so can only be from the buffer memory of FPGA1 read data.Its embodiment is: when the first buffer zone of FPGA1 is filled with, first the BD message corresponding with RAM1 issued to FPGA2, FPGA2 sends read request according to BD information to the RAM1 of FPGA1, and FPGA1 response read request is returned to the data message of corresponding RAM1.
For FPGA1, the smaller situation of 2 buffer memory difference, adopts Peer conventionally, is specially, and when the RAM1 of FPGA1 is filled with, the data message of RAM1 is write in FPGA2RAM by PCIE bus, and BD message corresponding to data message sent to FPGA2.Which is convenient than master-slave mode, owing to having saved the process of read request, makes communication quicker.
Please refer to Fig. 6, the embodiment of the present invention provides another kind of communicator, comprises CPU21, the first logical device 22, PCIE Switch23, the second logical device 24 and Service Interface Card 25.Wherein the first logical device 22 is connected with CPU21 by point-to-point bus, the second logical device 24 is on Service Interface Card 25, the first logical device 22 is connected with Down Stream with the Up Stream on PCIE Switch23 by PCIE bus respectively with the second logical device 24, the first logical device 22 comprises that resolution unit 221 and buffer unit 222, the second logical devices comprise resolution unit 241 and buffer unit 242.Wherein said buffer unit 242 comprises the 4th buffer zone 2421 and the 5th buffer zone 2422.
On to the processing of upstream data, the buffer unit 242 of the second logical device 24 receives after the uplink data messages of Service Interface Card 25 transmissions, first peel off control information, data message is put into the 4th buffer zone 2421, resolution unit 241 is resolved after control information, construct up transmission BD and deposit the 5th buffer zone 2422 in, when the 4th buffer zone 2421 is filled with, data message in the 4th buffer zone 2421 and corresponding up transmission BD are sent to the buffer unit 222 of the first logical device 22 by BD message, wherein, described BD message comprises an above BD.
The buffer unit 222 of the first logical device 22 receives after data message, according to up transmission BD information, data message is reduced into one or more data messages, sends to CPU21.
In the present embodiment, by the buffer unit 242 of the second logical device 24, incite somebody to action, realized the fully loaded transmission of TLP message in PCIE bus, reduced the quantity of up TLP message, promoted the valid data bandwidth of PCIE bus.
Please refer to Fig. 7, the embodiment of the present invention provides another communicator, comprises CPU31, the first logical device 32, PCIE Switch33, the second logical device 34 and Service Interface Card 35.Wherein the first logical device 32 is connected with CPU31 by point-to-point bus, the second logical device 34 is on Service Interface Card 35, the first logical device 32 is connected with Down Stream with the Up Stream on PCIE Switch33 by PCIE bus respectively with the second logical device 34, the first logical device 32 comprises resolution unit 321 and buffer unit 322, and wherein said buffer unit comprises the first buffer zone 3221 and the second buffer zone 3222.The second logical device comprises resolution unit 341 and buffer unit 342.Wherein said buffer unit 342 comprises the 4th buffer zone 3421 and the 5th buffer zone 3422.
Described the first logical device 32 further comprises the 3rd buffer zone 3223, and standby each other with the first buffer zone 3221, described the first logical device 32 deposits the data message of receiving in first buffer zone 3221, when the first buffer zone 3221 is filled with, by remaining data information memory to the three buffer zones 3223, and further store follow-up message, after data message in the first buffer zone 3221 sends, as the standby buffer zone of the 3rd buffer zone 3223, the two alternately backups each other.
34 of described the second logic devices further comprise the 6th buffer zone 3423, and standby each other with the 4th buffer zone 3421,34 of described the second logic devices deposit the data message of receiving in the 4th buffer zone 3421, when the 4th buffer zone 3421 is filled with, by remaining data information memory to the six buffer zones 3423, and further store follow-up message, after data message in the 4th buffer zone 3421 sends, as the standby buffer zone of the 6th buffer zone 3423, the two alternately backups each other.
Suppose when system initialization the payload capacity Pay load size(TLP size of a TLP in PCIE bus) be 256 bytes, MTU MTU is 1500 bytes, according to the formula rounding up:
((MTU+TLP size-1)/TLP size) * TLP size, the size that calculates the first buffer zone 3221 of the first logical device 32 is 1536 bytes.
Suppose that it is 512 bytes that CPU31 sends first data flow, the first logical device 32 deposits the first buffer zone 3221 in data message, be not filled with, and the descending transmission BD message of constructing its correspondence deposits the second buffer zone 3222 in, in PCIE bus, do not initiate any operation;
It is 512 bytes that CPU sends second data flow, the first logical device 32 continues to deposit in the first buffer zone 3221 data message, be not filled with (being now 1024 bytes), and the descending transmission BD that constructs its correspondence continues to deposit in the second buffer zone 3222, still inoperation in PCIE bus;
It is 1024 bytes that CPU sends the 3rd data flow, and the first logical device 32 continues to deposit in the first buffer zone 3221 data message, and the descending transmission BD that constructs its correspondence deposits the second buffer zone 3222 in.Now the first buffer zone 3221 is filled with the first logical device 32 front 512 bytes of the first two message of the first buffer zone 3221 and the 3rd message is sent; Then in PCIE bus, send again a TLP message, comprise the descending transmission BD that the first two data message is corresponding.In addition, the descending transmission BD that the first logical device exists the 3rd buffer zones 3223 remaining 512 bytes of the 3rd data flow and constructs its correspondence deposits the second buffer zone 3222 in, if the first logical device 32 no longer receives new message, the data message of 512 bytes in the 3rd buffer zone 3223 is built to a TLP message BD message corresponding with it and send together.The second logical device 34 is received after TLP message, and data message is deposited in to buffer unit 342 according to descending transmission BD cutting data, and the complete data message of every reduction starts interface and sends to Service Interface Card 35.
In order to guarantee that data message transmits in time, can be respectively for the buffer zone of store data information in buffer unit, in Fig. 7, the data buffer storage region of the first buffer zone 3221, the 3rd buffer zone 3223, the 4th buffer zone 3421 and the 6th buffer zone 3423 these classes arranges a timer.When described data buffer storage region starts to receive data, start a timer, the duration of timer is N system clock cycle.If before timer expiry, the data of buffer zone are filled with, and the data of buffer zone and corresponding BD message are sent, and delete timer; If when timer expiry, buffer zone is not also filled with, also start PCIE bus the middle data of buffer zone and corresponding BD are sent, then delete timer.
Wherein, the ratio of the transmission rate of the size that the duration of described timer is buffer zone and PCIE bus, and be the clock cycle N doubly, N is integer.The calculating of N meets following principle:
N/Sysclock Frequency>RAM size/Line Rate, that is to say, when the transmission rate of data flow is during lower than general linear speed, in PCIE bus, accordingly the requirement of effective bandwidth utilance has also been reduced, can adopt this time original mode to transmit in PCIE bus, the message that allows a TLP message to carry is less than TLP size.This device that is arranged so that like this can be adjusted data transfer mode according to the actual conditions of communication system, thereby realizes the high efficiency of transmission in various situations.
According to the scheme of the embodiment of the present invention, in PCIE bus, transmit the performance of 64 byte parcels:
Sending direction, 24 messages of every transmission (26 * 64=1536, forms a RAM piece, corresponding 1536/256=6 TLP size), 6 TLP messages of descending generation; Then 24 descending transmission BD produce a TLP message; Downlink message length 1536 bytes, downlink data total length 6 * (256+24)+(24 * 8+24)=1896 byte, corresponding, confirm that BD message takies upstream bandwidth 24 * 8+24=216 byte;
Receive direction, similarly, every 1536 bytes of uplink message take upstream bandwidth 1896 bytes;
When finally, 64 byte parcels transmit, the valid data bandwidth availability ratio of PCIE bus is: 1536/(1896+216)=72%.Than former scheme, for the PCIE bus of a 20G bandwidth, parcel transmission performance can rise to 11.6G from 6.72G.
As can be seen here, by the FPGA with RAM piece, discontinuous data flow on address is converted to data flow continuous on address, realize the fully loaded transmission of TLP message in PCIE bus.Reduce the quantity of TLP message, promoted the valid data bandwidth of PCIE bus.
The foregoing is only preferred embodiment of the present invention, in order to limit the present invention, within the spirit and principles in the present invention not all, any modification of making, be equal to replacement, improvement etc., within all should being included in the scope of protection of the invention.
Claims (9)
1. a communicator, comprise CPU, it is characterized in that: described device further comprises the first logical device, the second logical device, PCIE Switch and Service Interface Card, wherein said the second logical device is on Service Interface Card, the first logical device is connected with CPU by point-to-point bus, the first logical device is connected by PCIE Switch with the second logical device, the first logical device and the second logical device all comprise buffer unit and resolution unit, and wherein the buffer unit of the first logical device comprises the first buffer zone and the second buffer zone;
The buffer unit of the first logical device receives after the downlink data message of CPU transmission, peel off control information, data message is existed to the first buffer zone, and resolution unit is resolved control information, and the descending transmission buffer memory descriptor BD that structure is corresponding deposits the second buffer zone of buffer unit in; When the first buffer zone is filled with, data message in the first buffer zone is sent to the buffer unit of the second logical device, and descending transmission BD corresponding to data message sent to the buffer unit of the second logical device by BD message, wherein, described BD message comprises an above BD;
The buffer unit of the second logical device receives after data message, according to the BD information of descending transmission BD message, data message is reduced to one or more data messages and is sent by Service Interface Card; After being sent completely, replying one and confirm that BD message is to the first logical device, wherein, described confirmation BD message comprises the confirmation BD for a described above BD.
2. communicator as claimed in claim 1, it is characterized in that, when the first buffer zone is filled with, the buffer unit that the descending transmission BD message of the data message in the first buffer zone and correspondence is sent to the second logical device specifically comprises, described the first logical device is write the data message of the first buffer zone the buffer unit of the second logical device, and descending transmission BD corresponding to data message sent to the buffer unit of the second logical device by BD message.
3. communicator as claimed in claim 1, it is characterized in that, when the first buffer zone is filled with, the buffer unit that the descending transmission BD message of the data message in the first buffer zone and correspondence is sent to the second logical device specifically comprises, described the first logical device is issued the buffer unit of the second logical device by the descending transmission BD corresponding with the first buffer zone data message by BD message, the second logical device is sent out read request according to BD to the first logical device, the first logical device response read request sends to the corresponding data information of the first buffer zone the buffer unit of the second logical device.
4. communicator as claimed in claim 1, is characterized in that, the control information of described data message is included in header SOP/ telegram end EOP indication.
5. communicator as claimed in claim 1, it is characterized in that, the buffer unit of described the second logical device comprises the 4th buffer zone and the 5th buffer zone, when described the second logical device receives after the uplink data messages of Service Interface Card transmission, peel off control information, data message is put into the 4th buffer zone, resolution unit is resolved control information, construct up transmission BD and deposit the 5th buffer zone in, when the 4th buffer zone is filled with, data message in the 4th buffer zone and corresponding up transmission BD are sent to the buffer unit of the first logical device by BD message, wherein, described BD message comprises an above BD,
The buffer unit of the first logical device receives after data message, according to descending transmission BD information, data message is reduced into one or more data messages, sends to CPU.
6. communicator as claimed in claim 1, it is characterized in that, described the first logical device further comprises the 3rd buffer zone, and standby each other with the first buffer zone, described the first logical device deposits the data message of receiving in first buffer zone, when the first buffer zone has been filled with, follow-up data information is stored in to the 3rd buffer zone, after the data message in the first buffer zone sends as the standby buffer zone of the 3rd buffer zone.
7. communicator as claimed in claim 5, it is characterized in that, described the second logical device further comprises the 6th buffer zone, and standby each other with the 4th buffer zone, described the second logical device deposits the data message of receiving in the 4th buffer zone, when the 4th buffer zone has been filled with, follow-up data information is stored in to the 6th buffer zone, after the data message in the 4th buffer zone sends as the standby buffer zone of the 6th buffer zone.
8. the communicator as described in as arbitrary in claim 1 to 7, it is characterized in that, while starting to deposit data message in data buffer storage region, start timer, when this buffer zone is filled with or timer expiry, the data message of this buffer zone and descending transmission BD corresponding to data message are sent and delete timer by BD message.
9. communicator as claimed in claim 8, is characterized in that, the duration of described timer is that the ratio of the size in data buffer storage region and the transmission rate of PCIE bus rounds up a clock cycle.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310514176.4A CN103546394B (en) | 2013-10-25 | 2013-10-25 | Communication device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310514176.4A CN103546394B (en) | 2013-10-25 | 2013-10-25 | Communication device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103546394A true CN103546394A (en) | 2014-01-29 |
| CN103546394B CN103546394B (en) | 2017-05-10 |
Family
ID=49969458
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310514176.4A Active CN103546394B (en) | 2013-10-25 | 2013-10-25 | Communication device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103546394B (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104901904A (en) * | 2015-04-22 | 2015-09-09 | 上海昭赫信息技术有限公司 | Method and device for transmitting data from PCIE acceleration sub card to host |
| CN105022699A (en) * | 2015-07-14 | 2015-11-04 | 惠龙易通国际物流股份有限公司 | Cache region data preprocessing method and system |
| CN106453018A (en) * | 2016-11-28 | 2017-02-22 | 天津光电通信技术有限公司 | A communication platform and communication method based on PCIe Switch |
| CN107525955A (en) * | 2017-07-07 | 2017-12-29 | 珠海格力电器股份有限公司 | Ammeter data processing method and device |
| CN108170373A (en) * | 2017-12-19 | 2018-06-15 | 北京云知声信息技术有限公司 | A kind of data cache method, device and data transmission system |
| CN109361607A (en) * | 2018-10-15 | 2019-02-19 | 迈普通信技术股份有限公司 | List item data capture method, device and communication equipment |
| CN112887319A (en) * | 2021-02-01 | 2021-06-01 | 上海帆一尚行科技有限公司 | Network state monitoring method and device based on downlink traffic and electronic equipment |
| CN113973039A (en) * | 2020-07-24 | 2022-01-25 | 深圳市中兴微电子技术有限公司 | Data processing method, device, equipment and storage medium |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030065735A1 (en) * | 2001-10-02 | 2003-04-03 | Connor Patrick L. | Method and apparatus for transferring packets via a network |
| US6647443B1 (en) * | 2000-12-28 | 2003-11-11 | Intel Corporation | Multi-queue quality of service communication device |
| CN101202707A (en) * | 2007-12-03 | 2008-06-18 | 杭州华三通信技术有限公司 | Method for transmitting message of high speed single board, field programmable gate array and high speed single board |
| CN103064807A (en) * | 2012-12-17 | 2013-04-24 | 福建星网锐捷网络有限公司 | Multi-channel direct memory access controller |
| CN103218313A (en) * | 2013-04-02 | 2013-07-24 | 杭州华三通信技术有限公司 | Method and electric device for interacting cache descriptors |
-
2013
- 2013-10-25 CN CN201310514176.4A patent/CN103546394B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6647443B1 (en) * | 2000-12-28 | 2003-11-11 | Intel Corporation | Multi-queue quality of service communication device |
| US20030065735A1 (en) * | 2001-10-02 | 2003-04-03 | Connor Patrick L. | Method and apparatus for transferring packets via a network |
| CN101202707A (en) * | 2007-12-03 | 2008-06-18 | 杭州华三通信技术有限公司 | Method for transmitting message of high speed single board, field programmable gate array and high speed single board |
| CN103064807A (en) * | 2012-12-17 | 2013-04-24 | 福建星网锐捷网络有限公司 | Multi-channel direct memory access controller |
| CN103218313A (en) * | 2013-04-02 | 2013-07-24 | 杭州华三通信技术有限公司 | Method and electric device for interacting cache descriptors |
Cited By (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104901904A (en) * | 2015-04-22 | 2015-09-09 | 上海昭赫信息技术有限公司 | Method and device for transmitting data from PCIE acceleration sub card to host |
| CN105022699A (en) * | 2015-07-14 | 2015-11-04 | 惠龙易通国际物流股份有限公司 | Cache region data preprocessing method and system |
| CN105022699B (en) * | 2015-07-14 | 2018-04-24 | 惠龙易通国际物流股份有限公司 | The preprocess method and system of buffer area data |
| CN106453018A (en) * | 2016-11-28 | 2017-02-22 | 天津光电通信技术有限公司 | A communication platform and communication method based on PCIe Switch |
| CN107525955A (en) * | 2017-07-07 | 2017-12-29 | 珠海格力电器股份有限公司 | Ammeter data processing method and device |
| CN108170373B (en) * | 2017-12-19 | 2021-01-05 | 云知声智能科技股份有限公司 | Data caching method and device and data transmission system |
| CN108170373A (en) * | 2017-12-19 | 2018-06-15 | 北京云知声信息技术有限公司 | A kind of data cache method, device and data transmission system |
| CN109361607A (en) * | 2018-10-15 | 2019-02-19 | 迈普通信技术股份有限公司 | List item data capture method, device and communication equipment |
| CN109361607B (en) * | 2018-10-15 | 2021-09-17 | 迈普通信技术股份有限公司 | Method and device for acquiring table item data and communication equipment |
| CN113973039A (en) * | 2020-07-24 | 2022-01-25 | 深圳市中兴微电子技术有限公司 | Data processing method, device, equipment and storage medium |
| WO2022017236A1 (en) * | 2020-07-24 | 2022-01-27 | 中兴通讯股份有限公司 | Data processing method and apparatus, and device and storage medium |
| US12244445B2 (en) | 2020-07-24 | 2025-03-04 | Sanechips Technology Co., Ltd. | Data processing method and apparatus, and device and storage medium |
| CN112887319A (en) * | 2021-02-01 | 2021-06-01 | 上海帆一尚行科技有限公司 | Network state monitoring method and device based on downlink traffic and electronic equipment |
| CN112887319B (en) * | 2021-02-01 | 2022-07-01 | 上海帆一尚行科技有限公司 | Network state monitoring method and device based on downlink traffic and electronic equipment |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103546394B (en) | 2017-05-10 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103546394A (en) | Communication device | |
| US20200174953A1 (en) | Methods and apparatus for synchronizing uplink and downlink transactions on an inter-device communication link | |
| TWI575918B (en) | Apparatus, method and non-transitory computer-readable storage medium utilizing time division operations | |
| US10567194B2 (en) | User station for a bus system and method for increasing the transmission capacity in a bus system | |
| CN111405534B (en) | Information transmission method, first terminal and computer storage medium | |
| CN205545305U (en) | Based on dark embedded data interchange device of xilinx FPGA | |
| CN201639589U (en) | Embedded dual-redundant network card based on ARM | |
| CN105657017A (en) | Data transmission method, device and system | |
| CN104780118B (en) | A kind of flow control method and device based on token | |
| CN103617132B (en) | A kind of ethernet terminal based on shared storage sends implementation method and terminal installation | |
| CN101478462B (en) | Apparatus and method for storage data reading and writing, solid hard disk | |
| CN109446126A (en) | DSP and FPGA high-speed communication system and method based on EMIF bus | |
| CN102566959A (en) | Image segmentation processing method and device thereof based on SGDMA (scatter gather direct memory access) | |
| CN106936677A (en) | A kind of data transmission method of Modular UPS system and power apparatus | |
| US9354696B2 (en) | Credit based power management | |
| CN104486187B (en) | A kind of CAN communication device and method of dynamic synchronization | |
| CN101079815B (en) | Message forwarding method, system and device | |
| CN104714832A (en) | Buffer management method used for airborne data network asynchronous data interaction area | |
| CN103051612A (en) | Firewall and method for preventing network attack | |
| CN102420734A (en) | CAN bus topological structure implementation system | |
| CN106657097B (en) | A kind of data transmission method for uplink and device | |
| CN109586931A (en) | Method of multicasting and terminal device | |
| WO2012058875A1 (en) | Method and system for serial communication | |
| CN103761065B (en) | Data output method and device | |
| CN102546422A (en) | Message forwarding method in exchange chip, exchange chip and network device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| CB02 | Change of applicant information | ||
| CB02 | Change of applicant information |
Address after: 310052 Binjiang District Changhe Road, Zhejiang, China, No. 466, No. Applicant after: Xinhua three Technology Co., Ltd. Address before: 310053 Hangzhou hi tech Industrial Development Zone, Zhejiang province science and Technology Industrial Park, No. 310 and No. six road, HUAWEI, Hangzhou production base Applicant before: Huasan Communication Technology Co., Ltd. |
|
| GR01 | Patent grant | ||
| GR01 | Patent grant |