CN103579012B - Tape welding spherical array flat-four-side pin-less packaging part production method - Google Patents
Tape welding spherical array flat-four-side pin-less packaging part production method Download PDFInfo
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- CN103579012B CN103579012B CN201310508832.XA CN201310508832A CN103579012B CN 103579012 B CN103579012 B CN 103579012B CN 201310508832 A CN201310508832 A CN 201310508832A CN 103579012 B CN103579012 B CN 103579012B
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 43
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 42
- 238000003466 welding Methods 0.000 title claims abstract description 21
- 238000002161 passivation Methods 0.000 claims abstract description 88
- 239000002184 metal Substances 0.000 claims abstract description 83
- 229910052751 metal Inorganic materials 0.000 claims abstract description 83
- 239000010949 copper Substances 0.000 claims abstract description 80
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 79
- 229910052802 copper Inorganic materials 0.000 claims abstract description 79
- 238000004544 sputter deposition Methods 0.000 claims abstract description 26
- 239000011248 coating agent Substances 0.000 claims abstract description 22
- 238000000576 coating method Methods 0.000 claims abstract description 22
- 238000000227 grinding Methods 0.000 claims abstract description 20
- 238000012360 testing method Methods 0.000 claims abstract description 10
- 238000000926 separation method Methods 0.000 claims abstract description 5
- 229920002120 photoresistant polymer Polymers 0.000 claims description 33
- 239000011265 semifinished product Substances 0.000 claims description 31
- 238000005530 etching Methods 0.000 claims description 28
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 25
- 238000005192 partition Methods 0.000 claims description 20
- 238000000034 method Methods 0.000 claims description 19
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 12
- 229910052759 nickel Inorganic materials 0.000 claims description 12
- 239000010931 gold Substances 0.000 claims description 11
- 229910000679 solder Inorganic materials 0.000 claims description 11
- 238000005476 soldering Methods 0.000 claims description 10
- 238000011049 filling Methods 0.000 claims description 9
- 238000005516 engineering process Methods 0.000 claims description 8
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 8
- 229910052737 gold Inorganic materials 0.000 claims description 8
- 238000007639 printing Methods 0.000 claims description 8
- 238000007711 solidification Methods 0.000 claims description 8
- 230000008023 solidification Effects 0.000 claims description 8
- 238000005520 cutting process Methods 0.000 claims description 7
- 238000011161 development Methods 0.000 claims description 6
- 239000000945 filler Substances 0.000 claims description 6
- 238000010521 absorption reaction Methods 0.000 claims description 5
- 238000001259 photo etching Methods 0.000 claims description 5
- 230000005540 biological transmission Effects 0.000 claims description 4
- 239000000203 mixture Substances 0.000 claims description 3
- 239000005022 packaging material Substances 0.000 claims description 3
- 238000005498 polishing Methods 0.000 claims description 3
- 239000007921 spray Substances 0.000 claims description 3
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 3
- 230000007797 corrosion Effects 0.000 claims description 2
- 238000005260 corrosion Methods 0.000 claims description 2
- 239000012943 hotmelt Substances 0.000 claims description 2
- 238000005538 encapsulation Methods 0.000 abstract description 12
- 239000000758 substrate Substances 0.000 abstract description 5
- 239000000047 product Substances 0.000 description 7
- 238000003384 imaging method Methods 0.000 description 3
- 239000002253 acid Substances 0.000 description 2
- 238000004026 adhesive bonding Methods 0.000 description 2
- 238000013400 design of experiment Methods 0.000 description 2
- 238000013401 experimental design Methods 0.000 description 2
- 238000012827 research and development Methods 0.000 description 2
- 238000007789 sealing Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005253 cladding Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 238000005507 spraying Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Ceramic Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Dicing (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
A kind of tape welding spherical array flat-four-side pin-less packaging part production method, band salient point wafer reduction scribing；Bare copper frame resist coating；Bare copper frame is formed the second groove；Being coated with the first passivation layer, the first passivation layer of the second bottom portion of groove etches UBM1Window；High-frequency sputtering complex metal layer；Chip bump is made to enter the second groove and connect UBM1Layer；Solidify after plastic packaging；The grinding framework back side is coated with the second passivation layer, etched recesses；Coat the 3rd passivation layer；Etch the second pattern groove；Sputtering the first metal layer, etches the 4th groove；3rd passivation layer surface is coated with the 4th passivation layer, etches the 5th groove；In 5th groove, all sputtering forms UBM2Layer；Plant ball, print, cut separation and test, obtain tape welding spherical array flat-four-side pin-less packaging part.This production method can substitute the CPS of substrate production, it is achieved IC chip is flexibly applied to the CSP encapsulation of lead frame；Reduce the thickness of framework, meet thin encapsulation requirement.
Description
Technical field
The invention belongs to electronic information Element of automatic control technical field, relate to a kind of AAQFN package production method, be specifically related to a kind of tape welding spherical array flat-four-side without pin (AAQFN) packaging part production method.
Background technology
For a long time, being limited by etching template and etch process technology, conventional QFN product continues up individual pen (1 circle) the lead frame pattern of the exploitation nineties in 20th century.Owing to being limited in individual pen encapsulation, therefore pins of products is few, and I/O is few, can not meet high density, the demand of many I/O encapsulation.Nearly 2 years domestic research and development multi-turns QFN that have started to, but owing to frame manufacturing process difficulty is relatively big, only indivedual international vendors can design, produce, and limited by associated companies patent, and relative pin is less, and the R&D cycle is long.Therefore, although compare the BGA package using substrate production soldered ball as output, lead frame multi-turn QFN packaging efficiency is high, and cost is relatively low, use encapsulation flexibly, but multi-turn QFN is limited to lead frame manufacturer, it is impossible to meet the requirement of the flexible Application of short, flat, fast and different chip.
Summary of the invention
It is an object of the invention to provide a kind of tape welding spherical array flat-four-side pin-less packaging part production method, break away from the restriction of lead frame manufacturer, produce and meet the packaging part that short, flat, fast and different chip flexible Application requires.
For achieving the above object, the technical solution adopted in the present invention is: a kind of tape welding spherical array flat-four-side pin-less packaging part production method, specifically sequentially includes the following steps:
Step 1: the wafer of thinning band salient point, scribing, form IC chip；
Uniformly coat photoresist on the surface of bare copper frame, form photoresist layer, then toast 25 ± 5 minutes at a temperature of 60 DEG C～70 DEG C；
Step 2: photoresist layer is carried out alignment exposure, then development, fixing, remove exposure area photoresist, make on photoresist layer, to form multiple the first groove side by side, the bare copper frame of each first groove position exposes, post bake afterwards；
Step 3: the bare copper frame part exposed under spray corrosion the first groove so that bare copper frame front forms multiple the second groove side by side, has partition wall, then remove remaining photoresist layer between adjacent two second grooves；
Step 4: uniformly coat the first passivation layer on the surface on bare copper frame surface and all second grooves, then etch UBM on the first passivation layer of all second bottom portion of groove1Window；
Step 5: use high-frequency sputtering at all of UBM1In window and the first passivation layer surface high-frequency sputtering copper metal layer of the second groove surfaces, the two ends of copper metal layer lay respectively on first passivation layer on bare copper frame surface, then sputter nickel metal layer in copper metal layer surface high frequency, then sputter gold metal layer in nickel metal layer surface high frequency；Copper metal layer, nickel metal layer and gold metal layer composition UBM1Layer；By photoetching, etching step, removing unnecessary metal level, the UBM1 layer formed in making adjacent two the second grooves does not contacts, and obtains semi-finished product lead frame；
Step 6: take the IC chip that step 1 prepares, by core in this IC flip-chip on the semi-finished product lead frame of step 5, makes chip bump enter in the second groove and and UBM1It is connected bottom Ceng, then fills the space between adjacent chip bump and chip bump and UBM with lower filler1Space between Ceng；
Step 7: plastic packaging and after solidify；
Step 8: grinding, by the semi-finished product lead frame back side after plastic packaging and rear solidification, is cleaned, dried；
Step 9: bare copper frame backside coating the second passivation layer after grinding；Then be exposed, develop, fixing, then on the second passivation layer, etch the first pattern groove, each partition wall is corresponding first pattern groove at the lead frame back side；
Step 10: perform etching the first pattern groove again, forms the 3rd groove communicated with partition wall；
Step 11: coating the 3rd passivation layer, the 3rd passivation layer not only covers the back side of semi-finished product lead frame, and fills up this all of groove in semi-finished product lead frame back side；Then etching the second pattern groove on the 3rd passivation layer, the position at the second pattern groove place is position, pin bottom surface and the place needing copper cash framework to expose；
Step 12: the 3rd passivation layer surface is at sputtering the first metal layer, and the first metal layer is further filled with all of second graph groove simultaneously, etches the 4th groove the most on the first metal layer；
Step 13: coat the 4th passivation layer in the 3rd passivation layer surface, and make the 4th passivation layer be full of all of 4th groove, then etch the 5th groove on the 4th passivation layer；
Step 14: all sputter multiple layer metal in all of 5th groove, forms UBM2Layer；
Step 15: reflow soldering stannum ball and UBM2Layer, cleans；
Step 16: use existing technique to carry out printing, cutting separation and test, obtain tape welding spherical array flat-four-side pin-less packaging part.
Production method of the present invention can substitute for the CSP(Chip-Scale Package of substrate production, wafer-level package), it is achieved IC chip is flexibly applied to the CSP encapsulation of lead frame；Its production cost and construction cycle, far below substrate package, there is bigger advantage.Break away from the restriction of lead frame manufacturer, produce the packaging part that short, flat, fast and different chip flexible Application requires, reduce the thickness of framework, meet thin encapsulation requirement.
Accompanying drawing explanation
Fig. 1 is the generalized section coating photoresist in production method of the present invention on bare copper frame.
Fig. 2 is the generalized section that in production method of the present invention, exposure imaging makes pattern post bake.
Fig. 3 is the generalized section etching groove in production method of the present invention on bare copper frame.
Fig. 4 is to coat the first passivation layer in production method of the present invention on bare copper frame and carve the generalized section of UBM1 window.
Fig. 5 is that in production method of the present invention, in groove, high-frequency sputtering multiple layer metal forms the generalized section of UBM1 layer.
Fig. 6 is the big figure of P prescription in Fig. 5.
Fig. 7 is core and the generalized section of lower filling in upside-down mounting in production method of the present invention.
Fig. 8 is plastic packaging and the generalized section of rear solidification in production method of the present invention.
Fig. 9 is the generalized section after coating the second passivation layer in production method of the present invention and etching.
Figure 10 is that in production method of the present invention, lead frame back-etching goes out the 3rd groove and removes the generalized section of the second passivation layer.
Figure 11 is to coat the 3rd passivation layer in production method of the present invention and etch the generalized section of the 4th groove.
Figure 12 is in the 3rd passivation layer surface metal cladding the generalized section that etches the 4th groove in production method of the present invention.
Figure 13 is to coat the 4th passivation layer in production method of the present invention and etch the generalized section of the 5th groove.
Figure 14 is the generalized section that in production method of the present invention, bottom sputtering multiple layer metal forms UBM2 layer；
Figure 15 is the generalized section after planting ball, Reflow Soldering in production method of the present invention.
In figure: 1. bare copper frame, 2. photoresist layer, 3. the first groove, 4. the second groove, 5. partition wall, 6. the first passivation layer, 7.UBM1Window, 8.UBM1Layer, 9.IC chip, 10. chip bump, 11. times fillers, 12. solders, 13. plastic-sealed bodies, 14. second passivation layers, 15. first pattern groove, 16. the 3rd grooves, 17. the 3rd passivation layers, 18. second pattern groove, 19. the first metal layers, 20. the 4th grooves, 21. the 4th passivation layers, 22. the 5th grooves, 23.UBM2Layer, 24. stannum balls, a.Cu metal level, b.Ni metal level, c.Au metal level.
Detailed description of the invention
The present invention is described in detail with detailed description of the invention below in conjunction with the accompanying drawings.
The flow process of this production method is as follows:
Bare copper frame gluing → exposure imaging post bake → etch the second groove → coat the first passivation layer and carve UBM1Window → high-frequency sputtering multiple layer metal forms UBM1Core and lower filling → plastic packaging and rear solidification → framework back side grinding in layer → upside-down mounting → coat the second passivation layer also etches the first pattern groove → lead frame bottom surface etching the 3rd groove → coating the 3rd passivation layer and etches the second pattern groove → high-frequency sputtering the first metal layer and etch the 4th groove → coating the 4th passivation layer and etch five grooves → bottom and sputter multiple layer metal formation UBM2Layer → plant ball.
The production method of the face array flat-four-side pin-less packaging part of the band soldered ball that the present invention provides, specifically sequentially includes the following steps:
Step 1: wafer reduction scribing, coating photoresist on bare copper frame
Use the thinning machine of 8～12, use corase grind, thin fine-grinding and polishing warpage preventing technique, the wafer of band salient point is thinned to 200～250 μm, roughly grind speed 6 μm/s, refine speed 1.0 μm/s；A-WD-300TXB scribing machine is used to carry out scribing, scribing feed velocity≤10mm/s；Form IC chip 9；
Use sol evenning machine or coating machine, uniformly coat a layer thickness in the front of bare copper frame 1 and be at least the photoresist (positive negativity) of 10 μm, form photoresist layer 2, as it is shown in figure 1, then toast 25 ± 5 minutes at a temperature of 60 DEG C～70 DEG C；
Step 2: exposure imaging post bake
The bare copper frame 1 having been coated with photoresist is carried out alignment exposure by exposure machine, then development, fixing, remove the photoresist of exposure area, make on photoresist layer 2, to form multiple the first groove 3 side by side, the bare copper frame 1 of each first groove 3 position exposes, bare copper frame 1 region exposed demonstrates pattern, afterwards post bake 30 ± 5 seconds at a temperature of 120 DEG C ± 5 DEG C, as shown in Figure 2；
Step 3: etch the second groove
Bare copper frame 1 after post bake is placed in etching, cleans on all-in-one, make photoresist layer 2 upwards, spray downwards corrosive liquid (acid or alkalescence), the figure of needs is gone out in bare copper frame 1 front-side etch exposed, multiple the second groove 4 side by side is i.e. formed in bare copper frame 1 front, there is partition wall 5 between adjacent two second grooves 4, then remove remaining photoresist layer 2, as shown in Figure 3；
Step 4: coat the first passivation layer and etching UBM1Window
Use coating machine, uniformly coat the first passivation layer 6 on the surface on bare copper frame 1 surface and all second grooves 4 that etch figure, then on the first passivation layer 6 of the bottom of all second grooves 4, etch UBM1Window 7, such as Fig. 4；
Step 5: growth UBM1Layer
Use high-frequency sputtering method at all of UBM1The first passivation layer 6 surface high frequency sputtering copper metal layer a in window 7 and the second groove 4 surface, the two ends of copper metal layer a lay respectively on first passivation layer 6 on bare copper frame 1 surface, then sputter nickel metal layer b in copper metal layer a surface high frequency, then sputter gold metal layer c in nickel metal layer b surface high frequency；Copper metal layer a, nickel metal layer b and gold metal layer c form UBM1Layer 8, UBM1Layer 8 is high-frequency sputtering Cu-Ni-Au layer；By photoetching, etching step, remove unnecessary metal level, the UBM formed in making adjacent two the second grooves 41Layer 8 does not contacts, and obtains semi-finished product lead frame, as shown in Figure 5 and Figure 6；
Step 6: core and lower filling in upside-down mounting
Take the IC chip 9 that step 1 prepares, on chip bump 10, be first stained with solder 12, use upside-down mounting chip feeder, by core in this IC chip 9 upside-down mounting on the semi-finished product lead frame of step 5, in making chip bump 10 enter the second groove 4 and with the second groove 4 bottom UBM1Layer 8 is connected, and then fills in the second groove 4 space between chip bump 10 and chip bump 10 and UBM with lower filler 111Space between layer 8, lower filler 11 plays insulating effect, makes to insulate, such as Fig. 7 between the salient point on IC chip 9 and salient point；
Core and lower fill process in upside-down mounting: on special upside-down mounting chip feeder, first chip is overturn, after being stained with solder, automatically alignment is placed into UBM(metalization under bump corresponding on the bare copper frame 1 of core in upside-down mounting, metallize under salient point) position, on whole piece framework after complete chip, automatically income transmission box, in flip-chip, Reflow Soldering operation delivered to by semi-finished product lead frame transmission box after core by the gross.By DOE (Design of
Experiment, EXPERIMENTAL DESIGN) test under the thermal reflow profile determined, by UBM corresponding on stannum salient point, solder and the lead frame on chip by Reflow Soldering hot melt, chip is firmly welded together with the UBM on lead frame, directly instead of traditional upper core and bond technology.
Choosing the most lower inserts (less implant) by DOE (Design of Experiment, EXPERIMENTAL DESIGN) test, lower filling mould has Incision Machine's.Under vac sorb so that the space between chip bump and salient point can be sufficiently filled up completely with by lower inserts, will not have cavity, prevent soldered ball from shifting at high temperature.
Step 7: plastic packaging and after solidify
Use full-automatic sealing machine, use low stress (a1≤ 1) the environment-friendly type plastic packaging material meeting European Union's Weee, ROHS standard and SoNY standard of, low moisture absorption (water absorption rate < 0.25%) carries out plastic packaging to the semi-finished product lead frame after core in step 6 upside-down mounting, plastic-sealed body 13 is formed in bare copper frame 1 front, IC chip 9 and bare copper frame 1 front are all packaged in plastic-sealed body 13, as shown in Figure 8, solidify after then carrying out by general anti-absciss layer technique；
Step 8: the grinding bare copper frame back side
On equipment for grinding, to the semi-finished product lead frame back side after solidification after plastic packaging, i.e. the back side of bare copper frame 1 carries out grinding, grinding thichness 0.03mm～0.035mm, then cleans, dries；
Step 9: coat the second passivation layer and etch the first pattern groove
Use coating exposure all-in-one, bare copper frame 1 backside coating the second passivation layer 14 after grinding；Then be exposed on litho machine, develop, fixing, the first pattern groove 15 is etched again on the second passivation layer 14, each partition wall 5 correspondence position on the second passivation layer 14 all has first pattern groove 15, first pattern groove 15 of i.e. one partition wall 5 correspondence, it is positioned at the underface of this partition wall 5, as shown in Figure 9；
Step 10: framework etches
The semi-finished product lead frame that the framework back side the second passivation layer 14 etches the first pattern groove 15 performs etching again, remove the metal between the first pattern groove 15 that partition wall 5 is corresponding with this partition wall 5, forming the 3rd groove 16, as shown in Figure 10, the 3rd groove 16 communicates with partition wall 5；
Step 11: coating the 3rd passivation layer also etches the second pattern groove
On covering and answering a pager's call, having given backside coating the 3rd passivation layer 17 of the semi-finished product lead frame of step 10, the 3rd passivation layer 17 not only covers the back side of semi-finished product lead frame, fills up again this all of 3rd groove 16 in semi-finished product lead frame back side；Then etching the second pattern groove 18 on the 3rd passivation layer 17, the position at the second pattern groove 18 place is position, pin bottom surface and the place needing copper cash framework 1 to expose；
Step 12: splash-proofing sputtering metal layer
Complete the semi-finished product lead frame back spatter the first metal layer 19 of step 11, the first metal layer 19 is positioned at the 3rd passivation layer 17 surface, and is full of all of second graph groove 18, then etches the 4th groove 20 on the first metal layer 19, as shown in figure 12, the first metal layer 19 is copper metal layer；
Step 13: coating the 4th passivation layer also etches the 4th groove
At the 3rd passivation layer 17 surface-coated the 4th passivation layer 21, and make the 4th passivation layer 21 be full of all of 4th groove 20, on the 4th passivation layer 21, then etch the 5th i.e. UBM of groove 22(2Window), as shown in figure 13；
Step 14: form UBM2
All sputtering multiple layer metal in all of 5th groove 22, this multiple layer metal fills all of 5th groove 22, forms UBM2Layer 23, as shown in figure 14；
Step 15: plant ball
By ball attachment machine, at the UBM at the semi-finished product lead frame back side completing step 142Brush solder on layer 23, then stannum ball 24 is placed on brush solder, makes stannum ball 24 and UBM by Reflow Soldering2Layer 23 strong bonded, clean；
Step 16: use the printing of QFN encapsulation and cutting separating technology to carry out printing, cutting separation, but stannum ball 24 need to be protected not damage；The product separated is tested by the test technology using BGA package, and certified products are the tape welding spherical array flat-four-side pin-less packaging part shown in Figure 15.
The wafer of this encapsulation is thinning, scribing and the printing of product, cutting separates, test uses the equipment identical with BGA package and technique.
This production method have employed the photoetching (plate-making, gluing, development, post bake) in chip manufacturing, etching.Front surface coated passivation layer, etching UBM1Window, high-frequency sputtering multiple layer metal form UBM1Layer.Use band salient point IC chip, use core and lower filling in the upside-down mounting in packaging technology, plastic packaging and rear curing process, complete packaging part front and produce.The framework back side uses grinding process, thin frame thickness, meets Ultrathin packaging.Continue to use the passivation of chip production and etch process, by coating the second passivation layer 14, etching the first pattern groove 15, continue etching the first pattern groove 15, formed the 3rd groove 16 communicated with partition wall 5 and, and remove the second passivation layer 14.Coat the 3rd passivation layer 17 and etch the second pattern groove 18, high-frequency sputtering metallic copper, form the first metal layer 19, the first metal layer 19 etches the 4th groove 20, coat the 4th passivation layer 21, etch the 5th groove 22(UBM2Window), high-frequency sputtering metal, in the 5th groove 22, form UBM2Layer 23.Use the general printing of encapsulation, plant ball reflow soldering process, make stannum ball 24 and UBM2Layer 23 strong bonded, prepare tape welding spherical array flat-four-side pin-less packaging part.Production method of the present invention can substitute the CPS of substrate production, it is achieved IC chip is flexibly applied to the CSP encapsulation of lead frame.
Embodiment
1
8～the 12 thinning machines of use, use corase grind, thin fine-grinding and polishing warpage preventing technique, and the wafer of band bump chip is thinned to 250 μm, roughly grind speed 6 μm/s, refine speed 1.0 μm/s；A-WD-300TXB scribing machine is used to carry out scribing, scribing feed velocity control≤10mm/s.On sol evenning machine, a surface of bare copper frame uniformly coats the photoresist of the positivity of a layer thickness 10 μm, form lithography layer, then toast 30 minutes at a temperature of 60 DEG C；The bare copper frame having been coated with photoresist layer is carried out alignment exposure by exposure machine, then carries out developing, fixing, bare copper frame demonstrates pattern, afterwards post bake 35 seconds at a temperature of 115 DEG C；In etching, clean on all-in-one, by spraying downwards acid etching solution, go out the figure needed in bare copper frame front-side etch, i.e. form multiple the second groove side by side in bare copper frame front, there is partition wall between adjacent two second grooves, and remove the photoresist layer of bare copper frame surface-coated；In coating machine, uniformly coat the first passivation layer on the bare copper frame surface and all second groove surfaces etching the second groove, the first passivation layer of all second groove floor etches UBM1Window；Use high-frequency sputtering at UBM1In window and the first passivation layer surface high-frequency sputtering copper metal layer of the second groove surfaces, the two ends of copper metal layer lay respectively on first passivation layer on bare copper frame surface, then sputter nickel metal layer in copper metal layer surface high frequency, then sputter gold metal layer in nickel metal layer surface high frequency；Copper metal layer, nickel metal layer and gold metal layer composition UBM1Layer, UBM1Layer is high-frequency sputtering Cu-Ni-Au layer；By photoetching, etching, remove unnecessary metal level, the UBM formed in making adjacent two the second grooves1Layer does not contacts, and obtains semi-finished product lead frame；Use upside-down mounting chip feeder, the IC chip of the band salient point that use scribing obtains, be first stained with solder at chip bump, then core lower filling in upside-down mounting on this semi-finished product lead frame, make chip bump and UBM1Bottom Ceng be connected, and by lower filler make between chip bump and chip bump between insulate；Use full-automatic sealing machine, use low stress (a1≤ 1), the meeting European Union's Weee, ROHS standard and the environment-friendly type plastic packaging material of SoNY standard, the semi-finished product lead frame after core in upside-down mounting carried out plastic packaging of low moisture absorption (water absorption rate < 0.25%), solidify after carrying out by general anti-absciss layer technique after plastic packaging；0.03mm is removed in the semi-finished product lead frame back side grinding of rear solidification, cleans, dry；Use coating exposure all-in-one, the semi-finished product lead frame back side after grinding, coating second layer passivation layer, be exposed, develop, fixing, the first pattern groove is etched again on the second passivation layer, each partition wall is corresponding first pattern groove, the first pattern groove of i.e. one partition wall 5 correspondence at the lead frame back side, is positioned at the underface of this partition wall 5；Continue etching the first pattern groove, form the 3rd groove communicated with partition wall；On covering and answering a pager's call, at backside coating the 3rd passivation layer of semi-finished product lead frame, the 3rd passivation layer not only covers the back side of semi-finished product lead frame, fills up again this all of groove in semi-finished product lead frame back side；Then etching the second pattern groove on the 3rd passivation layer, the position at the second pattern groove place is position, pin bottom surface and the place needing copper cash framework to expose；High-frequency sputtering the first metal layer on the 3rd passivation layer, the first metal layer is full of all of second graph groove simultaneously, etches the 4th groove the most on the first metal layer, and the first metal layer is copper metal layer；At the first metal layer surface-coated the 4th passivation layer, and it is full of all of 4th groove, the 4th passivation layer etches the 5th groove；Sputtering multiple layer metal in the 5th groove, this multiple layer metal fills all of 5th groove, forms UBM2Layer；By ball attachment machine, first at UBM2Brush solder on Ceng, then stannum ball is placed on brush solder, makes stannum ball and UBM by Reflow Soldering2Layer strong bonded, then be carried out, use the printing of QFN encapsulation and cutting separating technology to carry out printing, cutting separation, but stannum ball need to be protected not damage；The product separated is tested by the test technology using BGA package, and certified products are tape welding spherical array flat-four-side pin-less packaging part.
Embodiment
2
Wafer reduction scribing is with embodiment 1, and simply the wafer of band bump chip is thinned to 200 μm；A surface of bare copper frame uniformly coats the photoresist of the negativity of a layer thickness 20 μm, forms photoresist layer, then toast 20 minutes at a temperature of 70 DEG C；Carry out alignment exposure, then development, fixing, remove exposure area photoresist, make on photoresist layer, to form multiple the first groove side by side, the bare copper frame of each first groove position exposes, and the bare copper frame region exposed demonstrates pattern, afterwards post bake 30 seconds at a temperature of 120 DEG C；The method using embodiment 1 etches the second groove, coats the first passivation layer and etching UBM1Window, growth UBM1Layer, in upside-down mounting after core and lower filling, plastic packaging and rear solidification, by bare copper frame back side grinding 0.035mm, then prepare tape welding spherical array flat-four-side pin-less packaging part as described in Example 1.
Embodiment
3
Wafer reduction scribing is with embodiment 1, and simply the wafer of band bump chip is thinned to 225 μm；A surface of bare copper frame uniformly coats the photoresist of the negativity of a layer thickness 30 μm, forms photoresist layer, then toast 25 minutes at a temperature of 65 DEG C；Carry out alignment exposure, then development, fixing, remove exposure area photoresist, make on photoresist layer, to form multiple the first groove side by side, the bare copper frame of each first groove position exposes, and the bare copper frame region exposed demonstrates pattern, afterwards post bake 25 seconds at a temperature of 125 DEG C；The method using embodiment 1 etches the second groove, coats the first passivation layer and etching UBM1Window, growth UBM1Layer, in upside-down mounting after core and lower filling, plastic packaging and rear solidification, by bare copper frame back side grinding 0.033mm, then prepare tape welding spherical array flat-four-side pin-less packaging part as described in Example 1.
Although having shown that in conjunction with preferred embodiment and describing the present invention, it will be understood by those skilled in the art that on the premise of the spirit and scope of the present invention defined in the appended claims, can modify and convert.
Claims (7)
1. a tape welding spherical array flat-four-side pin-less packaging part production method, it is characterised in that specifically sequentially include the following steps:
Step 1: the wafer of thinning band salient point, scribing, form IC chip；
Uniformly coat photoresist on the surface of bare copper frame, form photoresist layer, then toast 25 ± 5 minutes at a temperature of 60 DEG C～70 DEG C；
Step 2: photoresist layer is carried out alignment exposure, then development, fixing, remove exposure area photoresist, make on photoresist layer, to form multiple the first groove side by side, the bare copper frame of each first groove position exposes, post bake afterwards；
Step 3: the bare copper frame part exposed under spray corrosion the first groove so that bare copper frame front forms multiple the second groove side by side, has partition wall, then remove remaining photoresist layer between adjacent two second grooves；
Step 4: uniformly coat the first passivation layer on the surface on bare copper frame surface and all second grooves, then etch UBM on the first passivation layer of all second bottom portion of groove1Window；
Step 5: use high-frequency sputtering at all of UBM1In window and the first passivation layer surface high-frequency sputtering copper metal layer of the second groove surfaces, the two ends of copper metal layer lay respectively on first passivation layer on bare copper frame surface, then sputter nickel metal layer in copper metal layer surface high frequency, then sputter gold metal layer in nickel metal layer surface high frequency；Copper metal layer, nickel metal layer and gold metal layer composition UBM1Layer；By photoetching, etching step, remove unnecessary metal level, the UBM formed in making adjacent two the second grooves1Layer does not contacts, and obtains semi-finished product lead frame；
Step 6: take the IC chip that step 1 prepares, by core in this IC flip-chip on the semi-finished product lead frame of step 5, makes chip bump enter in the second groove and and UBM1It is connected bottom Ceng, then fills the space between adjacent chip bump and chip bump and UBM with lower filler1Space between Ceng；
Step 7: plastic packaging and after solidify；
Step 8: grinding, by the semi-finished product lead frame back side after plastic packaging and rear solidification, is cleaned, dried；
Step 9: bare copper frame backside coating the second passivation layer after grinding；Then be exposed, develop, fixing, then on the second passivation layer, etch the first pattern groove, each partition wall is corresponding first pattern groove at the lead frame back side；
Step 10: perform etching the first pattern groove again, forms the 3rd groove communicated with partition wall；
Step 11: coating the 3rd passivation layer, the 3rd passivation layer not only covers the back side of semi-finished product lead frame, and fills up this all of groove in semi-finished product lead frame back side；Then etching the second pattern groove on the 3rd passivation layer, the position at the second pattern groove place is position, pin bottom surface and the place needing copper cash framework to expose；
Step 12: the 3rd passivation layer surface is at sputtering the first metal layer, and the first metal layer is further filled with all of second graph groove simultaneously, etches the 4th groove the most on the first metal layer；
Step 13: coat the 4th passivation layer in the 3rd passivation layer surface, and make the 4th passivation layer be full of all of 4th groove, then etch the 5th groove on the 4th passivation layer；
Step 14: all sputter multiple layer metal in all of 5th groove, forms UBM2Layer；
Step 15: reflow soldering stannum ball and UBM2Layer, cleans；
Step 16: use existing technique to carry out printing, cutting separation and test, obtain tape welding spherical array flat-four-side pin-less packaging part.
Tape welding spherical array flat-four-side pin-less packaging part production method the most according to claim 1, it is characterised in that in described step 1, use corase grind, thin fine-grinding and polishing warpage preventing technique, the wafer of band salient point is thinned to 200～250 μm, roughly grinds speed 6 μm/s, refine speed 1.0 μm/s；Feed velocity≤10mm/s during scribing.
Tape welding spherical array flat-four-side pin-less packaging part production method the most according to claim 1, it is characterised in that in described step 2, post bake 30 ± 5 seconds at a temperature of 120 DEG C ± 5 DEG C.
Tape welding spherical array flat-four-side pin-less packaging part production method the most according to claim 1, it is characterized in that, core and lower fill process in the upside-down mounting used in described step 6: on special upside-down mounting chip feeder, first chip is overturn, after being stained with solder, alignment is placed into UBM corresponding on the bare copper frame of core in upside-down mounting automatically1Position, on whole piece framework after complete chip, automatically income transmission box, in flip-chip, Reflow Soldering operation delivered to by semi-finished product lead frame transmission box after core by the gross；
Under the thermal reflow profile determined by DOE test, by UBM corresponding on stannum salient point, solder and the lead frame on chip1By Reflow Soldering hot melt so that chip and the UBM on lead frame1Firmly weld together, directly instead of traditional upper core and bond technology；
Choosing the most lower inserts by DOE test, lower filling mould has Incision Machine's；
Under vac sorb so that the space between chip bump and salient point can be sufficiently filled up completely with by lower inserts, will not have cavity, prevent soldered ball from shifting at high temperature.
Tape welding spherical array flat-four-side pin-less packaging part production method the most according to claim 1, it is characterized in that, in described step 7, < the environment-friendly type plastic packaging material of 0.25% carries out plastic packaging to the semi-finished product lead frame after core in step 6 upside-down mounting, solidifies after then carrying out by general anti-absciss layer technique to use stress≤1, water absorption rate.
Tape welding spherical array flat-four-side pin-less packaging part production method the most according to claim 1, it is characterised in that grinding thichness 0.03mm～0.035mm at the bare copper frame back side in described step 8.
Tape welding spherical array flat-four-side pin-less packaging part production method the most according to claim 1, it is characterised in that the first metal layer in described step 12 is copper metal layer.
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| CN116967602A (en) * | 2022-04-29 | 2023-10-31 | 派克泰克封装技术有限公司 | Method and apparatus for soldering electronic components to circuit boards |
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| US6975035B2 (en) * | 2002-03-04 | 2005-12-13 | Micron Technology, Inc. | Method and apparatus for dielectric filling of flip chip on interposer assembly |
| US7652374B2 (en) * | 2006-07-31 | 2010-01-26 | Chi Wah Kok | Substrate and process for semiconductor flip chip package |
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