CN103579423B - The manufacture method of chip size stage wafer light-emitting diode - Google Patents

Abstract

A method for manufacturing a chip-scale wafer light-emitting diode, comprising: drilling two through holes on the surface of a substrate; vapor-depositing a silicon dioxide protective film on both sides of the substrate; placing the substrate in concentrated sulfuric acid and Erosion and cleaning in concentrated phosphoric acid mixed solution; remove the silicon dioxide film protective film on the substrate surface; grow N-type doped layer, multi-quantum well light-emitting layer, P-type doped layer and ITO layer sequentially on one side of the substrate; The upper side of the ITO layer is etched downward to form a mesa, and there is a through hole in the center of the mesa; an N-type electrode is made on the through hole of the mesa; a P-type electrode is made on the through hole on the ITO layer on the other side of the mesa Electrode; Insulation layer is made on the inner wall of the through hole on the ITO layer on the other side of the table; Chromium gold guide layer is evaporated on the back of the substrate and in the two through holes; Photoresist is spin-coated and patterned on the back of the substrate , Corrosion chromium gold guide layer. The invention can reduce the package cost of the light-emitting diode, and is especially suitable for the package application of the large-scale power light-emitting diode.

Description

Chip-scale wafer light-emitting diode manufacturing method

technical field

The invention belongs to the technical field of semiconductors, in particular to a method for manufacturing a chip-scale wafer light-emitting diode.

Background technique

LED lighting is a new generation of solid cold light source, which has the characteristics of low energy consumption, long life, easy control, safety and environmental protection, etc. It is an ideal energy-saving and environmental protection product, suitable for various lighting places. The LED packaging process refers to pasting the LED chip on the substrate, shell or bracket in a certain way, and then connecting the electrodes on the chip to the substrate, shell or bracket through the gold wire ball bonding process to realize electric drive, and finally Seal or cover with transparent encapsulation material. Due to more packaging steps, more materials are consumed, and the production efficiency is low due to the individual packaging of a single chip, so LED packaging is developing towards integration and miniaturization. Chip-scale packaging, especially wafer-level chip-scale packaging, which is currently emerging, is attracting widespread attention because it can package multiple chips in batches at one time. However, these packages are realized by placing LED epitaxial chips on substrates made of other materials. The substrate needs to be transferred during the packaging process, and its packaging cost and process cost are still high.

Contents of the invention

The main purpose of the present invention is to provide a method for manufacturing chip-scale wafer light-emitting diodes, which is to use laser processing through holes on the substrate of gallium nitride-based light-emitting diodes in the process of making light-emitting diode chips, so that the P of the light-emitting diodes can be The electrode and N electrode are made on the back of the substrate, which can greatly reduce the chip package size, save space for the chip and external connection, save package volume and package materials, thereby reducing the package cost of the light-emitting diode, especially suitable for large-scale power light-emitting diodes packaging applications.

In order to achieve the above object, the present invention provides a method for manufacturing a chip-size wafer light-emitting diode, which includes the following steps:

Step 1: Drill two through holes with a laser on the surface of the substrate;

Step 2: Evaporate a silicon dioxide film protective film on the front and back sides of the substrate with through holes;

Step 3: put the substrate of the vapor-deposited silicon dioxide film protective film into the mixture of concentrated sulfuric acid and concentrated phosphoric acid to etch, and clean and corrode the residue after laser ablation on the side wall of the through hole;

Step 4: cleaning, removing the silicon dioxide film protective film on the surface of the substrate;

Step 5: growing an N-type doped layer, a multi-quantum well light-emitting layer, a P-type doped layer and an ITO layer sequentially on one side of the substrate;

Step 6: Etching downward on the upper side of the ITO layer, the etching depth reaches the N-type doped layer, forming a mesa, and a through hole is located in the center of the mesa;

Step 7: making an N-type electrode on the through hole of the table, and the N-type electrode covers the through hole; making a P-type electrode on the through hole on the ITO layer on the other side of the table, and the P-type electrode covers the through hole;

Step 8: Make an insulating layer on the inner wall of the through hole on the ITO layer on the other side of the table;

Step 9: Evaporating a chrome-gold guide layer on the back of the substrate and in the two through holes, the chrome-gold guide layer is in contact with the N-type electrode and the P-type electrode;

Step 10: Spin-coat photoresist on the back of the substrate and make a pattern, etch the chrome-gold guide layer, isolate the P-type electrode and the N-type electrode, and complete the preparation.

Description of drawings

In order to further illustrate the specific technical content of the present invention, below in conjunction with embodiment and accompanying drawing detailed description as follows, wherein:

Fig. 1 is the production flowchart of the present invention;

Fig. 2 is a structural sectional view of the present invention.

detailed description

Please refer to FIG. 1 and FIG. 2, the present invention provides a method for manufacturing a chip-scale wafer light-emitting diode, including the following steps:

Step 1: using a laser to drill two through holes 211 on the surface of the substrate 21; wherein the material of the substrate 21 is sapphire, Si, SiC, GaAs or glass. There are also wet etching, dry etching or mechanical drilling methods for making through holes. Wherein the diameter of the through hole 211 on the substrate 21 is 20-200 μm.

Step 2: Evaporate a silicon dioxide protective film or a silicon nitride or polyimide protective film on the front and back sides of the substrate 21 with the through hole 211 punched.

Step 3: put the substrate 21 on which the silicon dioxide film protective film is evaporated into the mixed solution of concentrated sulfuric acid and concentrated phosphoric acid to etch, and clean and corrode the residue after laser ablation on the side wall of the through hole 211; or use aqua regia, hydrogen Fluoric acid, sodium hydroxide solution to clean the residue on the side wall. Wherein the mixture of concentrated sulfuric acid and concentrated phosphoric acid is concentrated sulfuric acid:concentrated phosphoric acid=3:1, the temperature is 200-330°C, and the corrosion time is 2-10 hours.

Step 4: cleaning, removing the silicon dioxide protective film on the surface of the substrate 21;

Step 5: growing an N-type doped layer 22, a multi-quantum well light-emitting layer 23, a P-type doped layer 24, and an ITO layer 25 sequentially on one side of the substrate 21; wherein the material of the N-type doped layer 22 is N-GaN, The thickness is 1-5 μm. The material of the multiple quantum well light-emitting layer 23 is InGaN, and the thickness is 50-500nm. The material of the P-type doped layer 24 is P-GaN, and the thickness is 200-500 nm.

Step 6: Etching one side of the ITO layer 25 downward, the etching depth reaches the N-type doped layer 22, forming a mesa 210, and a through hole 211 is located in the center of the mesa 210;

Step 7: Make an N-type electrode 28 on the through hole 211 of the mesa 210, and the N-type electrode 28 covers the through hole 211; make a P-type electrode 27 on the through hole 211 on the ITO layer 25 on the other side of the mesa 210, The P-type electrode 27 covers the through hole 211; the material of the ITO layer 25 is 95% InO ₂ , 5% SnO ₂ , and the thickness is 10-1000 nm.

Step 8: Form an insulating layer 30 on the inner wall of the through hole 211 on the ITO layer 25 on the other side of the mesa 210; the insulating layer can be silicon dioxide film, silicon nitride, or polyimide.

Step 9: Evaporate a chrome-gold guide layer 31 on the back of the substrate 21 and in the two through holes 211, the chrome-gold guide layer 31 is in contact with the N-type electrode 28 and the P-type electrode 27;

Step 10: Spin-coat photoresist on the back of the substrate 21 and make a pattern, etch the chrome-gold guide layer 31 to isolate the P-type electrode 27 and the N-type electrode 28, and complete the preparation.

Although the invention has been described in conjunction with specific examples, it is evident that many alternatives, modifications and changes may be made by those skilled in the art in light of the above description. Accordingly, the present invention is intended to embrace all other such alternatives, modifications and variations that fall within the spirit and scope of the appended claims.

Claims (7)

1. A method for manufacturing a chip-size wafer light-emitting diode, comprising the following steps: Step 1: Drill two through holes with a laser on the surface of the substrate; Step 2: Evaporate a silicon dioxide film protective film on the front and back sides of the substrate with through holes; Step 3: put the substrate of the vapor-deposited silicon dioxide film protective film into the mixture of concentrated sulfuric acid and concentrated phosphoric acid to etch, and clean and corrode the residue after laser ablation on the side wall of the through hole; Step 4: cleaning, removing the silicon dioxide film protective film on the surface of the substrate; Step 5: growing an N-type doped layer, a multi-quantum well light-emitting layer, a P-type doped layer and an ITO layer sequentially on one side of the substrate; Step 6: Etching downward on the upper side of the ITO layer, the etching depth reaches the N-type doped layer, forming a mesa, and a through hole is located in the center of the mesa; Step 7: making an N-type electrode on the through hole of the table, and the N-type electrode covers the through hole; making a P-type electrode on the through hole on the ITO layer on the other side of the table, and the P-type electrode covers the through hole; Step 8: Make an insulating layer on the inner wall of the through hole on the ITO layer on the other side of the table; Step 9: Evaporating a chrome-gold guide layer on the back of the substrate and in the two through holes, the chrome-gold guide layer is in contact with the N-type electrode and the P-type electrode; Step 10: Spin-coat photoresist on the back of the substrate and make a pattern, etch the chrome-gold guide layer, isolate the P-type electrode and the N-type electrode, and complete the preparation. 2. The method for manufacturing a chip-scale wafer light-emitting diode according to claim 1, wherein the material of the substrate is sapphire, Si, SiC, GaAs or glass. 3. The method for manufacturing chip-scale wafer light-emitting diodes according to claim 1, wherein the material of the N-type doped layer is N-GaN, and the thickness is 1-5 μm. 4. The method for manufacturing chip-scale wafer light-emitting diodes according to claim 1, wherein the material of the multi-quantum well light-emitting layer is InGaN, and the thickness is 50-500nm. 5. The method for manufacturing chip-scale wafer light-emitting diodes according to claim 1, wherein the material of the P-type doped layer is P-GaN, and the thickness is 200-500 nm. 6. The method for manufacturing chip-scale wafer light-emitting diodes according to claim 1, wherein the insulating layer is made of silicon dioxide. 7. The method for manufacturing a chip-scale wafer light-emitting diode according to claim 1, wherein the diameter of the through hole on the substrate is 20-200 μm.