CN103632942B - The method of integrated SONOS device and LDMOS device in CMOS technology - Google Patents

Abstract

The invention discloses a kind of method of integrated SONOS device and LDMOS device in CMOS technology, comprise step: step one, form fleet plough groove isolation structure on a silicon substrate; Form well region; Carry out threshold voltage adjustment to inject.Step 2, formation the first pre-oxygen layer.Step 3, first of SONOS nmosfet formation region the pre-oxygen layer to be removed.Step 4, deposit ONO layer.Step 5, ONO layer to be etched, form the gate dielectric layer of SONOS device and LDMOS device simultaneously.The gate oxide of step 6, formation CMOS logical device.Step 7, carry out polysilicon deposition, polysilicon is etched to the grid polycrystalline silicon simultaneously forming SONOS device, LDMOS device and CMOS logical device.Step 8, carry out the injection of light dope source and drain; Form side wall; Carry out source and drain injection.The present invention can reduce the number of plies of reticle, reduces the manufacturing cost of chip.

Description

Method for integrating SONOS device and LDMOS device in CMOS process

technical field

The invention relates to a semiconductor integrated circuit manufacturing process method, in particular to a method for integrating SONOS devices and LDMOS devices in a CMOS process.

Background technique

Non-volatile memory (NVM) technology has been developed so far, mainly including floating gate technology, split gate technology and SONOS (Silicon-Oxide-Nitride-Oxide-Silicon, silicon oxide oxynitride silicon) technology. SONOS technology is widely used and has the advantages of low operating voltage, high speed and large capacity. With the rapid development of mobile Internet technology, especially the rapid rise of the semiconductor market with mobile terminals as the main market application, the emerging semiconductors represented by touch screen control integrate microprocessors, CODE storage devices, high-voltage devices such as LDMOS devices Wait. This requires high-voltage devices and embedded memory devices to be integrated on the same platform. Embedding memory and high-voltage devices into a standard CMOS logic process requires adding more than 10 layers of photolithography, and the design and manufacturing costs are very high.

As shown in Figure 1, the structure schematic diagram of existing N-type SONOS device; Existing N-type SONOS device: comprise P-type well region 101, on described P-type well region 101, be successively formed with first silicon oxide layer 103, the second Silicon nitride layer 104 and the third silicon oxide 105, the ONO layer is composed of the first silicon oxide layer 103, the second silicon nitride layer 104 and the third silicon oxide 105, and the first silicon oxide layer 103 is a device tunnel oxide layer, the second silicon nitride layer 104 is a data storage medium layer, and the third silicon oxide layer 105 is a control oxide layer. A gate polysilicon 106 is formed over the ONO layer. A sidewall 107 is formed on the side of the gate polysilicon 106 , and the ONO layer also extends below the sidewall 107 . The P-type well region 101 covered by the gate polysilicon 106 is a channel region, and a threshold voltage adjustment injection region 102 is formed in the channel region, and the threshold voltage adjustment injection region 102 is an N-region, Used to adjust the threshold voltage of the device. The P-type well region 101 on both sides of the gate polysilicon 106 is formed with symmetrically arranged lightly doped source and drain (LDD) regions 108 and source and drain regions 109, and the lightly doped source and drain regions 108 and the Edges of the gate polysilicon 106 are self-aligned, and edges of the source-drain region 109 and the spacer 107 are self-aligned. When the device performs a writing operation, a positive voltage VPOS is biased on the gate polysilicon 106, a negative voltage VNEG is biased on the source and drain regions 109, and a negative voltage is also biased on the P-type well region 101. VNEG, thus forming the tunneling voltage difference (VPOS-VNEG) from the gate polysilicon 106 to the channel region, so that the F-N tunneling of electrons occurs, that is, the electrons in the channel region pass through the F-N Tunneling through the first silicon oxide layer 103 into the second silicon nitride layer 104 and being trapped by the traps of the second silicon nitride layer 104 . For the existing P-type SONOS device, the doping of each region is opposite to that of the existing N-type SONOS device, for example, the channel region is N-type, and the source and drain regions are P-type.

Embedding the existing SONOS device into the standard CMOS process requires an additional 3 to 4 photoresist layers, such as including: tunnel oxide layer definition photoresist layer, storage tube channel adjustment injection photoresist layer, storage tube ONO dielectric film definition The photoresist layer, the storage tube LDD is injected into the photoresist layer, etc.

As shown in FIG. 2A, it is a schematic structural diagram of an existing asymmetric N-type LDMOS device; the existing N-type LDMOS device includes: a silicon substrate 201, in which a shallow trench isolation structure is formed, filled with The shallow trench field oxygen 203 in the shallow trench isolates the active region. An N-type well region (NWELL) 202 is formed in the silicon substrate 201; a P-type well region (PWELL) 204 is formed in the N-type well region 202, and sequentially formed on the surface of the silicon substrate 201 are The gate dielectric layer 205 is such as a gate oxide layer and gate polysilicon 206 , and the P-type well region 204 covered by the gate polysilicon 206 forms a channel region. The source region 207 is an N+ region formed in the P-type well region 204; the drain region 208 is an N+ region formed in the N-type well region 202, between the drain region 208 and the channel region A shallow trench field oxygen 203 is isolated, and the shallow trench field oxygen 203 is also separated from the channel region by a certain distance, and the gate polysilicon 206 extends to the top of the shallow trench field oxygen 203; The N-type well region 202 between the channel region and the drain region 208 constitutes a drift region (N-Drift) of the device. A back gate electrode lead-out region 209 is formed in the P-type well region 204 , and the back gate electrode lead-out region 209 is an N+ region. Metal contacts 210 are respectively formed above the source region 207, the drain region 208, the gate polysilicon 206 and the back gate electrode lead-out region 209, and lead out the source, drain, gate and back gate respectively. electrode.

As shown in Figure 2B, it is a schematic structural diagram of an existing asymmetric P-type LDMOS device; the existing P-type LDMOS device is formed in a deep N-type well region (DNWELL) 301 on a silicon substrate, in the silicon substrate A shallow trench isolation structure is formed, and the active region is isolated by the shallow trench field oxygen 303 filled in the shallow trench. A P-type well region 302 is formed in the deep N-type well region 301; an N-type well region 304 is formed in the P-type well region 302, and a gate dielectric layer 305 is sequentially formed on the surface of the silicon substrate such as Gate oxide layer and gate polysilicon 306 , the N-type well region 304 covered by the gate polysilicon 306 forms a channel region. The source region 307 is a P+ region formed in the N-type well region 304; the drain region 308 is a P+ region formed in the P-type well region 302, between the drain region 308 and the channel region A shallow trench field oxygen 303 is isolated, and the shallow trench field oxygen 303 is also separated from the channel region by a certain distance, and the gate polysilicon 306 extends to the top of the shallow trench field oxygen 303; The P-type well region 302 between the channel region and the drain region 308 constitutes a drift region (P-Drift) of the device. A back-gate electrode lead-out region 309 is formed in the NP-type well region 304, and the back-gate electrode lead-out region 309 is an N+ region. Metal contacts 310 are respectively formed above the source region 307, the drain region 308, the gate polysilicon 306 and the back gate electrode lead-out region 309, and lead out the source, drain, gate and back gate respectively. electrode.

The characteristic of LDMOS devices is that a thicker gate dielectric layer is formed under the gate polysilicon to withstand high voltage such as the high voltage applied to the gate. The gate dielectric layer needs to be defined and etched by photolithography to form. In addition, LDMOS devices also need to form a drift region to withstand the high voltage between the source and drain of the device. The drift region includes two types of P-type drift region (P-Drift) and N-type drift region (N-Drift). Two layers are photolithographically formed. In addition, LDMOS devices also require two to three layers of photolithography to form a high-voltage well region (HVWELL) to achieve high-voltage withstand voltage of the device, such as high-voltage N-type well region (NWELL), P-type well region (PWELL) and deep N-type Well area (DNWELL). In this way, in the prior art, it is necessary to add 6-7 layers of photolithography process to realize embedding the LDMOS device into the standard CMOS process.

Therefore, in the prior art, if the SONOS device and the high-voltage LDMOS device are embedded in the standard CMOS process, compared with the standard CMOS process, an additional 9-11 photolithography layers need to be added, which makes the process and manufacturing costs relatively high.

Contents of the invention

The technical problem to be solved by the present invention is to provide a method for integrating SONOS devices and LDMOS devices in a CMOS process, which can greatly reduce the number of layers of photolithographic plates and greatly reduce the manufacturing cost of chips.

In order to solve the above-mentioned technical problems, the method for integrating SONOS devices and LDMOS devices in the CMOS process provided by the present invention is used to integrate SONOS devices, LDMOS devices and CMOS logic devices on the same silicon substrate, comprising the following steps:

Step 1: forming a shallow trench isolation structure on the silicon substrate, and isolating an active region by the shallow trench isolation structure; forming a well region; performing threshold voltage adjustment implantation.

Step 2, forming a first pre-oxidation layer on the surface of the silicon substrate after step 1.

Step 3: Etching the first pre-oxidation layer using a photolithography process, removing the first pre-oxidation layer in the SONOS device formation region and exposing the surface of the silicon substrate, and placing the SONOS The first pre-oxidation layer outside the device formation area remains.

Step 4, depositing a first silicon oxide layer, a second silicon nitride layer and a third silicon oxide layer in sequence on the front side of the silicon substrate, the first silicon oxide layer, the second silicon nitride layer and the The third silicon oxide layer constitutes an ONO layer, and the ONO layer covers the surface of the silicon substrate in the formation area of the SONOS device and the surface of the first pre-oxidation layer outside the formation area of the SONOS device.

Step 5. Etching the ONO layer by using a photolithographic etching process, and simultaneously forming the gate dielectric layer of the SONOS device and the LDMOS device, the gate dielectric layer of the SONOS device is located on the SONOS after etching The ONO layer in the device formation area, the gate dielectric layer of the LDMOS device is composed of the first pre-oxidation layer and the ONO layer in the LDMOS device formation area after etching.

Step 6, forming a gate oxide layer of the CMOS logic device.

Step 7: Depositing polysilicon, and etching the polysilicon by using a photolithography process to simultaneously form the gate polysilicon of the SONOS device, the LDMOS device and the CMOS logic device.

Step 8: Perform lightly doped source and drain implantation to form lightly doped source and drain implantation regions in the silicon substrate on both sides of each gate polysilicon; form sidewalls on each side of the gate polysilicon; Drain implants form source and drain regions of the SONOS device, the LDMOS device and the CMOS logic device.

A further improvement is that the thickness of the first pre-oxidation layer is 100 angstroms to 150 angstroms; the thickness of the first silicon oxide layer is 18 angstroms to 24 angstroms; the thickness of the second silicon nitride layer is 80 angstroms ˜120 angstroms; the thickness of the third silicon oxide layer is 40 angstroms˜80 angstroms.

A further improvement is that the thickness of the gate dielectric layer of the LDMOS device is 200-300 angstroms.

A further improvement is that the LDMOS device includes a channel region and a drift region; the channel region and the drift region are adjacent, and the gate polysilicon of the LDMOS device is covered above the channel region for controlling Channel formation; for N-type LDMOS devices, the channel region is composed of P-type well regions, and the drift region is composed of N-type well regions; for P-type LDMOS devices, the channel region is composed of N-type well regions, and the drift region is composed of P-type well regions. The P-type well region and the N-type well region are formed in step one.

A further improvement is that, for a symmetric LDMOS device, the drift region includes two, and the two drift regions are arranged symmetrically on both sides of the channel region, and a source-drain implant is formed in each drift region region, and the two source and drain injection regions are symmetrical structures and serve as the source region or the drain region of the symmetrical LDMOS device respectively. For an asymmetric LDMOS device, the drift region includes one, the drift region is set on the side of the channel region close to the drain end, the drain region is formed in the drift region, and the source region is formed in the In the channel region, and the source region is self-aligned with the gate polysilicon edge above the channel region.

A further improvement is that the gate polysilicon withstand voltage of the LDMOS device is 12V-16V.

A further improvement is that the source-drain breakthrough voltage of the LDMOS device is 12V-16V.

A further improvement is that the SONOS device includes a channel region; for an N-type SONOS device, the channel region is composed of a P-type well region; for a P-type SONOS device, the channel region is composed of an N-type well region ; The P-type well region and the N-type well region are formed in step one.

A further improvement is that the CMOS logic device includes a PMOS logic device and an NMOS logic device, and both the PMOS logic device and the NMOS logic device include a channel region; for the NMOS logic device, the channel region consists of a P-type well region; for PMOS logic devices, the channel region is composed of an N-type well region; the P-type well region and the N-type well region are formed in step one.

In the present invention, by setting the gate dielectric layer of the LDMOS device as a structure in which the first pre-oxidation layer and the ONO layer are stacked, the same photolithography plate can be used to simultaneously photoetch and etch to form the gate dielectric layer of the SONOS device and the LDMOS device. In addition, a photolithography plate is required to define the position of the SONOS device when the ONO layer is formed, and a total of 2 photolithography plates are required to prepare the gate dielectric layer of the SONOS device and the LDMOS device; and the well region required by the LDMOS device and the SONOS device The formation of the threshold voltage adjustment injection region can be carried out together with the well region and the threshold voltage adjustment injection region of the CMOS logic device, and the formation of the gate polysilicon and source and drain regions of the LDMOS device and SONOS device can also be carried out together with the gate polysilicon of the CMOS logic device. It is carried out together with the source and drain regions, so it can greatly reduce the number of photolithographic layers required to form well regions, threshold voltage adjustment implant regions, gate polysilicon and source and drain regions required to form LDMOS devices and SONOS devices alone; the above advantages The present invention only needs to add 3 to 4 layers of photolithographic plates on the basis of the standard CMOS process to realize the embedding of SONOS devices and LDMOS devices into the CMOS process, which can greatly reduce the number of layers of photolithographic plates, thereby greatly reducing Chip manufacturing costs.

Description of drawings

Below in conjunction with accompanying drawing and specific embodiment, the present invention will be described in further detail:

Fig. 1 is the structural representation of existing N-type SONOS device;

FIG. 2A is a schematic structural diagram of an existing asymmetric N-type LDMOS device;

FIG. 2B is a schematic structural diagram of an existing asymmetric P-type LDMOS device;

Fig. 3 is the flowchart of the embodiment method of the present invention;

4A-4I are schematic diagrams of device structures in each step of the method of the embodiment of the present invention.

detailed description

FIG. 3 is a flowchart of the method of the embodiment of the present invention; FIG. 4A to FIG. 4I are schematic diagrams of device structures in each step of the method of the embodiment of the present invention. The method for integrating SONOS devices and LDMOS devices in the CMOS process of the embodiment of the present invention is used to integrate SONOS devices, LDMOS devices and CMOS logic devices on the same silicon substrate, including the following steps:

Step 1. As shown in FIG. 4A , a shallow trench isolation structure 3 is formed on the silicon substrate, and the shallow trench isolation structure 3 , that is, the shallow trench field oxygen filled in the shallow trench, isolates active region; forming a well region; performing threshold voltage adjustment implantation. The well region includes a deep N-type well 1 , a P-type well region 2 and an N-type well region 4 .

The LDMOS device includes a channel region and a drift region; the channel region is adjacent to the drift region, and a threshold voltage adjustment injection region is formed in the channel region through the threshold voltage adjustment implantation. For an N-type LDMOS device, the channel region is composed of a P-type well region 2, and the drift region is composed of an N-type well region 4; for a P-type LDMOS device, the channel region is composed of an N-type well region 4, and the drift region is composed of a P-type well region Zone 2 is composed. For a symmetric LDMOS device, the drift region includes two, and the two drift regions are symmetrically arranged on both sides of the channel region; for an asymmetric LDMOS device, the drift region includes one, and the drift region is set On the side of the channel region close to the drain terminal. 4A to 4I illustrate a cross-sectional structure of a formation region of an asymmetric P-type LDMOS device. The cross-sectional structure of the asymmetric N-type LDMOS device and the symmetrical P-type and N-type LDMOS devices can also be referred to the cross-sectional structure of the formation region of the asymmetric P-type LDMOS device, and the asymmetric N-type LDMOS The channel region and drift region of the device and the doping type of the subsequent source and drain doped regions can be reversed; the cross-sectional structure of the symmetrical LDMOS device only needs to be on the source region side on the basis of the symmetrical LDMOS device. Add a symmetrical drift zone.

The SONOS device includes a channel region, and a threshold voltage adjusting injection region is formed in the channel region through the threshold voltage adjusting implantation. For an N-type SONOS device, the channel region is composed of a P-type well region 2 ; for a P-type SONOS device, the channel region is composed of an N-type well region 4 . Figure 4A to Figure 4I have schematically shown the sectional structure of the formation region of a P-type SONOS device; The doping type of the channel region of the SONOS device and the subsequent source and drain doping regions can be reversely transformed.

The CMOS logic device includes a PMOS logic device and an NMOS logic device. Both the PMOS logic device and the NMOS logic device include a channel region, and a threshold voltage adjustment is formed in the channel region through the threshold voltage adjustment injection. injection area. For an NMOS logic device, the channel region is composed of a P-type well region 2 ; for a PMOS logic device, the channel region is composed of an N-type well region 4 . Fig. 4A to Fig. 4I have shown the sectional structure of the formation region of an NMOS logic device; The doping types of the channel region and the subsequent source and drain doped regions can be reversely transformed.

It can be seen that in step 1, the deep N-type well 1, P-type well region 2, and N-type well region 4 required in the LDMOS device, the SONOS device, and the CMOS logic device can be separately used together with a photolithography plate. It can be formed. It is not necessary to add a plurality of optical blocks to form the deep N-type well 1, P-type well region 2, and N-type well region 4 of the LDMOS device, and the P-type well region 2 and N-type well region 4 of the SONOS device. Engraving.

When forming the well region and performing threshold voltage adjustment implantation, it is necessary to first form a shielding oxide layer 5 on the surface of the silicon substrate to protect the surface of the silicon substrate. Afterwards, the photoresist 6 is used to define the region to be implanted with ions.

After the well region implantation and threshold voltage adjustment implantation, as shown in FIG. 4B , the photoresist 6 and the shielding oxide layer 5 are removed.

Step 2, as shown in FIG. 4C , a first pre-oxidation layer 7 is formed on the surface of the silicon substrate after step 1. The thickness of the first pre-oxidation layer 7 is 100 angstroms to 150 angstroms.

Step 3, as shown in FIG. 4D, the first pre-oxidation layer 7 is etched using a photolithography process, and the first pre-oxidation layer 7 in the SONOS device formation region is removed to expose the silicon On the surface of the substrate, the first pre-oxidation layer 7 outside the region where the SONOS device is formed is reserved.

Step 4, as shown in FIG. 4E , deposit a first silicon oxide layer 8 , a second silicon nitride layer 9 and a third silicon oxide layer 10 sequentially on the front side of the silicon substrate, and the first silicon oxide layer 8 The thickness is 18 angstroms to 24 angstroms; the thickness of the second silicon nitride layer 9 is 80 angstroms to 120 angstroms; the thickness of the third silicon oxide layer 10 is 40 angstroms to 80 angstroms. An ONO layer is composed of the first silicon oxide layer 8 , the second silicon nitride layer 9 and the third silicon oxide layer 10 . The ONO layer covers the surface of the silicon substrate in the SONOS device formation area and the surface of the first pre-oxidation layer 7 outside the SONOS device formation area.

Step 5, as shown in FIG. 4F , the ONO layer is etched by a photolithography process, and the gate dielectric layers of the SONOS device and the LDMOS device are formed at the same time. The gate dielectric layer of the SONOS device is composed of the ONO layer located in the formation area of the SONOS device after etching, wherein the first silicon oxide layer 8 is the tunnel oxide layer of the device, and the second nitride The silicon layer 9 is a data storage medium layer, and the third silicon oxide 10 is a control oxide layer. The gate dielectric layer of the LDMOS device is composed of the first pre-oxidation layer 7 and the ONO layer superimposed on the formation area of the LDMOS device after etching, and the thickness of the gate dielectric layer of the LDMOS device is 200 angstroms to 300 Angstroms. After the gate dielectric layer of the SONOS device and the LDMOS device is formed, the same photoresist pattern is used when etching the ONO layer, and the gate dielectric layer of the SONOS device and the LDMOS device is etched using an etching process. The outer first pre-oxidation layer is completely removed, and the etching process can be wet etching; after that, the photoresist is removed.

Step 6, as shown in FIG. 4G , forming a gate oxide layer of the CMOS logic device.

Step 7, as shown in FIG. 4G, polysilicon deposition is performed, and the polysilicon is etched by photolithography and etching process, and simultaneously the gate polysilicon 11c of the SONOS device, the gate polysilicon 11a of the LDMOS device, and the polysilicon are formed. The gate polysilicon 11b of the CMOS logic device.

Step 8, as shown in FIG. 4G , perform lightly doped source and drain implantation to form lightly doped source and drain implantation regions in the silicon substrate on both sides of each of the gate polysilicon 11 a , 11 b and 11 c . Edges of the lightly doped source and drain implant regions are self-aligned with the corresponding gate polysilicon.

Side walls are formed on the side surfaces of each of the gate polysilicon 11a, 11b, and 11c.

Source-drain implantation is performed to form the source and drain regions of the SONOS device, the LDMOS device and the CMOS logic device, and simultaneously form the back gate lead-out region (Bulk) of the LDMOS device.

The source region and the drain region of the SONOS device are arranged symmetrically, and both are self-aligned with the sidewall edges of the corresponding gate polysilicon. The source region and the drain region 12c of the P-type SONOS device are composed of a P+ region; the source region and the drain region of the N-type SONOS device are composed of an N+ region.

The source region and the drain region of the CMOS logic device are arranged symmetrically, and both are self-aligned with the sidewall edges of the corresponding gate polysilicon. The source region and the drain region 12b of the NMOS logic device are composed of an N+ region; the source region and the drain region of the PMOS logic device are composed of a P+ region.

The source region 12a of the asymmetric P-type LDMOS device is formed in the channel region, and the source region 12a is self-aligned with the sidewall edge of the corresponding gate polysilicon; the asymmetric P-type LDMOS The drain region of the device is formed in a corresponding drift region (not shown); the source region 12a and the drain region of the asymmetric P-type LDMOS device are both composed of P+ regions.

Both the source region and the drain region of the asymmetric N-type LDMOS device are composed of N+ regions.

Both the source region and the drain region of the symmetrical P-type LDMOS device are formed in the corresponding drift region, are arranged symmetrically and are composed of a P+ region.

Both the source region and the drain region of the symmetrical N-type LDMOS device are formed in the corresponding drift regions, are arranged symmetrically and are composed of N+ regions.

The lead-out region of the back gate electrode of the LDMOS device also includes two types of P+ region and N+ region, and the doping type of the lead-out region of the back gate electrode is the same as that of the channel region to be led out.

The above SONOS device, the LDMOS device and the CMOS logic device have the same lightly doped source and drain implantation region, that is, the N-type or P-type lightly doped source and drain implantation region can use a photolithography plate respectively Do the injection. The source region and the drain region of the SONOS device, the LDMOS device and the CMOS logic device, and the back gate electrode lead-out region of the LDMOS device include two types, a P+ region and an N+ region, and a photolithographic plate can be used respectively Implantation is performed to form a P+ region or an N+ region, thereby forming the source and drain regions of each of the SONOS devices, the LDMOS devices, and the CMOS logic devices, and the back gate electrode lead-out regions of each of the LDMOS devices. Therefore, the method of the present invention does not need to add a plurality of additional photolithography plates for forming the lightly doped source-drain implant region and the source-drain region of the SONOS device.

The thickness of the gate dielectric layer of the LDMOS device is set so that the gate polysilicon withstand voltage of the LDMOS device is 12V-16V. The arrangement of the channel region and the well region corresponding to the drift region of each of the LDMOS devices makes the source-drain breakthrough voltage of each of the LDMOS devices 12V˜16V. The LDMOS device formed by the present invention satisfies the high withstand voltage characteristic of 12V-16V.

As shown in FIG. 4H , form a metal contact 13 that is in contact with the source and drain regions of each of the SONOS devices, the LDMOS devices, and the CMOS logic devices, and the back gate electrode lead-out region of each of the LDMOS devices. .

As shown in Figure 4I, a metal layer 14 is formed, and the source and drain electrodes of each of the SONOS devices, the LDMOS devices and the CMOS logic devices, and the back gate electrodes of each of the LDMOS devices are formed by photolithography .

The present invention has been described in detail through specific examples above, but these do not constitute a limitation to the present invention. Without departing from the principle of the present invention, those skilled in the art can also make many modifications and improvements, which should also be regarded as the protection scope of the present invention.

Claims (9)

1. a method for integrating SONOS devices and LDMOS devices in a CMOS process, for integrating SONOS devices, LDMOS devices and CMOS logic devices on the same silicon substrate, it is characterized in that, comprising the steps: Step 1, forming a shallow trench isolation structure on the silicon substrate, and isolating an active region by the shallow trench isolation structure; forming a well region; performing threshold voltage adjustment implantation; Step 2, forming a first pre-oxidation layer on the surface of the silicon substrate after step 1; Step 3: Etching the first pre-oxidation layer using a photolithography process, removing the first pre-oxidation layer in the SONOS device formation region and exposing the surface of the silicon substrate, and placing the SONOS The first pre-oxidation layer remains outside the device formation region; Step 4, depositing a first silicon oxide layer, a second silicon nitride layer and a third silicon oxide layer in sequence on the front side of the silicon substrate, the first silicon oxide layer, the second silicon nitride layer and the The third silicon oxide layer forms an ONO layer, and the ONO layer covers the surface of the silicon substrate in the SONOS device formation area and the surface of the first pre-oxidation layer outside the SONOS device formation area; Step 5. Etching the ONO layer by using a photolithographic etching process, and simultaneously forming the gate dielectric layer of the SONOS device and the LDMOS device, the gate dielectric layer of the SONOS device is located on the SONOS after etching The ONO layer in the device formation area, the gate dielectric layer of the LDMOS device is composed of the first pre-oxidation layer and the ONO layer located in the LDMOS device formation area after etching; using an etching process to The first pre-oxidation layer other than the gate dielectric layer of the SONOS device and the LDMOS device is completely removed; Step 6, forming a gate oxide layer of the CMOS logic device; Step 7, performing polysilicon deposition, using a photolithographic etching process to etch the polysilicon and simultaneously forming the gate polysilicon of the SONOS device, the LDMOS device and the CMOS logic device; Step 8: Perform lightly doped source and drain implantation to form lightly doped source and drain implantation regions in the silicon substrate on both sides of each gate polysilicon; form sidewalls on each side of the gate polysilicon; Drain implants form source and drain regions of the SONOS device, the LDMOS device and the CMOS logic device. 2. The method according to claim 1, characterized in that: the thickness of the first pre-oxidation layer is 100 angstroms to 150 angstroms; the thickness of the first silicon oxide layer is 18 angstroms to 24 angstroms; The thickness of the silicon nitride layer is 80-120 angstroms; the thickness of the third silicon oxide layer is 40-80 angstroms. 3. The method according to claim 1, wherein the gate dielectric layer of the LDMOS device has a thickness of 200 angstroms to 300 angstroms. 4. The method according to claim 1, wherein: the LDMOS device comprises a channel region and a drift region; the channel region and the drift region are adjacent, and the gate polysilicon of the LDMOS device covers Above the channel region is used to control the formation of the channel; for an N-type LDMOS device, the channel region is composed of a P-type well region, and the drift region is composed of an N-type well region; for a P-type LDMOS device, the channel region is composed of The drift region is composed of an N-type well region, and the drift region is composed of a P-type well region; the P-type well region and the N-type well region are formed in step one. 5. The method according to claim 4, characterized in that: for a symmetrical LDMOS device, the drift region comprises two, and the two drift regions are symmetrically arranged on both sides of the channel region, and each of the A source implantation region or a drain implantation region is respectively formed in the drift region, the source implantation region serves as the source region of the symmetric LDMOS device, and the drain implantation region serves as the drain region of the symmetric LDMOS device , the source region and the drain region are symmetrical structures; For an asymmetric LDMOS device, the drift region includes one, the drift region is set on the side of the channel region close to the drain end, the drain region is formed in the drift region, and the source region is formed in the In the channel region, and the source region is self-aligned with the gate polysilicon edge above the channel region. 6 . The method according to claim 3 , wherein the gate polysilicon withstand voltage of the LDMOS device is 12V˜16V. 7. The method according to claim 4 or 5, characterized in that: the source-drain breakthrough voltage of the LDMOS device is 12V-16V. 8. The method according to claim 1, wherein: the SONOS device includes a channel region; for the N-type SONOS device, the channel region is composed of a P-type well region; for the P-type SONOS device, the The channel region is composed of an N-type well region; the P-type well region and the N-type well region are formed in step one. 9. method as claimed in claim 1 is characterized in that: described CMOS logic device comprises PMOS logic device and NMOS logic device, and described PMOS logic device and described NMOS logic device all comprise channel region; For NMOS logic device, the channel region is composed of a P-type well region; for a PMOS logic device, the channel region is composed of an N-type well region; the P-type well region and the N-type well region are formed in step one.