CN103647708A - ATCA-based data message processing board - Google Patents
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- JEOQACOXAOEPLX-WCCKRBBISA-N (2s)-2-amino-5-(diaminomethylideneamino)pentanoic acid;1,3-thiazolidine-4-carboxylic acid Chemical compound OC(=O)C1CSCN1.OC(=O)[C@@H](N)CCCN=C(N)N JEOQACOXAOEPLX-WCCKRBBISA-N 0.000 title claims abstract description 23
- 238000012545 processing Methods 0.000 title claims abstract description 19
- 230000015654 memory Effects 0.000 claims description 16
- 238000012546 transfer Methods 0.000 claims description 15
- 238000000034 method Methods 0.000 description 5
- 230000005540 biological transmission Effects 0.000 description 4
- 238000004891 communication Methods 0.000 description 4
- 230000006870 function Effects 0.000 description 4
- NBGBEUITCPENLJ-UHFFFAOYSA-N Bunazosin hydrochloride Chemical compound Cl.C1CN(C(=O)CCC)CCCN1C1=NC(N)=C(C=C(OC)C(OC)=C2)C2=N1 NBGBEUITCPENLJ-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 238000005303 weighing Methods 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 230000009897 systematic effect Effects 0.000 description 1
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Abstract
The invention discloses an ATCA-based data message processing board. The data message processing board comprises an FPGA used for receiving a data message, analyzing the received data message, determining message header information corresponding to the data message and sending the message header information, and a co-processor used for receiving the message header information, determining message execution operation information matched with the message header information according to a pre-configured message header processing rule and sending the message execution operation information, wherein the message header processing rule is used for recording the corresponding relationship between the message header information and the message execution operation information matched with the message header information, and the FPGA is further used for receiving the message execution operation information and executing corresponding operation according to the message execution operation information.
Description
Technical field
The present invention relates to communication engineering field, specifically, relate to a kind of based on ATCA(Advanced Telecom Computing Architecture, communication system computer platform framework) data message disposable plates.
Background technology
At present, bag disposable plates based on ATCA can support that the main flow implementation of 40G flow is to take two NP(Network Processor that REDSYS is representative, network processing unit) scheme namely has two completely independently NP on a plate, and each NP is responsible for the flow of 20G.Although realize simply like this, when practical application, also there is many weak points, for example:
The sometimes flow of two 20G unbalanced meeting causes a NP load overweight, if carry out dynamic load migration, can produce extra expense again; In addition, because some algorithm of customer requirement is not suitable for realizing with NP, can seriously increase the pressure of NP access memory, cause the workload of software tuning to increase severely; In addition, two NP schemes are difficult to directly access the flow of 40G on plank, need an extra pre-processed board or interface board, have reduced like this bulk density of whole system in the situation that ATCA standard has been stipulated cabinet number of slots; In addition, two NP schemes generally can adopt an exchange chip to do exchange in plate, to make up the problem of NP network interface lazy weight and outer net expansion interface.But exchange chip cost very golf calorific value brings very large problem to system very greatly, and increase the transmission delay that has significantly increased system after one-level exchanges, be unfavorable for the performance of systematic function.
The mass flow discrepancy that can support the main flow implementation of 40G flow to exist for the bag disposable plates based on ATCA in existing correlation technique weighs, internal storage access pressure is excessive, need to configure extra pre-processed board or interface board and need to configure extra exchange chip does the problem exchanging in class, not yet proposes at present effective solution.
Summary of the invention
For the bag disposable plates based on ATCA in existing correlation technique, can support that the mass flow discrepancy of the main flow implementation existence of 40G flow weighs, internal storage access pressure is excessive, need to configure extra pre-processed board or interface board and need to configure extra exchange chip and do the problem exchanging in plate, the present invention proposes a kind of data message disposable plates based on ATCA.
Technical scheme of the present invention is achieved in that
According to an aspect of the present invention, provide a kind of data message disposable plates based on ATCA.
Should the data message disposable plates based on ATCA comprise:
FPGA, for receiving data packets, and analyzes the described data message receiving, and determines the header information that described data message is corresponding, and sends this header information;
Coprocessor, be used for receiving described header information, and according to pre-configured header processing rule, determine the message executable operations information suitable with described header information, and send this message executable operations information, wherein, described header processing rule for record header information and with the corresponding relation of the suitable message executable operations information of this header information;
Described FPGA is also for receiving described message executable operations information, and according to operation corresponding to this message executable operations information and executing.
Wherein, header information comprise following one of at least: the source port information of the source address information of data transfer layer protocol information, transfer of data, the destination address information of transfer of data, transfer of data, the destination interface information of transfer of data.
In addition, should the data message disposable plates based on ATCA also comprise: first memory, for determining after described header information at described FPGA, the data message that described FPGA is received carries out buffer memory.
In addition, described FPGA also, for according to the corresponding relation of pre-configured header information and coprocessor core information, determines the coprocessor core information that described header information is corresponding, and sends described coprocessor core information.
And, described coprocessor is also for receiving described coprocessor core information, and according to this coprocessor core information, described header information is dispensed to corresponding coprocessor core, impel described coprocessor core according to pre-configured header processing rule, determine the message executable operations information suitable with described header information.
In addition, should the data message disposable plates based on ATCA also comprise: second memory, for storing the corresponding relation of pre-configured header information and coprocessor core information.
The data traffic of the data message that wherein, described FPGA receives is 40G.
The present invention is by adopting the direct receiving data packets of FPGA, thereby avoided disposable plates when receiving data packets, to occur that the phenomenon of mass flow discrepancy weighing apparatus occurs, also avoided needing the trouble of additional configuration pre-processed board or interface board simultaneously, in addition, due to the processor that has adopted programmable FPGA as disposable plates, thereby make the algorithm that user requires that meets that data message disposable plates can adaptivity, avoid the excessive phenomenon of internal storage access pressure to occur, and because FPGA possesses data exchanging function in andante, from having avoided needing additional configuration exchange chip to do the trouble exchanging in plate, reduced the input cost of equipment, guaranteed the transmission rate of system, improved the performance performance of system.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, to the accompanying drawing of required use in embodiment be briefly described below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skills, do not paying under the prerequisite of creative work, can also obtain according to these accompanying drawings other accompanying drawing.
Fig. 1 is according to the structural representation of the data message disposable plates based on ATCA of the embodiment of the present invention;
Fig. 2 is according to the principle configuration diagram of the data message disposable plates based on ATCA of the embodiment of the present invention;
Fig. 3 is the principle schematic while processing according to the data flow of the data message disposable plates based on ATCA of the embodiment of the present invention.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is only the present invention's part embodiment, rather than whole embodiment.Embodiment based in the present invention, the every other embodiment that those of ordinary skills obtain, belongs to the scope of protection of the invention.
According to embodiments of the invention, provide a kind of data message disposable plates based on ATCA.
As shown in Figure 1, according to the data message disposable plates based on ATCA of the embodiment of the present invention, comprise:
FPGA11, for receiving data packets, and analyzes the described data message receiving, and determines the header information that described data message is corresponding, and sends this header information;
Described FPGA11 is also for receiving described message executable operations information, and according to operation corresponding to this message executable operations information and executing.
Wherein, header information comprise following one of at least: the source port information of the source address information of data transfer layer protocol information, transfer of data, the destination address information of transfer of data, transfer of data, the destination interface information of transfer of data.
In addition, should the data message disposable plates based on ATCA also comprise: first memory (not shown), for determining after described header information at described FPGA, the data message that described FPGA is received carries out buffer memory.
In addition, described FPGA11 also, for according to the corresponding relation of pre-configured header information and coprocessor core information, determines the coprocessor core information that described header information is corresponding, and sends described coprocessor core information.
And, described coprocessor 12 is also for receiving described coprocessor core information, and according to this coprocessor core information, described header information is dispensed to corresponding coprocessor core, impel described coprocessor core according to pre-configured header processing rule, determine the message executable operations information suitable with described header information.
In addition, should the data message disposable plates based on ATCA also comprise: second memory (not shown), for storing the corresponding relation of pre-configured header information and coprocessor core information.
The data traffic of the data message that wherein, described FPGA11 receives is 40G.
From concrete principle aspect, technique scheme of the present invention is elaborated below.
Fig. 2 is the principle configuration diagram of the data message disposable plates based on ATCA, as can be seen from Figure 2,, in whole framework, FPGA is the control centre of flow, played the effect of master chip, coprocessor (XLP) is that the companion chip as FPGA is used.Below respectively FPGA part and XLP are partly described.
To with FPGA part, in whole framework, FPGA has the SFI5.1 interface of a 17*3.125G to be connected on the 300PIN optical module of a 40G, in order to accept the input flow rate of single channel 40G, (be mainly 40GPOS, compatible 40GE), certainly, also can be connected to one with the subcard of 4 XFP modules, in order to realize the access of 4*10GPOS.
And in order to improve throughput of system, it is second memory that FPGA has also connected two TCAM() be used for pre-search rule, between two TCAM, adopted the mode of serial connection to connect the RX that the TX of FPGA is namely connected to TCAM1, the TX of TCAM1 is connected to the RX of TCAM2, the TX of TCAM2 is connected to the RX of FPGA, is all 12*6.25GILA bus.And, on FGPA, also connected 4 QDR chips (being first memory), wherein, the space of each QDR chip is 72Mb, be used for data cached stream when XLP searches in detail, each QDR is used independently controller to widen system cache total bandwidth.
In addition, in order to realize the communication of data, FPGA is upper also has the IL signal of one group of 40G bandwidth to be connected to xlp, and for the communication of self-defined association processing messages, indication xlp completes the operation of response, and the lookup result that obtains returning from XLP.And, FPGA has also realized the function of a part of exchange chip, concrete, FPGA has 2 40GE network interfaces to be connected to Zone2 connector, the service management data that are used for CPB to send are transmitted to XLP by 10,000,000,000 interfaces between FPGA and XLP, a part of flow can also be given to other PPB simultaneously to realize load balancing.Because FPGA does not support the electric agreement of 40GE-KR4, so be connected in series a BCM84328 on link, the QSFP+ bus of FPGA is changed into KR4 standard.In addition, FPGA has 16 10GE and 24 interfaces of 8 GE totals to be connected to zone3 connector, coordinates special a RTM board to realize descending being redirected or backflow interface.
And for XLP part, in whole framework, XLP is that the primary processor of writing processor and system management as data processing carrys out use.
Wherein, for data division, XIL has connected four DDR3 internal memories to preserve detailed rules data, when FPGA sends after searching message, in DDR3, searches.
Wherein, for administrative section, in XLP, need to have the control of photoelectric protection, need to communicate by letter with CPB with OPB, therefore need two GE networks to be connected to the base switching network of Zone2.In order to improve system business handling property, the administrative messag message of the rule list operation between CPB and PPB, walks the fabric exchange of 10GE, and the base exchange of GE is used for doing the management (being mainly hardware management) of independent of service specially, therefore, XLP has 10GE interface (XAUI) E to be connected on FPGA.And because the rule of FPGA is downloaded and the PCIE interface of managerial demand by XLP carries out, so XLP also to need to have PCIE to be connected to FPGA upper, the network interface of XLP and serial ports are drawn from front panel, facilitate system debug.Whether XLP has also connected SD card and the NAND Flash of startup use in addition, and by a circuit, automatically detect SD card and insert, if inserted, otherwise starts from SD card start-up from NAND Flash.
Fig. 3 is the principle schematic of the data flow of the data message disposable plates based on ATCA while processing, as can be seen from Figure 3, PPB is to each message of receiving, extract the five-tuple information (transport layer protocol of message, source ip, object ip, transport layer source port, transport layer destination interface), and search in a plurality of rule lists, which server decision is transmitted to by these five-tuple information is continued to analyze, or blocking-up or this message of continuation transmission, the present invention has used a FPGA and XLP on PPB, wherein, FPGA is responsible for flow access and buffer memory, data enter from the 40G optical module of front panel, extract afterwards the header information (comprising five-tuple information) of message, and according to header information, search the TCAM chip being connected with FPGA, and predict the regular hit situation of message in DDR3.Header information and prediction case, by interlacken interface, send to XLP, the rule list of preserving in XLP inquiry ddr3 internal memory, in this process, the initial data of message is kept in QDR buffer memory.XLP possesses 32 core cpus, wherein, the present invention uses No. 0 as CPU management, and the rule that other 31 CPU carry out service surface is tabled look-up, XLP receives the message five-tuple information transmitting from FPGA, by micro engine (MicroEngine) five-tuple distribution of information 31 CPU to service surface.Search after CPU completes rule searching in DDR3 result feedback sent back to FPGA to CPU0 unification,
FPGA determines the action that carry out message according to rule match result, have two kinds of mode of operations to be decided by the configuration of CPB here.
A kind of is shunt mode: if hit, to descending port repeat message otherwise dropping packets.E-Packet and likely have both direction, be specially between the plate of downlink port on RTM or Zone2 balancedly, FPGA determines from which mouthful to forward according to inner forwarding rule list and the result of hitting.All miss messages are all abandoned, and do not have any message and send from uplink port.
Another kind is filtered model: if hit, to descending port repeat message otherwise message is forwarded from another uplink port.To descending port repeat message, likely have both direction, be specially between the plate of downlink port on RTM or Zone2 balancedly, FPGA determines from which mouthful to forward according to inner forwarding rule list and the result of hitting.Whether no matter hit, most packet all will copy portion and send out from another uplink port, only has the packet that hits on a small quantity special rules only to descending port repeat, to there will not be on another uplink port.
In sum, by means of technique scheme of the present invention, by adopting the direct receiving data packets of FPGA, thereby avoided disposable plates when receiving data packets, to occur that the phenomenon of mass flow discrepancy weighing apparatus occurs, also avoided needing the trouble of additional configuration pre-processed board or interface board simultaneously, in addition, due to the processor that has adopted programmable FPGA as disposable plates, thereby make the algorithm that user requires that meets that data message disposable plates can adaptivity, avoid the excessive phenomenon of internal storage access pressure to occur, and because FPGA possesses data exchanging function in andante, from having avoided needing additional configuration exchange chip to do the trouble exchanging in plate, reduced the input cost of equipment, guaranteed the transmission rate of system, improved the performance performance of system.
The foregoing is only preferred embodiment of the present invention, in order to limit the present invention, within the spirit and principles in the present invention not all, any modification of doing, be equal to replacement, improvement etc., within all should being included in protection scope of the present invention.
Claims (6)
1. the data message disposable plates based on Advanced telecom computing architecture ATCA, is characterized in that, comprising:
On-site programmable gate array FPGA, for receiving data packets, and analyzes the described data message receiving, and determines the header information that described data message is corresponding, and sends this header information;
Coprocessor, be used for receiving described header information, and according to pre-configured header processing rule, determine the message executable operations information suitable with described header information, and send this message executable operations information, wherein, described header processing rule for record header information and with the corresponding relation of the suitable message executable operations information of this header information;
Described FPGA is also for receiving described message executable operations information, and according to operation corresponding to this message executable operations information and executing.
2. data message disposable plates according to claim 1, is characterized in that, described header information comprise following one of at least:
The source port information of the source address information of data transfer layer protocol information, transfer of data, the destination address information of transfer of data, transfer of data, the destination interface information of transfer of data.
3. data message disposable plates according to claim 1, is characterized in that, further comprises:
First memory, for determining after described header information at described FPGA, the data message that described FPGA is received carries out buffer memory.
4. data message disposable plates according to claim 1, it is characterized in that, described FPGA also, for according to the corresponding relation of pre-configured header information and coprocessor core information, determines the coprocessor core information that described header information is corresponding, and sends described coprocessor core information;
And, described coprocessor is also for receiving described coprocessor core information, and according to this coprocessor core information, described header information is dispensed to corresponding coprocessor core, impel described coprocessor core according to pre-configured header processing rule, determine the message executable operations information suitable with described header information.
5. data message disposable plates according to claim 4, is characterized in that, further comprises:
Second memory, for storing the corresponding relation of pre-configured header information and coprocessor core information.
6. according to the data message disposable plates described in any one in claim 1 to 5, it is characterized in that, the data traffic of the data message that described FPGA receives is 40G.
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| CN111404798A (en) * | 2020-03-09 | 2020-07-10 | 湖北微源卓越科技有限公司 | System and method for multi-user rule matching and flow replication |
| CN114124822A (en) * | 2021-11-29 | 2022-03-01 | 杭州迪普信息技术有限公司 | Message matching processing device and method |
| CN114124822B (en) * | 2021-11-29 | 2024-04-26 | 杭州迪普信息技术有限公司 | Message matching processing device and method |
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