CN103684354B - Ring oscillator circuit, ring oscillator and implementation method thereof - Google Patents

Abstract

The invention discloses a ring-shaped oscillation circuit, a ring-shaped oscillator and a realization method thereof, relating to the technical field of telecommunications. A technical problem that the required precision of a ring-shaped oscillation circuit device is high in the prior art is solved. The circuit comprises a current bias generating circuit and a ring-shaped oscillator level circuit. The ring-shaped oscillator level circuit comprises at least one level of first type of inverter and at least one level of second type of inverter. The current bias generating circuit is coupled with the first type of inverter. The output end of the first type of inverter is connected with the input end of the second type of inverter. The output end of the second type of inverter is connected with the input end of the first type of inverter.

Description

Ring oscillator circuit, ring oscillator and implementation method thereof

technical field

The invention relates to the technical field of telecommunication, in particular to a ring oscillator circuit, a ring oscillator and a realization method thereof.

Background technique

For most SOC (System on a Chip, system-on-a-chip) designs, the oscillator is an essential component, which can provide the clock for the chip. Among various types of oscillators, the ring oscillator does not require an external crystal or an inductor-capacitor tuning circuit, but only needs to use an odd number of inverters in series, and the output of the last stage is connected to the input of the first stage. can work. Considering its simple structure and low power consumption, ring oscillators are widely used in occasions where frequency accuracy is not required. However, the power supply voltage and ambient temperature have great influence on the output frequency of the ring oscillator. Therefore, the ring oscillator cannot meet the requirements of higher accuracy of the clock frequency system.

In order to achieve higher frequency accuracy, many technical solutions have optimized the structure of the ring oscillator. Among them, one of the more common structures is to form a ring oscillator through a current-limited inverter. Therefore, the oscillation frequency of the oscillator Related to the current, the power supply voltage and ambient temperature characteristics of the output frequency are improved by improving the reference current generation unit. However, the accuracy of the final output frequency of this type of solution mainly depends on whether the design of the reference current generating unit can just offset the corresponding voltage and temperature coefficient. Due to the great correlation between the temperature characteristics of the device and the process, the ideal result cannot be obtained if the compensation is insufficient or the compensation is too large. Therefore, for actual design, it is difficult to achieve better temperature and voltage characteristics. When the coefficient design is unreasonable, such as unreasonable compensation, there is a possibility of deteriorating temperature or voltage characteristics. Therefore, the output frequency of a common ring oscillator varies too much with the power supply voltage and ambient temperature, and cannot meet the system requirements for high frequency accuracy.

Moreover, for the ring oscillator solution composed of current-limited inverters, it is necessary to reasonably design the current generation circuit, configure a suitable temperature coefficient and compensate for the temperature characteristics of the subsequent oscillator, so the final temperature characteristics will affect the circuit The value of the middle device is more sensitive. Because the design results are too dependent on the device size and other design techniques in circuit design, in actual design, some factors that are difficult to control, such as layout mismatch and process deviation, will cause the expected compensation effect to be unable to be achieved.

Contents of the invention

In order to solve the technical problems of the prior art ring oscillating circuit in order to achieve the purpose of temperature compensation and power supply voltage compensation, resulting in high precision requirements for devices and relatively difficult design, the present invention provides a ring oscillating circuit, a ring oscillator and its implementation method.

A ring oscillator circuit comprising: a current bias generation circuit and a ring oscillator stage circuit;

The ring oscillator stage circuit includes at least one stage of a first type of inverter and at least one stage of a second type of inverter;

The current bias generating circuit is coupled to the first type of inverter; the output end of the first type of inverter is connected to the input end of the second type of inverter, and the output end of the second type of inverter is connected to the first type of inverter The input terminal connection of the inverter;

Among them, the first type of inverter is mainly a type of current-limited inverter; the second type of inverter is composed of a CMOS inverter.

Wherein, the current bias generation circuit includes a first PMOS, a second PMOS, a first NMOS, a second NMOS and a resistor R; wherein,

The gates of the first PMOS and the second PMOS are connected together to form a current mirror; the gate of the second PMOS is connected to its drain, and the gate and drain of the first NMOS are connected together and connected to the drain of the first PMOS , the gate of the second NMOS is connected to the gate of the first NMOS, the drain of the second NMOS is connected to the drain of the second PMOS, the source of the first NMOS is grounded, and the source of the second NMOS is connected to the resistor R One end of the resistor R is connected to ground.

Wherein, the first type of inverter includes a third PMOS, a third NMOS and at least one CMOS inverter; the current bias generating circuit is coupled with the first type of inverter, specifically including:

The gate of the third PMOS is connected to the gate of the second PMOS, and the gate of the third NMOS is connected to the gate of the first NMOS; the power supply and ground of the first CMOS inverter in the at least one CMOS inverter are respectively The drain of the third PMOS and the drain of the third NMOS are connected.

The output end of the first type inverter is connected to the input end of the second type inverter, and the output end of the second type inverter is connected to the input end of the first type inverter, specifically including:

The CMOS inverters of the first type and the second type of inverter are connected in series;

The output terminal of the last CMOS inverter after the series connection of the first type of inverter is connected to the input terminal of the first CMOS inverter after the series connection of the second type of inverter, and the last CMOS inverter after the series connection of the second type of inverter The output of one CMOS inverter is connected back to the input of the first CMOS inverter of the first type of inverter.

A ring oscillator comprising the ring oscillator circuit as claimed in the claims.

A method for implementing a ring oscillator, comprising:

The current of the power supply is biased to a current with a positive temperature coefficient independent of the power supply voltage through the current bias generation circuit;

controlling a first inverter in a ring oscillator stage circuit with the positive temperature coefficient current;

The first type of inverter is controlled by the positive temperature coefficient of the current to produce a positive power supply voltage, negative temperature coefficient and delayed inverter characteristics; and the second type of inverter generates a negative power supply voltage through the series connection of CMOS inverters , Inverter characteristics with positive temperature coefficient and time delay;

Through the interaction of the inverter characteristics of the first type of inverter and the inverter characteristics of the second type of inverter, a ring oscillator whose output frequency is temperature compensated and supply voltage compensated is formed.

The design of the scheme provided by the present invention is simple, because two kinds of inverters are used to form the oscillator, so the effect of temperature compensation can be achieved without intentionally setting the temperature coefficient. The purpose of power supply voltage compensation can be achieved without device design such as transistor matching. And low power consumption, the current bias circuit works in the sub-threshold region, so the working current is small, the mirrored current provides power to the inverter, and the power consumption is also small, because the current-limited inverter usually cannot be directly driven In the existing technology, an external module is usually connected with an inverter behind the ring oscillation stage to increase the drive, but in this design, the inverter that increases the drive behind becomes a part of the ring oscillation stage, thus saving The number of inverters in the inverter chain can achieve lower power consumption.

Description of drawings

The accompanying drawings are used to provide a further understanding of the present invention, and constitute a part of the description, and are used together with the embodiments of the present invention to explain the present invention, and do not constitute a limitation to the present invention. In the attached picture:

In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only These are some embodiments of the present invention. For those skilled in the art, other drawings can also be obtained according to these drawings without any creative effort.

Fig. 1 is the circuit diagram of the ring oscillator circuit that the embodiment 1 of the present invention provides;

FIG. 2 is a flow chart of the method provided by Embodiment 3 of the present invention.

Detailed ways

The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of the present invention. In addition, each of the following embodiments is an optional solution of the present invention, and the arrangement sequence and number of the embodiments have nothing to do with their preferred execution order.

Example 1

This embodiment provides a ring oscillator circuit, which includes: a current bias generation circuit 100 and a ring oscillator stage circuit 200;

The ring oscillator stage circuit 200 includes at least one stage of a first-type inverter 210 and at least one stage of a second-type inverter 211; wherein, the first-type inverter 210 is functionally used to limit current and belongs to is a current-limited inverter; the second inverter 211 includes a CMOS inverter.

The current bias generating circuit 100 is coupled to the first type inverter 210; the output end of the first type inverter 210 is connected to the input end of the second type inverter 211, and the output of the second type inverter 211 The terminal is connected to the input terminal of the first inverter 210 .

Wherein, in order to provide the first type of inverter 210 with a current that has no relation to the power supply voltage and has a positive temperature coefficient, the current bias generation circuit 100 provided in this embodiment includes a first PMOS103, a second PMOS104, a first NMOS102 , the second NMOS101 and the resistor R105; as shown in Figure 1,

The gates of the first PMOS103 and the second PMOS104 are connected together to form a current mirror; the gate of the second PMOS104 is connected to the drain of the second PMOS104, and the gate and drain of the first NMOS102 are connected together and connected to the drain of the first PMOS103 The gate of the second NMOS101 is connected to the gate of the first NMOS102, the drain of the second NMOS101 is connected to the drain of the second PMOS104, the source of the first NMOS102 is grounded, and the source of the second NMOS101 One end of the resistor R105 is connected, and the other end of the resistor R105 is grounded.

Specifically, the first type of inverter 210 includes a third PMOS204, a third NMOS205, and at least one CMOS201 inverter; the current bias generation circuit 100 is coupled to the first type of inverter 210, specifically including:

The gate of the third PMOS204 is connected to the gate of the second PMOS104, and the gate of the third NMOS205 is connected to the gate of the first NMOS102;

The power supply and the ground of the first CMOS inverter 201 among the at least one CMOS inverter 201 are respectively connected to the drain of the third PMOS 204 and the drain of the third NMOS 205 .

In a preferred solution, the output end of the first type inverter 210 is connected to the input end of the second type inverter 211, and the output end of the second type inverter 211 is connected to the input end of the first type inverter 210 connections, including:

The CMOS inverters of the first type inverter 210 and the second type inverter 211 are connected in series;

The output terminal of the last CMOS inverter connected in series in the first type inverter 210 is connected to the input end of the first CMOS inverter after the series connection of the second type inverter 211, and the second type inverter 211 The output terminal of the last CMOS inverter in series is connected back to the input terminal of the first CMOS inverter of the first type inverter 210 .

Wherein, the first type of inverter includes a CMOS inverter; the number of stages of the CMOS inverter chain formed by the first type of inverter and the second type of inverter is an odd number of stages.

Taking FIG. 1 as an example, the ring oscillator circuit provided by this embodiment will be described in detail below. It includes a current bias generation circuit 100 and a ring oscillator stage 200, wherein the ring oscillator stage 200 includes at least one stage of current-limited inverter (the first inverter 210 shown in FIG. 1 ) and at least one stage CMOS inverter (the second inverter 211 shown in FIG. 1 ). Figure 1 shows a circuit diagram of a three-stage ring oscillator circuit composed of a current-limited inverter and a two-stage CMOS inverter. In fact, the number of stages of the inverter chain composed of these two inverters can also be five or seven or other odd-numbered stages, that is, the odd-numbered stages refer to the first type of inverter and the second type of inverter The total number of devices is an odd number.

The current bias generating circuit 100 is composed of a first PMOS103, a second PMOS104, a first NMOS102, a second NMOS101 and R105, wherein the gates of the first PMOS103 and the second PMOS104 are connected together to form a current mirror, while the gates of the second PMOS104 The gate and drain of the first NMOS102 are connected together and connected with the drain of the first PMOS103, the gate of the second NMOS101 is connected with the gate of the first NMOS102, and the drain of the second NMOS101 The source of the first NMOS 102 is connected to the ground, the source of the second NMOS 101 is connected to one end of the resistor R105, and the other end of the resistor R105 is connected to the ground.

The ring oscillator stage circuit 200 is composed of a third PMOS204, a third NMOS205, and three sets of inverters 201, 202, and 203. The gate of the third PMOS204 is connected to the gate of the second PMOS104, and the third NMOS205 is connected to the gate of the first NMOS102. The gate is connected, and the power supply and ground of the first CMOS inverter 201 are respectively connected to the drains of the third PMOS204 and the third NMOS205, and the output of the inverter 204 is connected to the second CMOS inverter 202 (ie, the second The first inverter in the inverter) is connected to the input terminal, and the output of the second CMOS inverter 202 is connected to the third CMOS inverter 203 (that is, each inverter in the second inverter is connected in series. The input of the last CMOS inverter) is connected, and the output of the third CMOS inverter is connected back to the first CMOS inverter 201 (inverter 201 in FIG. 1 is the first inverter The first inverter after each inverter is connected in series is also the input terminal of the last inverter).

Referring to FIG. 1 , the principle of the ring oscillator circuit provided by this embodiment is as follows: first, the current bias circuit 100 generates a current on R105 through the VGS difference between the first NMOS102 and the second NMOS101, and the magnitude of the current has nothing to do with the power supply voltage, with It has a positive temperature coefficient and flows through the second PMOS104/second NMOS101 branch. Due to the 1:1 mirror relationship between the first PMOS103 and the second PMOS104, the same current flows on the first PMOS103/first NMOS102 branch. Through the current mirror composed of the second PMOS104 transistor and the third PMOS204 transistor, the current of the second PMOS104 is mirrored to the branch of the third PMOS204. Through the current mirror composed of the first NMOS102 tube and the third NMOS205 tube, the current of the first NMOS102 is mirrored to the branch of the third NMOS205, so the charging current of the first-stage inverter 201 is the current flowing through the second PMOS104, The discharge current of the first-stage inverter 201 is the current flowing through the third NMOS 204. The characteristics of the charge and discharge current value determine the delay characteristics of this stage of inverter. The output of the first-stage inverter 201 is connected to the ordinary CMOS behind The inverters 202 and 203 form a ring oscillator chain, and the final oscillation frequency is determined by the total delay of the inverter chain.

Wherein, the value of the current I generated by the current bias circuit 100 on the PMOS103/NMOS102 and PMOS104/NMOS101 branches is the difference between the VGS of the NMOS102 tube and the VGS of the NMOS104 tube compared to the resistance value of the resistor R105, as shown in the following formula (1)

$\mathrm{<span\; class="notranslate">\; I</span>}<span\; class="notranslate">\; =</span>\frac{{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; GSMN</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; N</span>}}_{\mathrm{<span\; class="notranslate">\; GSMN</span>}\mathrm{<span\; class="notranslate">\; 2</span>}}}{\mathrm{<span\; class="notranslate">\; R</span>}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; )</span>$

Since NMOS102 and NMOS101 work in the subthreshold region, formula (1) can be further written as

$\mathrm{<span\; class="notranslate">\; I</span>}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; no</span>}{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; T</span>}}\mathrm{<span\; class="notranslate">\; ln</span>}\mathrm{<span\; class="notranslate">\; m</span>}}{\mathrm{<span\; class="notranslate">\; R</span>}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; )</span>$

where M is the ratio of the width-to-length ratio of MN2 to MN1, VT is the thermal voltage, which has a positive temperature coefficient, and n is the subthreshold slope factor. When the resistor is a poly resistor, the resistance has a negative temperature coefficient, so the current has a positive temperature coefficient. Through the PMOS current mirror, the current of the first-stage current-limited inverter is proportional to the temperature, and the delay of this stage of inverter decreases with the increase of temperature; the threshold voltage of this stage of inverter increases with the increase of power supply voltage. increase, so that the inverter delay increases as the supply voltage increases.

The second type of inverter in the inverter chain is an ordinary CMOS inverter. The delay of this inverter increases with the increase of temperature and decreases with the increase of power supply voltage.

The temperature and voltage characteristics of these two kinds of inverters are just opposite, and the use of these two kinds of inverters in the oscillator loop can realize the functions of temperature compensation and voltage compensation. By adjusting the temperature coefficient of the current generating circuit, the temperature and voltage characteristics of the oscillator can be compensated in a targeted manner. Therefore, the temperature and voltage compensation function of the ring oscillating circuit is not sensitive to the value of specific components inside the circuit, so the purpose of temperature and voltage compensation can be achieved when used.

In the ring oscillating circuit provided by this embodiment, since the temperature characteristics and power supply voltage characteristics of the first type of inverter delay and the second type of inverter delay are just opposite, the total delay of the inverter chain varies between temperature and power supply voltage The purpose of compensation is achieved in terms of characteristics, so that the output frequency of the oscillator achieves the purpose of temperature compensation and power supply voltage compensation.

Example 2

This embodiment provides a ring oscillator. The ring oscillator includes the ring oscillator circuit described in Embodiment 1, and the specific content of the ring oscillator is not repeated here.

Example 3

This embodiment provides a method for implementing a ring oscillator, as shown in FIG. 2 , including:

Step 101, using the current bias generation circuit to bias the current of the power supply to a current with a positive temperature coefficient independent of the power supply voltage;

Step 102, using the positive temperature coefficient current to control the first inverter in the ring oscillator stage circuit;

Step 103, the first type of inverter is controlled by the positive temperature coefficient current to generate a positive power supply voltage, a negative temperature coefficient and a time-delayed inverter characteristic;

Step 104, at the same time that the inverter characteristics are generated in step 103, the second type of inverter generates negative power supply voltage, positive temperature coefficient and time-delayed inverter characteristics through the series connection of each CMOS inverter;

Step 105, through the interaction of the inverter characteristics of the first type of inverter and the inverter characteristics of the second type of inverter, a ring oscillator whose output frequency is temperature compensated and power supply voltage compensated is formed.

For example: Referring to FIG. 1, firstly, the current bias circuit 100 generates a current on R105 through the VGS difference between the first NMOS102 and the second NMOS101. /second NMOS 101 branch, due to the 1:1 mirror relationship between the first PMOS 103 and the second PMOS 104 , the same current flows on the first PMOS 103 /first NMOS 102 branch. Through the second PMOS104 tube and the third

The current mirror composed of PMOS204 tubes mirrors the current of the second PMOS104 to the branch of the third PMOS204. Through the current mirror composed of the first NMOS102 tube and the third NMOS205 tube, the current of the first NMOS102 is mirrored to the branch of the third NMOS205, so the charging current of the first-stage inverter 201 is the current flowing through the second PMOS104, The discharge current of the first-stage inverter 201 is the current flowing through the third NMOS 204. The characteristics of the charge and discharge current value determine the delay characteristics of this stage of inverter. The output of the first-stage inverter 201 is connected to the ordinary CMOS behind The inverters 202 and 203 form a ring oscillator chain, and the final oscillation frequency is determined by the total delay of the inverter chain.

Please refer to the ring oscillating circuit in Embodiment 1 for the specific implementation of each step, which will not be repeated here.

The implementation method provided by the present invention uses two kinds of inverters that can produce opposite temperature and power supply voltage characteristics, so the effect of temperature compensation can be achieved without deliberately setting the temperature coefficient. The technical effects of power supply voltage compensation and low power consumption can be achieved without device design such as transistor matching.

In the above methods provided in the embodiments of the present invention, although the order of performing the steps is given, this order is only a preferred implementation manner of the present invention. Obviously, those skilled in the art can perform various equivalent transformations on the order of execution of the steps of the method according to the above method, that is to say, the above steps or some of the steps in the method of the embodiment of the present invention can be executed in other orders, or Execute at the same time. For example: step 104 is executed first, and then step 103 is executed; or step 103 and step 104 are executed simultaneously. Therefore, the execution sequence of the steps described in the above method is not limited to one mode provided in the embodiment.

The above description is only a specific embodiment of the present invention, but the present invention can have a variety of different forms of specific embodiments, and the above is an example of the present invention in conjunction with the accompanying drawings, which does not mean that the specific implementation of the application of the present invention The method can only be limited to these specific implementations, and those skilled in the art should understand that the specific implementations provided above are only some examples of various preferred implementations, and any specific implementation that embodies the claims of the present invention All should be within the scope of protection required by the claims of the present invention; those skilled in the art can modify the technical solutions described in the above specific embodiments, or perform equivalent replacements for some of the technical features. Any modification, equivalent replacement or improvement made within the spirit and principle of the present invention shall be included in the protection scope of the claims of the present invention.

Claims (6)

1. A ring oscillator circuit, comprising: a current bias generating circuit and a ring oscillator stage circuit; the ring oscillator stage circuit comprises at least one stage of first inverter and at least one stage of second inverter; the current bias generating circuit is coupled with the first inverter; the output end of the first inverter is connected with the input end of the second inverter, the output end of the second inverter is connected with the input end of the first inverter, and the current bias generating circuit comprises a first PMOS, a second PMOS, a first NMOS, a second NMOS and a resistor R; the grid electrodes of the first PMOS and the second PMOS are connected together to form a current mirror; the grid electrode of the second PMOS is connected with the drain electrode of the second PMOS, the grid electrode of the first NMOS is connected with the drain electrode of the first PMOS, the grid electrode of the second NMOS is connected with the grid electrode of the first NMOS, the drain electrode of the second NMOS is connected with the drain electrode of the second PMOS, the source electrode of the first NMOS is grounded, the source electrode of the second NMOS is connected with one end of a resistor R, the other end of the resistor R is connected with the ground, and the first inverter comprises a third PMOS, a third NMOS and at least one CMOS inverter; the current bias generating circuit is coupled with the first inverter, and specifically comprises: the grid electrode of the third PMOS is connected with the grid electrode of the second PMOS, and the grid electrode of the third NMOS is connected with the grid electrode of the first NMOS; and the power supply and the ground of the first CMOS inverter of the at least one CMOS inverter are respectively connected with the drain electrode of the third PMOS and the drain electrode of the third NMOS.

2. The ring oscillator circuit of claim 1 wherein the first inverter comprises a current limited inverter; the second inverter comprises a CMOS inverter.

3. The ring oscillator circuit according to claim 1, wherein the output of the first inverter is connected to the input of the second inverter, and the output of the second inverter is connected to the input of the first inverter, specifically comprising: each CMOS inverter of the first and second inverters is connected in series; the output end of the last CMOS phase inverter after the first phase inverter is connected in series is connected with the input end of the first CMOS phase inverter after the second phase inverter is connected in series, and the output end of the last CMOS phase inverter after the second phase inverter is connected in series is connected back to the input end of the first CMOS phase inverter of the first phase inverter.

4. A ring oscillator circuit according to claim 3 wherein the chain of CMOS inverters formed by the first and second inverters is an odd number of stages.

5. A ring oscillator comprising the ring oscillator circuit of any one of claims 3 to 4.

6. A method for implementing the ring oscillator of claim 5, comprising: the current of the power supply is biased to be the current of the positive temperature coefficient irrelevant to the power supply voltage through a current bias generating circuit; controlling a first inverter in a ring oscillator stage circuit by using the current with the positive temperature coefficient; the first inverter is controlled by the current of the positive temperature coefficient to generate the inverter characteristics of positive power supply voltage, negative temperature coefficient and time delay; the second inverter generates the inverter characteristics of negative power supply voltage, positive temperature coefficient and time delay through the series connection of all the CMOS inverters; by the interaction of the inverter characteristic of the first inverter with the inverter characteristic of the second inverter, a ring oscillator whose output frequency is temperature compensated and whose supply voltage is compensated is formed.