CN103681264B - The forming method of semiconductor device and the forming method of MOS transistor - Google Patents

Abstract

The forming method of a kind of semiconductor device and the forming method of MOS transistor.Wherein, the forming method of semiconductor device includes: provide substrate, described substrate is formed pseudo-grid, the top of dummy gate and sidewall are coated with mask layer；The mask layer surface of substrate surface and pseudo-grid top is carried out ion implanting, forms ion implanted layer；Remove the mask layer on pseudo-grid sidewall；Remove described ion implanted layer.The formed semiconductor device of the present invention and the stable performance of MOS transistor.

Description

Method for forming semiconductor device and method for forming MOS transistor

technical field

The invention relates to the technical field of semiconductor manufacturing, in particular to a method for forming a semiconductor device and a method for forming a MOS transistor.

Background technique

In the existing manufacturing process of semiconductor devices, since stress can change the energy gap and carrier mobility of silicon materials, it has become an increasingly common means to improve the performance of MOS transistors through stress. Specifically, by properly controlling the stress, the mobility of carriers (electrons in NMOS transistors and holes in PMOS transistors) can be increased, thereby increasing the driving current, thereby greatly improving the performance of MOS transistors.

At present, an embedded silicon germanium (Embedded SiGe) technology is adopted, that is, a silicon germanium layer is first formed in a region where a heavily doped region needs to be formed, and then doped to form a heavily doped region of a MOS transistor. The silicon germanium layer is formed to introduce compressive stress caused by lattice mismatch between silicon and silicon germanium (SiGe), so as to improve the performance of the MOS transistor.

In order to improve the performance of MOS transistors, in addition to forming a silicon germanium layer in the heavily doped region of the MOS transistor, after forming the heavily doped region of the MOS transistor and before forming a conductive plug connected to the heavily doped region, the MOS A metal silicide layer is formed on the surface of the heavily doped region of the transistor to reduce the contact resistance between the conductive plug of the MOS transistor and the heavily doped region.

For more information on the formation process of MOS transistors, please refer to US Patent No. US7569443.

However, the performance of the MOS transistor formed by the prior art is not stable enough.

Contents of the invention

The problem to be solved by the present invention is to provide a method for forming a semiconductor device and a method for forming a MOS transistor, and improve the stability of the formed semiconductor device and MOS transistor.

In order to solve the above problems, the present invention provides a method for forming a semiconductor device, comprising: providing a substrate on which a dummy gate is formed, and the top and side walls of the dummy gate are covered with a mask layer; Ion implantation is performed on the surface of the substrate and the surface of the mask layer on the top of the dummy gate to form an ion implantation layer; the mask layer on the sidewall of the dummy gate is removed; and the ion implantation layer is removed.

The present invention also provides a method for forming a MOS transistor, including: providing a substrate, on which a dummy gate structure is formed, and the dummy gate structure includes a gate dielectric layer and a dummy gate on the gate dielectric layer. , the top and sidewalls of the dummy gate structure are covered with a mask layer; using the mask layer as a mask, etching the substrates on both sides of the dummy gate structure to form grooves, and The groove is filled with a silicon germanium layer; the surface of the substrate and the silicon germanium layer and the surface of the mask layer on the top of the dummy gate structure are ion-implanted to form an ion implantation layer; the dummy gate structure sidewall is removed mask layer; removing the ion implantation layer; performing lightly doped ion implantation on the substrates on both sides of the dummy gate structure to form lightly doped regions; forming sidewalls covering the sidewalls of the dummy gate structure; The germanium silicon layer is implanted with heavily doped ions to form a heavily doped region.

Compared with the prior art, the technical solution of the present invention has the following advantages:

Before removing the mask layer on the sidewall of the dummy gate, ion implantation is performed on the surface of the substrate and the surface of the mask layer on the top of the dummy gate to form an ion implantation layer. In the process of removing the mask layer on the sidewall of the dummy gate, due to The removal rate of the ion implantation layer by the removal process is much lower than the removal rate of the mask layer, and the ion implantation layer can protect the mask layer on the top of the dummy gate, avoiding damage to the substrate caused by the removal process and exposure of the top of the dummy gate, Further, influence on the subsequent process is avoided, and the stability of the formed semiconductor device is improved.

Further, after the ion implantation layer is formed, an annealing treatment is performed to activate the dopant ions in the ion implantation layer, thereby better protecting the substrate and the mask layer on the top of the dummy gate, and improving the stability of the formed semiconductor device .

Description of drawings

1 to 7 are schematic cross-sectional structure diagrams of MOS transistors formed at various stages in an embodiment of a method for forming a MOS transistor according to the present invention.

detailed description

As mentioned in the background section, the performance of MOS transistors formed in the prior art is not stable enough.

After research by the inventors, it was found that the performance of MOS transistors in the prior art is not stable enough, because when the metal silicide layer on the surface of the heavily doped region of the MOS transistor is formed, the metal silicide will be formed on the dummy gate not covered by the mask layer. The top of the structure is piled up. After removing the mask layer on the top of the dummy gate structure, part of the dummy gate is still covered by metal silicide, which is not conducive to the removal of the dummy gate and the formation of the gate, resulting in poor morphology of the formed gate. The performance of the formed MOS transistor is not stable.

In view of the above problems, the inventor has proposed a method for forming a semiconductor device. After forming a dummy gate whose top and sidewalls are covered with a mask layer on the substrate, ionization is carried out on the surface of the substrate and the surface of the mask layer on the bottom of the dummy gate. implanting to form an ion implantation layer, and then removing the mask layer and the ion implantation layer on the sidewall of the dummy gate in sequence. In the formation method of the semiconductor device of the present invention, before removing the mask layer on the sidewall of the dummy gate, an ion implantation layer is formed on the surface of the substrate and the top mask layer of the dummy gate by an ion implantation process, so as to mask the mask layer on the sidewall of the dummy gate. During the layer removal process, the substrate and the mask layer on the top of the dummy gate are protected, so as to prevent the premature exposure of the top of the dummy gate from affecting the subsequent formation process of the semiconductor device, and improve the stability of the formed semiconductor device.

Referring to FIG. 1 to FIG. 7 , the method for forming a semiconductor device and the method for forming a MOS transistor of the present invention will be described in detail through an embodiment.

Referring to FIG. 1 , a substrate 101 is provided. A dummy gate structure is formed on the substrate 101 . The top and sidewalls of the dummy gate structure are covered with a mask layer 107 a.

In this embodiment, the dummy gate structure includes a gate dielectric layer 103 on the substrate 101 and a dummy gate 105 on the gate dielectric layer 103 . The material of the substrate 101 is silicon, silicon germanium, or silicon-on-insulator, etc., and an isolation structure (not shown) is formed in the substrate 101. The isolation structure may be a silicon oxide shallow trench isolation structure. The isolation structure is used to isolate devices formed on the surface of the substrate 101 . The material of the gate dielectric layer 103 is a high-k dielectric material such as silicon oxide or hafnium oxide, and the material of the dummy gate 105 is amorphous silicon or doped polysilicon. The mask layer 107a is made of silicon nitride.

Continuing to refer to FIG. 1 , using the mask layer 107 a as a mask, the substrate 101 on both sides of the dummy gate structure is etched to form a groove, and the silicon germanium layer 109 a is filled in the groove.

Preferably, the groove is sigma-shaped (that is, Σ-shaped), so that after the groove is filled with the silicon germanium layer 109a, the mobility of carriers on the channel region of the formed MOS transistor is improved, thereby improving the formed The response rate of the MOS transistor. The sigma-shaped groove can be formed by combining wet etching and dry etching, and the silicon germanium layer 109a can be formed by an epitaxial growth process to form a sigma-shaped groove and fill the sigma-shaped groove The method for the silicon germanium layer 109a is well known to those skilled in the art, and will not be repeated here.

It should be noted that, in this embodiment, except for filling the sigma-shaped groove, the silicon germanium layer 109a has a surface slightly higher than the surface of the substrate 101, so that when the contact electrode connected to the heavily doped region is formed, Reduce the consumption of heavily doped regions and reduce leakage.

In other embodiments, the upper surface of the silicon germanium layer 109 a may also be flush with the surface of the substrate 101 , which does not limit the protection scope of the present invention.

Referring to FIG. 2, ion implantation is performed on the surface of the substrate 101 and the silicon germanium layer 109a and the surface of the mask layer 107a on the top of the dummy gate structure in FIG. layer 110 and ion implantation layer 108 covering the surface of mask layer 107b on top of the dummy gate structure.

In this embodiment, the direction of ion implantation on the surface of the substrate 101 and the silicon germanium layer 109a and the surface of the mask layer 107a on the top of the dummy gate structure in FIG. The included angles are all 0°, that is, the ion implantation direction for forming the ion implantation layer 108 is perpendicular to the upper surface of the substrate 101 and the upper surface of the silicon germanium layer 109a.

The ions implanted into the silicon germanium layer 109a and the mask layer 107a on the top of the dummy gate structure are phosphorus ions, boron ions, boron difluoride ions, arsenic ions, germanium ions, argon ions, carbon ions, oxygen ions, One or more of nitrogen ions, fluoride ions, silicon ions, sulfur ions, and chloride ions.

In this embodiment, the ions implanted into the silicon germanium layer 109a and the mask layer 107a on the top of the dummy gate structure are oxygen ions, and the implantation dose of the ion implantation is 10 ¹⁰ /cm ² -10 ²³ /cm ² , the implantation energy is 1KeV-5000KeV.

By performing ion implantation on the surface of the mask layer 107a on the top of the dummy gate structure, part of the silicon nitride on the surface of the mask layer 107a is combined with oxygen ions to form silicon oxynitride, and then the ion implantation layer 108 covering the mask layer 107b is formed. ; By implanting oxygen ions on the surface of the substrate 101 and the silicon-germanium layer 109a, the oxygen ions are combined with germanium atoms and/or germanium atoms in the substrate 101 and the silicon-germanium layer 109a to form on the surface of the substrate 101 and the silicon-germanium layer 109b The ion implantation layer 110 is made of germanium oxide and/or silicon oxide.

Preferably, after performing ion implantation on the surface of the substrate 101 and the silicon germanium layer 109a and the surface of the mask layer 107a on the top of the dummy gate structure, an annealing treatment is performed to activate the oxygen ions in the ion implantation layers 108 and 110, The content of silicon oxynitride in the ion implantation layer 108 is increased, and the content of silicon oxide and/or germanium oxide in the ion implantation layer 110 is increased.

In this embodiment, the annealing treatment is rapid thermal annealing, the temperature of the annealing treatment is 100°C-1400°C, the gas is nitrogen, argon, hydrogen or helium, and the time is 0s-120s.

Referring to FIG. 3 , the mask layer 107b on the sidewall of the dummy gate structure in FIG. 2 is removed.

In this embodiment, the method of removing the mask layer 107b on the sidewall of the dummy gate structure is wet etching, the solution of the wet etching is a phosphoric acid solution, and the temperature of the phosphoric acid solution is 110° C. to 180° C. , the wet etching time is 30s-600s.

When the mask layer 107b on the sidewall of the dummy gate structure is removed by phosphoric acid solution, since the etching rate of phosphoric acid solution to silicon nitride is much higher than that of silicon oxynitride, silicon oxide and germanium oxide, the ion implantation layer 108 can effectively protect the mask layer 107c located between the ion implantation layer 108 and the dummy gate 105 from being etched, and the ion implantation layer 110 can effectively protect the silicon germanium layer 109b and the substrate 101 from being etched.

Referring to FIG. 4 , the ion implantation layers 108 and 110 in FIG. 3 are removed, and lightly doped ion implantation is performed on the substrate 101 on both sides of the dummy gate structure to form a lightly doped region (not shown).

In this embodiment, the method for removing the ion implantation layers 108 and 110 is wet etching, the solution of the wet etching is hydrofluoric acid solution, and the volume of hydrofluoric acid and water in the hydrofluoric acid solution is The ratio is 1:10 to 1:1000, and the wet etching time is 10s to 1800s.

In this embodiment, the formed MOS transistors are PMOS transistors or NMOS transistors. When forming a PMOS transistor, the ions implanted by the lightly doped ions are boron ions or boron difluoride ions; when forming an NMOS transistor, the ions implanted by the lightly doped ions are phosphorus ions, arsenic ions or antimony ions. The process of forming the lightly doped region is a well-known technique for those skilled in the art, and will not be repeated here.

Referring to FIG. 5 , a sidewall 111 covering the sidewall of the dummy gate structure is formed, and then heavily doped ion implantation is performed on the silicon germanium layer 109 b to form a heavily doped region (not shown).

In this embodiment, the sidewall 111 is a single-layer structure, and its material can be silicon nitride; in other embodiments, the sidewall 111 can also be a laminated structure, such as ONO (oxide-nitride-oxide) structure. Specifically, a silicon nitride material or an ONO stack can be formed on the surfaces of the silicon germanium layer 109b, the substrate 101, and the mask layer 107c, and then the silicon nitride material or the ONO stack can be etched to form a covering dummy gate structure. The side wall 111 of the side wall.

In this embodiment, the ions to be implanted into the germanium-silicon layer 109b are determined by the type of the formed MOS transistor, which is the same as the type of ions implanted into the lightly doped region of the MOS transistor, and will not be repeated here. .

Referring to FIG. 6 , using the mask layer 107c on the top of the dummy gate structure as a mask, a metal silicide layer 113 is formed on the surface of the substrate 101 and the silicon germanium layer 109b.

In this embodiment, the material of the metal silicide layer 113 is one or a combination of NiSi or NiSi ₂ , which is used to reduce the contact resistance between the heavily doped region and the corresponding conductive plug.

The method for forming the metal silicide layer 113 can be: first form a nickel (Ni) metal layer on the surface of the substrate 101 and the silicon germanium layer 109b, and then perform an annealing treatment to make the nickel atoms in the nickel metal layer and the substrate 101 and The silicon atoms on the surface of the silicon germanium layer 109 b combine to form the metal silicide layer 113 . The method for forming the nickel metal layer is a physical vapor deposition process.

Referring to FIG. 6, the mask layer 107c in FIG. 5 is removed.

In this embodiment, the mask layer 107c is removed by wet etching, the wet etching solution is a phosphoric acid solution, the temperature of the phosphoric acid solution is 110° C. to 180° C., and the wet etching time is 10s～1000s.

Continuing to refer to FIG. 6 , the dummy gate 105 in FIG. 5 is removed to expose the gate dielectric layer 103 .

In this embodiment, the method for removing the dummy gate 105 is dry etching, and its specific process is known to those skilled in the art, and will not be repeated here.

Referring to FIG. 7 , a gate 115 is formed on the gate dielectric layer 103 , and the upper surface of the gate 115 is flush with the upper surface of the spacer 111 .

In this embodiment, the material of the grid 115 is metal (such as: tungsten, titanium, tantalum, ruthenium, zirconium, cobalt, copper, aluminum, lead, platinum, tin, silver or gold), conductive composite material (such as nitrogen Tantalum oxide, titanium nitride, tungsten silicide, tungsten nitride, ruthenium oxide, nickel silicide, etc.), carbon nanotubes or conductive carbon.

In another embodiment, after the MOS transistor in FIG. 5 is formed, removing the mask layer 107c and the dummy gate 105 in FIG. 5 and forming the gate 115 in FIG. 7 can also be performed through the following steps:

Forming a dielectric layer covering the surface of mask layer 107c, sidewall 111, substrate 101 and metal silicide layer 113 in FIG. 5;

planarizing the dielectric layer and the mask layer 107c to expose the dummy gate 105;

removing the dummy gate 105, and forming a gate 115 on the gate dielectric layer 103, the upper surface of the gate 115 being flush with the upper surface of the dielectric layer;

The dielectric layer is removed.

In this embodiment, the material of the dielectric layer is a low-k material or an ultra-low-k material.

In other embodiments, the above-mentioned dielectric layer may not be removed, so as to form a conductive plug connected to the metal silicide layer 113 in the dielectric layer, so that the heavily doped region of the formed MOS transistor is electrically connected to the external power supply. connect.

In the above-mentioned embodiment, after the substrate is etched using the mask layer covering the dummy gate structure as a mask, the groove is formed, and the silicon germanium layer is filled in the groove, the silicon germanium layer and the dummy gate are firstly etched. The mask layer on the top of the pole structure is ion-implanted to form an ion-implanted layer, and then the mask layer and the ion-implanted layer on the sidewall of the dummy gate structure are removed in sequence; in the process of removing the mask layer on the sidewall of the dummy gate structure , because the etching rate of the ion implantation layer by the etching process is much lower than the etching rate of the mask layer, the ion implantation layer can protect the silicon germanium layer and the mask layer on the top of the dummy gate structure from being removed, avoiding etching The etch process will cause damage to the silicon germanium layer and ensure that the top of the dummy gate structure is completely covered by the mask layer, so as to avoid the accumulation of metal silicide on the top of the gate structure during the formation of the metal silicide layer on the heavily doped region, so as to facilitate the subsequent dummy gate structure. The removal of the gate and the formation of the gate improve the stability of the formed MOS transistor.

The present invention also provides a method for forming a semiconductor device, comprising: providing a substrate, on which a dummy gate is formed, and the top and side walls of the dummy gate are covered with a mask layer; Ion implantation is performed on the surface of the mask layer on the top of the dummy gate to form an ion implantation layer; the mask layer on the sidewall of the dummy gate is removed; and the ion implantation layer is removed. For the specific formation process, refer to the corresponding steps in the embodiment of the method for forming the MOS transistor. In the forming method of the semiconductor device of the present invention, before removing the mask layer positioned on the sidewall of the dummy gate, ion implantation is first performed on the surface of the substrate and the surface of the mask layer on the top of the dummy gate to form an ion implantation layer, and the formed ion implantation layer In the process of removing the mask layer on the sidewall of the dummy gate, the mask layer on the top of the dummy gate can be protected, thereby ensuring that the top of the dummy gate is covered by the mask layer, effectively avoiding the subsequent process from affecting the shape or structure of the top of the dummy gate. Influenced to improve the performance of the formed semiconductor device.

Claims (14)

1. A method for forming a semiconductor device, characterized in that, comprising: A substrate is provided, a dummy gate is formed on the substrate, and a mask layer is covered on the top and side walls of the dummy gate; performing ion implantation on the surface of the substrate and the surface of the mask layer on the top of the dummy gate to form an ion implantation layer; Perform annealing treatment, the annealing treatment is rapid thermal annealing, the temperature of the annealing treatment is 100°C-1400°C, the annealing gas is nitrogen, argon, hydrogen or helium, and the annealing time is 0s-120s; removing the mask layer on the sidewall of the dummy gate; removing the ion implantation layer; A metal silicide layer is formed on the surface of the substrate by using the mask layer on the top of the dummy gate as a mask. 2. The method for forming a semiconductor device according to claim 1, wherein the mask layer is made of silicon nitride. 3. The method for forming a semiconductor device according to claim 1 or 2, wherein the ions of the ion implantation are phosphorus ions, boron ions, boron difluoride ions, arsenic ions, germanium ions, argon ions, carbon ions, etc. One or more of ions, oxygen ions, nitrogen ions, fluorine ions, silicon ions, sulfur ions, and chloride ions, and the ion implantation direction is perpendicular to the upper surface of the substrate. 4. The method for forming a semiconductor device according to claim 3, wherein when the ions to be implanted are oxygen ions, the implantation energy is 1KeV-5000KeV, and the implantation dose is 10 ¹⁰ /cm ² -10 ²³ /cm ² . 5. The method for forming a semiconductor device according to claim 4, wherein the method for removing the ion implantation layer is wet etching, the solution of the wet etching is a hydrofluoric acid solution, and the hydrogen The volume ratio of hydrofluoric acid to water in the hydrofluoric acid solution is 1:10-1:1000, and the wet etching time is 10s-1800s. 6. the forming method of semiconductor device as claimed in claim 1 or 2 is characterized in that, the method for removing the mask layer on the dummy gate sidewall is wet etching, and the solution of described wet etching is phosphoric acid solution , the temperature of the phosphoric acid solution is 110° C. to 180° C., and the wet etching time is 30s to 600s. 7. The method for forming a semiconductor device according to claim 1, wherein the material of the metal silicide layer is one or a combination of _NiSi2 and NiSi. 8. A method for forming a MOS transistor, comprising: A substrate is provided, and a dummy gate structure is formed on the substrate, the dummy gate structure includes a gate dielectric layer and a dummy gate on the gate dielectric layer, and the top and side walls of the dummy gate structure are covered with mask layer; Using the mask layer as a mask, etching the substrates on both sides of the dummy gate structure to form a groove, and filling the groove with a silicon germanium layer; performing ion implantation on the surface of the substrate and the silicon germanium layer and the surface of the mask layer on the top of the dummy gate structure to form an ion implantation layer; Perform annealing treatment, the annealing treatment is rapid thermal annealing, the temperature of the annealing treatment is 100°C-1400°C, the annealing gas is nitrogen, argon, hydrogen or helium, and the annealing time is 0s-120s; removing the mask layer on the sidewall of the dummy gate structure; removing the ion implantation layer; Lightly doped ion implantation is performed on the substrates on both sides of the dummy gate structure to form lightly doped regions; forming sidewalls covering the sidewalls of the dummy gate structure; performing heavily doped ion implantation on the silicon germanium layer to form a heavily doped region; Using the mask layer on the top of the dummy gate structure as a mask, a metal silicide layer is formed on the surface of the substrate and the silicon germanium layer. 9. The method for forming a MOS transistor according to claim 8, wherein the mask layer is made of silicon nitride. 10. The forming method of MOS transistor as claimed in claim 8 or 9, is characterized in that, when carrying out ion implantation to the mask layer surface on described substrate and silicon germanium layer surface and dummy gate structure top, described The ion implanted is one of phosphorus ions, boron ions, boron difluoride ions, arsenic ions, germanium ions, argon ions, carbon ions, oxygen ions, nitrogen ions, fluorine ions, silicon ions, sulfur ions, and chloride ions. Or several, the direction of the ion implantation is perpendicular to the upper surface of the substrate and the upper surface of the silicon germanium layer. 11. The method for forming a MOS transistor according to claim 10, wherein when the ions to be implanted are oxygen ions, the implantation energy is 1 KeV-5000 KeV, and the implantation dose is 10 ¹⁰ /cm ² -10 ²³ /cm ² . 12. The formation method of MOS transistor as claimed in claim 11, is characterized in that, the method for removing described ion implantation layer is wet etching, and the solution of described wet etching is hydrofluoric acid solution, and described hydrogen The volume ratio of hydrofluoric acid to water in the hydrofluoric acid solution is 1:10-1:1000, and the wet etching time is 10s-1800s. 13. The forming method of MOS transistor as claimed in claim 8 or 9, is characterized in that, the method for removing the mask layer on the sidewall of dummy gate structure is wet etching, and the solution of described wet etching is Phosphoric acid solution, the temperature of the phosphoric acid solution is 110°C-180°C, and the wet etching time is 30s-600s. 14. The method for forming a MOS transistor according to claim 8, wherein the material of the metal silicide layer is one or a combination of _NiSi2 and NiSi.