CN103681382A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

The application discloses a semiconductor device and a manufacturing method thereof. An exemplary method may include: forming a gate and a source/drain region on a semiconductor substrate; epitaxially growing a sacrificial source/drain on the source/drain region; forming an interlayer dielectric layer on the semiconductor substrate, and performing planarization to expose the sacrificial source/drain; and removing at least a part of the sacrificial source/drain, and filling a hole formed by removing the at least part of the sacrificial source/drain.

Description

Semiconductor device and manufacturing method thereof

technical field

The present disclosure relates to the field of semiconductors, and more particularly, to a semiconductor device capable of improving contact formation and a method of manufacturing the same.

Background technique

After the semiconductor device is formed, it is necessary to form a contact portion for electrical connection with the outside. However, the conventional contact forming method has some problems.

Specifically, FIG. 1( a ) shows a cross-sectional view of an exemplary semiconductor device. As shown in FIG. 1( a ), the semiconductor device includes two unit devices formed in a semiconductor substrate 100 , which are isolated from each other by shallow trench isolation (STI) 101 , for example. Each unit device includes a gate 102 formed on a semiconductor substrate 100 (sidewalls 103 are formed on the sides of the gate 102 ) and source/drain regions 104 formed on both sides of the gate 102 in the semiconductor substrate 100 . Such semiconductor devices are well known in the art, and there are many methods to manufacture such semiconductor devices, which will not be repeated here.

In order to realize electrical connection with the outside, contacts to the gate 102 and the source/drain regions 104 need to be fabricated. For this reason, preferably, a silicide treatment is performed to form a metal silicide layer 105 on top of the gate 102 and the top of the source/drain region 104 . Then, as shown in FIG. 1(b), an interlayer dielectric layer 106 is deposited. In the interlayer dielectric layer 106, at the position corresponding to the gate 102 and the source/drain region 104, a contact hole is formed through an etching step, and the contact hole is filled with a conductive material (usually W, TiN, etc.) Contact portions 107-1 and 107-2 are formed.

However, the contact portion 107-2 on the gate 102 and the contact portion 107-1 on the source/drain region 104 have different heights, and thus the depths of the corresponding contact holes are different. Etching and filling of such different depth contact holes is difficult.

Therefore, there is a need for a novel semiconductor device and method of manufacturing the same in which the formation of contacts can be improved.

Contents of the invention

An object of the present disclosure is to provide a semiconductor device and a manufacturing method thereof.

According to one aspect of the present disclosure, there is provided a method of manufacturing a semiconductor device, comprising: forming a gate and a source/drain region on a semiconductor substrate; epitaxially growing a sacrificial source/drain on the source/drain region; forming an interlayer dielectric layer on the substrate, and planarizing it to expose the sacrificial source/drain; and removing at least a part of the sacrificial source/drain, and filling conductive Material.

According to another aspect of the present disclosure, there is provided a semiconductor device, comprising: a semiconductor substrate; a gate and a source/drain region formed on the semiconductor substrate; A contact plug consistent with the drain region, wherein the contact plug is flush with the top surface of the gate.

According to an embodiment of the present disclosure, by epitaxially growing the sacrificial source/drain aligned with the source/drain region, and finally replacing it with a contact plug, the height of the source/drain region can be “raised” to be the same as the height of the gate. In this way, the process in the subsequent formation of contacts to the gate and source/drain regions can be simplified. In addition, the coverage of the formed contact plug is basically the same as the coverage of the source/drain region, which can reduce the parasitic capacitance caused by the contact plug.

In addition, according to the embodiments of the present disclosure, materials with stress can be used for the interlayer dielectric layer, the conductive material used for the contact plug and/or the gate conductor material in the gate, so as to further improve device performance.

Description of drawings

The above and other objects, features and advantages of the present disclosure will be more clearly described through the following description of the embodiments of the present disclosure with reference to the accompanying drawings, in which:

FIG. 1 shows a schematic diagram of forming a contact portion of a semiconductor device according to the prior art;

FIG. 2 shows a schematic diagram of contact formation of a semiconductor device according to an embodiment of the present disclosure; and

3-6 show schematic diagrams of an improved example of forming a contact portion of a semiconductor device according to an embodiment of the present disclosure.

Detailed ways

Hereinafter, the present disclosure is described through specific embodiments shown in the accompanying drawings. It should be understood, however, that these descriptions are exemplary only, and are not intended to limit the scope of the present disclosure. Also, in the following description, descriptions of well-known structures and techniques are omitted to avoid unnecessarily obscuring the concept of the present disclosure.

Various structural views and cross-sectional views of semiconductor devices according to embodiments of the present disclosure are shown in the accompanying drawings. The figures are not drawn to scale, with certain details exaggerated and possibly omitted for clarity. The shapes of the various regions and layers shown in the figure, as well as their relative sizes and positional relationships are only exemplary, and may deviate due to manufacturing tolerances or technical limitations in practice, and those skilled in the art will Regions/layers with different shapes, sizes, and relative positions can be additionally designed as needed.

The basic idea of the present disclosure is to form a sacrificial source/drain by epitaxial growth on the active region of the semiconductor substrate (defining the source/drain region of the semiconductor device) on which the semiconductor device is formed. By sacrificing the source/drain, the height difference between the source/drain region and the gate is compensated. Subsequently, remove the sacrificial source/drain and replace it with a conductive material, preferably followed by planarization to form a contact plug, so that the height of the contact plug formed on the gate and the source/drain region is the same, which is beneficial to the subsequent contact part form. In addition, since the epitaxial growth is selectively performed on the semiconductor material (active area) (and not on the dielectric surrounding the active area, such as STI), the coverage of the formed contact plug is almost the same as that of the source/drain area. Therefore, the parasitic capacitance caused by contact plugging can be reduced.

Since unit devices in a semiconductor device are usually isolated from each other by a structure such as shallow trench isolation (STI), the sacrificial source/drain is self-aligned to the active region of the semiconductor device. This is because epitaxial growth is carried out on crystalline materials, and the active region is usually crystalline materials such as Si, etc. but isolation structures such as STI are usually not crystalline materials. In order to better define the sacrificial source/drain, an outer wall may be formed outside the gate spacer, which is separated from the gate spacer. For example, the outer sidewall may be located at the periphery of the corresponding unit device, such as at the end of the active region, so that the source/drain region of the unit device is basically located between the outer sidewall and the gate sidewall. In this way, during the epitaxial growth process, it can be ensured that the sacrificial source/drain is grown on the source/drain region of the device due to the limiting effect of the gate spacer and the outer wall.

FIG. 2 schematically shows the corresponding views of the structure obtained in each step of the semiconductor device manufacturing method according to the embodiment of the present disclosure.

As shown in FIG. 2(a), a semiconductor device was fabricated according to a conventional technique. The semiconductor device includes two unit devices formed in a semiconductor substrate 1000 , and the two unit devices are isolated from each other by shallow trench isolation (STI) 1001 , for example. Each unit device includes a gate 1002 formed on a semiconductor substrate 1000 (sidewalls 1003 are formed on the side of the gate 1002 ) and source/drain regions 1004 formed on both sides of the gate 1002 in the semiconductor substrate 1000 .

It should be noted here that, in this embodiment, the semiconductor device includes two unit devices. But the present disclosure is not limited thereto. For example, the present disclosure may be applied to a semiconductor device including more unit devices, or may be applied to a semiconductor device including only one unit device. In the present disclosure, in order to illustrate the application of the present disclosure in the field of complementary metal-oxide-semiconductor (CMOS), it is assumed that the two unit devices shown in FIG. 2( a ) are n-type devices and p-type devices respectively. For example, the unit device on the left in Figure 2(a) is an n-type device, and the unit device on the right in Figure 2(b) is a p-type device.

For convenience of description, it is assumed that the semiconductor device uses Si as the base material. For example, the semiconductor substrate 1000 includes bulk Si, the STI 1001 includes SiO ₂ , the gate 1002 includes a gate dielectric layer of SiO ₂ and a gate conductor layer of polysilicon, and the spacer 1003 includes nitride (such as Si ₃ N ₄ ). Of course, the present disclosure is not limited thereto. For example, the semiconductor substrate 1000 may include various other semiconductor materials such as Ge, SiGe, GaN, etc., and the gate 1002 may also include a high-K gate dielectric layer and a metal gate conductor layer.

Preferably, in order to protect the gate 1002 in the following processes, a protective cap 1005 is also formed on top of the gate 1002 . For example, the protective cap 1005 can be made of nitride like the sidewall 1003 .

The semiconductor device shown in FIG. 2( a ) is well known to those skilled in the art, and there are many ways to manufacture this semiconductor device, which will not be repeated here.

In this embodiment, in order to better define the sacrificial source/drain, an outer wall is preferably formed. Specifically, first, as shown in FIG. 2( b ), sacrificial spacers 1006 are formed on the sides of the gate spacers 1003 , and then outer sidewalls 1007 are formed on the sides of the sacrificial spacers 1006 . For example, the sacrificial sidewall 1006 may include oxide such as SiO _{2 ,} etc., and the outer sidewall 1007 may include nitride. It should be pointed out here that, for the convenience of the following processing, the material of the outer wall 1007 is selected to be the same as the material of the gate spacer 1003 (in this embodiment, it is nitride), but the material of the outer wall 1007 can also be selected. different from the material of the gate spacer 1003 . Next, as shown in FIG. 2( c ), the sacrificial spacer 1006 is removed, for example, by selective etching, so that the gate spacer 1003 and the outer sidewall 1007 separated from each other are left.

Figure 2(c') shows a top view of the structure shown in Figure 2(c). As shown in FIG. 2(c'), on the semiconductor substrate 1000, the active region (defining the source/drain region 1004) is surrounded by STI 1001. A gate spacer 1003 is formed on the side of the gate 1002 , and an outer sidewall 1007 is formed outside the gate spacer 1003 at a certain distance from the gate spacer 1003 . In this embodiment, the outer wall 1007 is located at the periphery of the unit device. Especially in the horizontal direction (gate length direction) in the figure, the outer wall 1007 may be located at the end of the active region. Therefore, the source/drain region 1004 is basically located between the gate spacer 1003 and the outer sidewall 1007 .

Next, as shown in FIG. 2( d ), a sacrificial source/drain 1008 is epitaxially grown on the structure shown in FIG. 2( c ). According to the top view of FIG. 2(c'), it can be seen that the active region (defining the source/drain region 1004) in the device is exposed, so the epitaxial growth is performed on the active region. While other areas are basically covered by STI 1001, so epitaxial growth does not occur. As a result, the grown sacrificial source/drain 1008 is self-aligned to the source/drain region 1004 and substantially completely overlaps the source/drain region 1004, as shown in the top view in FIG. 2(d'). The material of the sacrificial source/drain 1008 can be selected as a material that can effectively epitaxially grow on the semiconductor substrate 1000 . For example, when the semiconductor substrate 1000 is a Si substrate, the material of the sacrificial source/drain 1008 may also include Si, or may include other semiconductor materials such as SiGe, SiC and the like.

Then, as shown in Figures 2(e) and 2(e'), an interlayer dielectric (ILD) layer 1009 may be deposited. The ILD layer 1009 may include dielectric materials such as SiO ₂ and SiOC, for example. Next, a planarization process such as chemical mechanical polishing (CMP) may be performed to flatten the surface of the entire device and expose the sacrificial source/drain 1008 . In this way, the sacrificial source/drain 1008 can be subsequently replaced.

It can be seen from FIGS. 2( e ) and 2 ( e ′) that the protective cap 1005 used for protection is also removed through this planarization process, exposing the gate 1002 . Here, a replacement gate process may preferably be applied. Specifically, for example, the previously formed gate 1002 includes a gate dielectric layer of SiO ₂ and a gate conductor layer of polysilicon. After the planarization step shown in Figure 2(e), the gate dielectric layer of _SiO2 and the gate conductor layer of polysilicon are removed, and a high-K gate dielectric layer and a metal gate electrode layer are deposited in sequence, and then patterned to form the final gate stack. Preferably, a work function adjustment layer may also be formed between the high-K gate dielectric layer and the metal gate electrode layer. This replacement gate process itself is well known in the art and will not be described in detail here.

Next, as shown in FIGS. 2(f) and 2(f'), the sacrificial source/drain 1008 is removed by selective etching, for example, by HF solution. In FIGS. 2(f) and 2(f'), the sacrificial source/drain 1008 is completely removed, thereby exposing the source/drain region 1004 underneath. However, the present disclosure is not limited thereto. For example, only a part of the sacrificial source/drain 1008 may be removed, leaving a certain thickness of the sacrificial source/drain. The thickness can be determined according to device performance optimization. Specifically, the remaining sacrificial source/drain can help to form a thicker metal silicide in the silicidation process as described later, thereby reducing the contact resistance. Alternatively, a deep etch into the source/drain regions 1004 may be performed.

Then, as shown in Figures 2(g) and 2(g'), in the hole obtained due to the selective etching of the sacrificial source/drain 1008, a conductive material such as metal etc. is filled to form the source/drain region 1004 is electrically connected to contact plug 1010 . This filling can be done, for example, by first depositing a layer of conductive material followed by planarization.

Since the contact plug 1010 is realized by filling the hole left by removing the sacrificial source/drain region that is self-aligned to the source/drain region and substantially completely overlapped with the source/drain region, the contact plug 1010 is also self-aligned. It is aligned with the source/drain region, and the coverage area is basically consistent with the source/drain region. In particular, in the gate width direction (vertical direction in the figure), the size of the contact plug can be consistent with the size of the source/drain region; and in the gate length direction (horizontal direction in the figure), the size of the contact plug can be less than or equal to Dimensions of source/drain regions. In addition, the size of the contact plug can also be adjusted through the outer wall 1007 .

Preferably, in order to improve the electrical performance, metal silicide treatment may be performed before filling the conductive material, so as to form a metal silicide (not shown in the figure) at the bottom of the hole formed by removing the sacrificial source/drain 1008 . Specifically, for example, a metal film such as a Ni film can be deposited, and then annealed, so that the metal film and the Si element in the source/drain region 1004 (or, in the case of still leaving a part of the sacrificial source/drain 1008, A silicide reaction occurs with the Si element in the sacrificial source/drain 1008 to form a metal silicide. After that, the unreacted metal film is removed.

From Figure 2(g), it can be seen that the surface of the device now remains flat. Specifically, the heights of the gate 1002 and the contact plug 1010 of the source/drain region (in addition, the sidewalls 1003, 1007 and the interlayer dielectric layer 1009) are the same. In this way, in a subsequent process, contact portions of the gate electrode 1002 and the source/drain regions 1004 with the outside can be easily formed. For example, another dielectric layer may be deposited on the structure described in FIG. Contact holes are filled to form contacts. Since the current gate 1002 and the source/drain region 1004 (the height of which is raised by the contact plug 1010 ) are at the same height, only a contact hole of the same depth needs to be etched in the other dielectric layer, which greatly simplifies the process.

Preferably, in the steps shown in Figures 2(e) and 2(e') above, instead of simply forming an ILD layer such as SiO ₂ , a stressed dielectric layer such as Si ₃ N ₄ , to further improve device performance.

In Figures 3(a) and 3(a'), such an example is shown. Wherein, for the n-type device on the left, a dielectric layer 1009-1 with tensile stress can be formed; and for the p-type device on the right, a dielectric layer 1009-2 with compressive stress can be formed. For example, this can be done as follows. First, a layer of photoresist is covered on the right p-type device region, and a dielectric layer 1009-1 with tensile stress is deposited on the left n-type device region; then the right p-type device region is removed photoresist, and form a photoresist on the left n-type device region, and deposit a dielectric layer 1009-2 with compressive stress on the right p-type device region; finally planarize to expose the sacrificial source/ Leak 1008.

According to an embodiment of the present disclosure, the dielectric material with tensile stress may include metal oxides with tensile stress such as Al ₂ O ₃ , ZrO ₂ , CrO ₂ . According to another embodiment of the present disclosure, instead of directly depositing the dielectric layer, metals such as Al, Cr, and Zr etc. are firstly deposited and then oxidized to form the oxide dielectric layer with tensile stress.

According to an embodiment of the present disclosure, the dielectric material with compressive stress may include metal oxides with compressive stress such as Ta ₂ O ₅ , ZrO ₂ . According to another embodiment of the present disclosure, instead of depositing the dielectric layer directly, metals such as Ta and Zr etc. are first deposited and then oxidized to form a compressively stressed oxide dielectric layer.

Preferably, the outer wall 1007 can be removed after the sacrificial source/drain growth step shown in FIGS. 2( d ) and 2 ( d ′). In addition, the gate spacer 1003 can also be removed. Of course, in the case of removing the gate spacer 1003 , in order to protect the gate 1002 , a thin wall of the sidewall 1003 may be left on the side of the gate 1002 . After the spacer is removed, the ILD layer 1009 is formed.

In Figures 4(a) and 4(a'), such an example is shown. Wherein, both the gate sidewall 1003 and the outer sidewall 1007 are removed, so their corresponding positions are filled with the material of the ILD layer. For the convenience of illustration, the thin walls of the side walls 1003 remaining on the side of the gate 1002 are not shown in FIG. 4 . In the example shown in FIG. 4 , an ILD layer 1009 - 1 with tensile stress and an ILD layer 1009 - 2 with compressive stress are also formed for n-type devices and p-type devices, respectively.

It should be pointed out here that although FIG. 4 shows an example in which the removal of the sidewall and the formation of the stressed ILD layer are used in combination, the present disclosure is not limited thereto. These two measures can be used independently.

Preferably, in the steps shown in Figures 2(g) and 2(g') above, conductive materials such as metals are not simply filled, but conductive materials with stress are formed to further improve device performance .

In Figures 5(a) and 5(a'), such an example is shown. Wherein, for the n-type device on the left, a contact plug 1010-1 with tensile stress can be formed; and for the p-type device on the right, a contact plug 1010-2 with compressive stress can be formed. For example, conductive materials capable of providing tensile stress include metals such as Al, Cr, and Zr, and conductive materials capable of providing compressive stress include metals such as Ta and Zr. In the example shown in FIG. 5 , the spacer is also removed, and a tensile-stressed ILD layer 1009 - 1 and a compressive-stressed ILD layer 1009 - 2 are formed for the n-type device and the p-type device, respectively.

It should be noted here that although FIG. 5 shows an example in which the three measures of removing the spacer, forming the stressed ILD layer and forming the stressed contact plug are used in combination, the present disclosure is not limited thereto. These three measures can be used individually.

Preferably, after the contact plugs are formed as shown in FIGS. 2(g) and 2(g'), replacement gate processing may be performed. For example, the previously formed gate 1002 (for example, a gate dielectric layer comprising SiO ₂ and a polysilicon gate conductor layer, the structure of the gate 1002 is not clearly shown in the figure) is removed, and a high-K gate dielectric layer (such as , HfO ₂ , HfSiON _x, etc.) and metal gate conductor layer. More preferably, a work function adjusting layer is formed between the high-K gate dielectric layer and the metal gate conductor layer. They are then patterned to form the final gate stack.

Here, preferably, the gate conductor layer may include a stressed conductive material. Specifically, for n-type devices, the gate conductor layer can apply tensile stress, such as TiAlN, W material; and for p-type devices, the gate conductor layer can apply compressive stress, such as TiN material.

In Figures 6(a) and 6(a'), such an example is shown. Wherein, for the n-type device on the left, a gate 1002-1 with tensile stress can be formed (specifically, a gate conductor layer with tensile stress); and for the p-type device on the right, a gate conductor layer with compressive stress can be formed Gate 1002-2 (specifically, forming a gate conductor layer with compressive stress). In the example shown in FIG. 6 , the sidewall is also removed, and the ILD layer 1009-1 with tensile stress and the ILD layer 1009-2 with compressive stress are respectively formed for n-type devices and p-type devices, and for n-type devices The device and the p-type device respectively form a contact plug with tensile stress 1010-1 and a contact plug with compressive stress 1010-2.

It should be pointed out here that although FIG. 6 shows an example in which the four measures of removing the spacer, forming a stressed ILD layer, forming a stressed contact plug, and forming a stressed gate are used in combination, the present disclosure is not limited thereto. . These four measures can be used individually.

In the above description, technical details such as patterning and etching of each layer are not described in detail. However, those skilled in the art should understand that various means in the prior art can be used to form layers, regions, etc. of desired shapes. In addition, in order to form the same structure, those skilled in the art can also design a method that is not exactly the same as the method described above. Although the various embodiments have been described separately above, it does not mean that the advantageous features of these embodiments cannot be used in combination.

The present disclosure has been described above with reference to the embodiments of the present disclosure. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the present disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of the present disclosure, and these substitutions and modifications should all fall within the scope of the present disclosure.

Claims (13)

1. a method of manufacturing semiconductor device, comprising:

In Semiconductor substrate, form grid and source/drain region;

On described source/drain region, source/leakage is sacrificed in epitaxial growth;

In Semiconductor substrate, form interlevel dielectric layer, and it is carried out to planarization, to expose sacrifice source/leakage; And

Remove at least a portion and sacrifice source/leakage, and filled conductive material in the hole forming removing described at least a portion sacrifice source/leakage.

2. method according to claim 1, wherein, be formed with grid curb wall, and the method further comprises on the side of described grid:

Outside at described grid curb wall separates with grid curb wall and forms external wall, and wherein said grid curb wall and described external wall limit epitaxially grown scope.

3. method according to claim 2, wherein, forms external wall as follows:

On the side of grid curb wall, form and sacrifice side wall;

On the side of sacrificing side wall, form external wall; And

Remove and sacrifice side wall.

4. method according to claim 1, wherein, after removing sacrifice source/leakage and before filled conductive material, the method further comprises:

Carry out silicidation, with the bottom in described hole, form metal silicide.

5. method according to claim 1, wherein, described interlevel dielectric layer stress application,

Wherein, for N-shaped device, described stress is tension stress; For p-type device, described stress is compression.

6. method according to claim 5, wherein, the interlevel dielectric layer that applies tension stress comprises Al ₂o ₃, ZrO ₂and CrO ₂one of;

The interlevel dielectric layer that applies compression comprises TaO ₂and ZrO ₂one of.

7. method according to claim 1, wherein, after source/leakages sacrificed in epitaxial growth and before formation interlevel dielectric layer, the method further comprises:

Remove external wall and grid curb wall away from a part for gate side.

8. method according to claim 1, wherein, the electric conducting material stress application of filling,

Wherein, for N-shaped device, described stress is tension stress; For p-type device, described stress is compression.

9. method according to claim 8, wherein,

The electric conducting material that applies tension stress comprises one of Al, Zr and Cr;

The electric conducting material that applies compression comprises one of Ta and Zr.

10. method according to claim 1, wherein, after described planarisation step, the method further comprises:

Remove grid;

In the position of described grid, form new grid stacking, stacking gate dielectric layer and the grid conductor layer of comprising of described grid.

11. methods according to claim 10, wherein, described grid conductor layer stress application,

Wherein, for N-shaped device, described stress is tension stress; For p-type device, described stress is compression.

12. 1 kinds of semiconductor device, comprising:

Semiconductor substrate;

The grid forming in Semiconductor substrate and source/drain region;

In alignment with source/drain region and the coverage contact embolism consistent with source/drain region substantially,

Wherein, the end face of described contact embolism and grid maintains an equal level.

13. semiconductor device according to claim 12, wherein, in grid width direction, the size of contact embolism is consistent with source/drain region; And on grid length direction, the size of contact embolism is less than or equal to source/drain region.

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