CN103698689B - The ageing method and ageing device of integrated circuit - Google Patents
The ageing method and ageing device of integrated circuit Download PDFInfo
- Publication number
- CN103698689B CN103698689B CN201310728263.XA CN201310728263A CN103698689B CN 103698689 B CN103698689 B CN 103698689B CN 201310728263 A CN201310728263 A CN 201310728263A CN 103698689 B CN103698689 B CN 103698689B
- Authority
- CN
- China
- Prior art keywords
- burn
- signal
- integrated circuit
- aging
- interface
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
The present invention provides a kind of ageing method and ageing device of integrated circuit.Wherein, the described method includes：Ageing desired signal is received by combined testing action group jtag interface；According to the ageing desired signal, the ageing signal needed for ageing is carried out using the ageing unit in default signal generation rule generation integrated circuit；By the ageing unit in the ageing signal transmission to the integrated circuit, so that the ageing unit according to the ageing signal, performs the ageing process of the integrated circuit.The embodiment of the present invention has been multiplexed the jtag interface of I/O port tests, and without redesigning ageing scheme, the simpler convenience of connection of ageing test interface simplifies the process of integrated circuit ageing test, while also reduces ageing cost.
Description
Technical Field
The present invention relates to integrated circuit aging technologies, and in particular, to an integrated circuit aging method and an integrated circuit aging apparatus.
Background
The development of information technology has made integrated circuits become core components in the field of information technology, and the reliability of integrated circuits has been a key to restrict the reliability of software and hardware in industries such as information technology. The complexity, precision, etc. of the integrated circuit manufacturing process can cause the integrated circuit to be defective during the manufacturing process. For some chips with strict reliability requirements, in order to avoid the problem of early failure of the circuit, burn-in tests must be performed before the integrated circuit chip is shipped. The aging test technology is to apply certain stress to components within a certain time, such as current, voltage, temperature and the like, and is usually higher than the use stress of the components in normal work, so that defective products are removed, and the quality of the products leaving a factory is ensured.
At present, a sensitization path method can be selected for aging a common combinational logic circuit, and a state transition check method can be adopted for aging a single sequential logic circuit. However, for modern very large Scale integrated circuits (VLSI), such as SOC and multi-core microprocessors, which have large scales and complex functional modules, a sensitization path method and a state transition inspection method cannot be used for aging. In order to burn in a large scale integrated circuit to achieve burn-in, a testability design must be used in the integrated circuit design stage. In the testability design stage, the strategy of integrated circuit burn-in test is considered, and corresponding interfaces and/or circuits for burn-in test are designed and added in the integrated circuit so as to be used in the subsequent burn-in test.
In the prior art, the aging test strategy is considered in the integrated circuit design stage, and the corresponding aging test interface and/or circuit is added in the integrated circuit design, so that the design difficulty of the integrated circuit is increased, the design cost is improved, the whole aging test process comprises the integrated circuit design process and the subsequent test process, and the aging process is complex and high in cost.
Disclosure of Invention
The invention provides a burn-in method and a burn-in device of an integrated circuit, which are used for carrying out burn-in test by utilizing a JTAG interface and simplifying the burn-in method.
A first aspect of the invention provides a method of aging an integrated circuit, comprising:
receiving a burn-in demand signal through a Joint Test Action Group (JTAG) interface;
generating a burn-in signal required by a burn-in unit in the integrated circuit for burn-in by adopting a preset signal generation rule according to the burn-in demand signal;
and transmitting the burn-in signal to a burn-in unit in the integrated circuit, so that the burn-in unit executes the burn-in process of the integrated circuit according to the burn-in signal.
Another aspect of the present invention provides an aging apparatus, comprising:
the receiving module is used for receiving the aging demand signal through the JTAG interface;
the generating module is used for generating a burn-in signal required by a burn-in unit in the integrated circuit for burn-in by adopting a preset signal generating rule according to the burn-in demand signal;
and the transmission module is used for transmitting the burn-in signal to a burn-in unit in the integrated circuit so that the burn-in unit executes the burn-in process of the integrated circuit according to the burn-in signal.
According to the technical scheme, the embodiment of the invention utilizes the JTAG interface to receive the burn-in demand signal required by the burn-in of the integrated circuit, and generates the burn-in signal according to the obtained burn-in demand signal, so that the burn-in unit in the integrated circuit conducts the burn-in according to the burn-in signal. The embodiment of the invention reuses the JTAG interface for the I/O port test, does not need to redesign the burn-in scheme, has simpler and more convenient connection of the burn-in test interface, simplifies the burn-in test process of the integrated circuit, and simultaneously reduces the burn-in cost.
Drawings
FIG. 1 is a flowchart illustrating a method for aging an integrated circuit according to an embodiment of the present invention;
FIG. 2 is a schematic structural diagram of a burn-in apparatus according to a second embodiment of the present invention;
FIG. 3 is a schematic diagram of a method for aging an integrated circuit according to a third embodiment of the present invention
FIG. 4 is a schematic diagram of the TAP controller output state control signal provided by the present invention;
FIG. 5 is a schematic diagram showing the potentials of state control signals output by the TAP controller according to the received clock signal and mode selection signal;
fig. 6 is a schematic diagram of potentials of a first burn-in enable signal and a first burn-in clock output by the burn-in controller according to the clock signal and the state control signal provided by the present invention;
FIG. 7 is a schematic diagram of a method for aging an integrated circuit according to a fourth embodiment of the present invention;
FIG. 8 is a schematic diagram showing the potentials of a second burn-in enable signal and a second burn-in signal output by the burn-in controller according to the clock signal, and a schematic diagram showing the potentials of an MBIST self-reset signal output according to the output signal of the MBIST output terminal;
fig. 9 is a schematic diagram of a method for aging an integrated circuit according to a fifth embodiment of the present invention.
Detailed Description
The integrated circuits mentioned in the embodiments of the present invention are all integrated circuits supporting IEEE1149.1 standard protocol, and have Joint Test Action Group (JTAG) interfaces conforming to IEEE1149.1 standard protocol. The prior art only uses the pins and the ports included in the JTAG interface to perform control test on the I/O ports of the integrated circuit and the internal logic of the I/O ports, but cannot be used for burn-in test on the internal logic and the memory cells of the integrated circuit. The JTAG interface includes 5 Test Access Port (TAP) pins, and the 5 TAP pins are respectively connected to: the Test system comprises a Test Clock (TCK) interface, a Test Data Input (TDI) interface, a Test Data Output (TDO) interface, a Test mode Select signal (TMS) interface and a Test Reset Signal (TRST) interface. The invention aims to burn in the logic unit and/or the memory unit in the integrated circuit by utilizing the existing JTAG interface in the integrated circuit so as to reduce the interface and/or circuit which needs additional design because of the burn-in of the integrated circuit, simplify the burn-in process and reduce the burn-in cost.
As shown in fig. 1, a flowchart of a method for aging an integrated circuit according to an embodiment of the present invention is shown. As shown in fig. 1, an execution subject of the method according to the first embodiment may be a burn-in apparatus, and specifically, the method for burn-in of an integrated circuit includes:
step 101, receiving a burn-in demand signal through a JTAG interface.
In particular, in practical applications, the integrated circuit may be a complex integrated circuit, such as a CPU, that includes only combinational logic and sequential circuits, or only memory cells, or that includes both combinational logic and sequential circuits as well as memory cells.
For integrated circuits of different functional classes, the burn-in demand signal received via the JTAG interface is different, for example as follows:
1) when the burn-in unit is a burn-in chain formed by serially connecting registers of logic function units in the integrated circuit, the burn-in demand signal comprises: a clock signal, a mode select signal, and burn-in data. Wherein the burn-in unit may be a burn-in chain formed by a plurality of registers inserted into a scan chain. Correspondingly, in step 101, the receiving of the burn-in demand signal through the JTAG interface may be implemented by the following method, including:
and step S111, receiving the clock signal through a test clock TCK interface in the JTAG interface.
And step S112, receiving the mode selection signal through a test mode selection signal TMS interface in the JTAG interface.
And step S113, receiving the aging data through a test input data TDI interface in the JTAG interface.
Here, it should be noted that: by adopting the technical scheme provided by the embodiment to burn in the integrated circuit, the registers in the logic function units are inserted into the scan chains to form a scan chain formed by serially connecting the registers, and the scan chain is a burn-in chain. However, since existing burn-in chains are not designed inside the existing integrated circuit, when there is no existing burn-in chain in the integrated circuit, the following steps need to be added before step S111: the registers of the logic function units in the integrated circuit are connected in series to form a scan chain, and the scan chain is a burn-in chain.
2) When the burn-in unit is a memory built-in self test unit MBIST for performing memory self test on an built-in memory unit in the integrated circuit, the burn-in demand signal comprises: clock signal, mode selection signal and output signal of MBIST output terminal. Correspondingly, in step 101, the receiving of the burn-in demand signal through the JTAG interface may be implemented by the following method, including:
and step S121, receiving the clock signal through a TCK interface in the JTAG interface.
And step S122, receiving the mode selection signal through a TMS interface in the JTAG interface.
Step S123, acquiring an output signal of the MBIST output end at a signal receiving side of a test output data TDO interface in the JTAG interface.
What needs to be added here is: a Memory Built-in Self Test (MBIST) is a Self Test unit for providing a Self Test function by implanting a related function circuit into a circuit when an integrated circuit is designed. The MBIST includes test circuitry for loading, reading and comparing test patterns. In the aging process, the memory cell of the integrated circuit enters an operation state of operating the MBIST, and the memory cell of the integrated circuit is subjected to cyclic read-write operation through the MBIST so as to realize aging of the memory cell. It should be noted that: off-the-shelf MBISTs are not designed inside all integrated circuits. Therefore, when there is no existing MBIST in the integrated circuit, the built-in memory cells (e.g., RAM, ROM) in the integrated circuit are inserted into the memory cell self-test logic to form the MBIST.
3) When the aging unit comprises: when registers in logic function units of the integrated circuit are connected in series to form a burn-in chain and a memory built-in self test unit (MBIST) in the integrated circuit, the burn-in demand signal comprises: clock signal, mode selection signal, aging data and output signal of MBIST output terminal. Correspondingly, in step 101, the receiving of the burn-in demand signal through the JTAG interface may be implemented by the following method, including:
and S131, receiving the clock signal through a TCK interface in the JTAG interface.
And step S132, receiving the mode selection signal through a TMS interface in the JTAG interface.
And step S133, receiving the aging data through a TDI interface in the JTAG interface.
And step S134, acquiring an output signal of the output end of the MBIST at the signal receiving side of the TDO interface in the JTAG interface.
And 102, generating a burn-in signal required by a burn-in unit in the integrated circuit for burn-in by adopting a preset signal generation rule according to the burn-in demand signal.
Likewise, for different functional classes of integrated circuits, the burn-in signal generated is different because the burn-in demand signal received is different. Examples are as follows:
1) when the burn-in unit is a burn-in chain formed by serially connecting registers in a logic function unit of the integrated circuit, the burn-in signal comprises: a first burn-in enable signal, a first burn-in clock signal, a burn-in control signal, and the burn-in data. Correspondingly, in step 102, according to the burn-in demand signal, the burn-in signal required by the burn-in unit in the integrated circuit to burn in is generated by using the preset signal generation rule, and the method includes:
and step S211, generating a burn-in mode signal and a state control signal according to the clock signal and the mode selection signal.
Wherein the state control signal comprises: a scan control signal and a pause control signal. Specifically, when the clock signal is at an active level, a burn-in mode signal which is continuously at the active level is generated; generating a scan control signal of which the level is an effective level when the mode selection signal is a first selection timing signal; and generating a pause control signal with the level being the effective level when the mode selection signal is the second selection timing signal.
Step S212, generating a burn-in control signal, a first burn-in enable signal and a first burn-in clock signal according to the clock signal, the burn-in mode signal and the state control signal.
Specifically, the clock signal in the continuous clock in which the scan control signal is at an active level and the clock signal in the continuous clock in which the pause control signal is at an active level are used as the first burn-in clock signal;
when the scanning control signal is at an effective level, generating that the first burn-in enabling signal with the effective level is effective;
and when the burn-in mode signal is at an effective level, the burn-in control signal with the level being at the effective level is generated to be effective.
And step S213, when the aging control signal is an effective signal, acquiring the aging data in the aging demand signal.
2) When the burn-in unit is an MBIST in the integrated circuit, the burn-in signal comprises: a second burn-in enable signal, a second burn-in clock signal, and an MBIST self reset signal. Correspondingly, in step 102, according to the burn-in demand signal, the burn-in signal required by the burn-in unit in the integrated circuit to burn in is generated by using the preset signal generation rule, and the method includes:
and step 221, generating a burn-in mode signal and a driving indication signal according to the clock signal and the mode selection signal.
Specifically, when the clock signal is at an active level, a burn-in mode signal which is continuously at the active level is generated;
and when the mode selection signal is the first selection timing signal, generating a driving indication signal with the active level.
Step 222, generating a second burn-in enable signal and the second burn-in clock signal according to the clock signal, the burn-in mode signal and the driving indication signal.
Specifically, when the driving indication signal is at an active level, the second burn-in enable signal whose level is the active level is generated to be active;
and taking the clock signal in the continuous clock with the driving indication signal being at the effective level as the second aging clock signal.
And 223, generating the MBIST self-reset signal according to the output signal of the MBIST output end.
Specifically, when the output signal of the MBIST output terminal is at an effective level, delaying for a preset time after the start time when the output signal of the MBIST output terminal is at the effective level, and generating the MBIST self-reset signal.
3) When the aging unit comprises: when registers in logic functional units of the integrated circuit are connected in series to form a burn-in chain, and when the MBIST in the integrated circuit exists, the burn-in signal comprises: a first aging signal and a second aging signal, wherein the first aging signal comprises: first burn-in enable signal, first burn-in clock signal, burn-in control signal and burn-in data, the second burn-in signal includes: a second burn-in enable signal, a second burn-in clock signal, and an MBIST self reset signal. Correspondingly, in step 102, according to the burn-in demand signal, the burn-in signal required by the burn-in unit in the integrated circuit to burn in is generated by using the preset signal generation rule, and the method includes:
and 231, generating a burn-in mode signal, a state control signal and a driving indication signal according to the clock signal and the mode selection signal.
Specifically, when the clock signal is at an active level, a burn-in mode signal which is continuously at the active level is generated;
generating a scan control signal of which the level is an effective level when the mode selection signal is a first selection timing signal; generating a pause control signal of which the level is an effective level when the mode selection signal is a second selection timing signal;
and when the mode selection signal is the first selection timing signal, generating a driving indication signal with the active level.
Step 232, generating a burn-in control signal, a first burn-in enable signal and a first burn-in clock signal according to the clock signal, the burn-in mode signal and the state control signal.
Specifically, the clock signal in the continuous clock in which the scan control signal is at an active level and the clock signal in the continuous clock in which the pause control signal is at an active level are used as the first burn-in clock signal;
when the scanning control signal is at an effective level, generating that the first burn-in enabling signal with the effective level is effective;
and when the burn-in mode signal is at an effective level, the burn-in control signal with the level being at the effective level is generated to be effective.
And 233, acquiring the aging data in the aging demand signal when the aging control signal is an effective signal.
And 234, generating a second burn-in enable signal and a second burn-in clock signal according to the clock signal, the burn-in mode signal and the driving indication signal.
Specifically, when the driving indication signal is at an active level, the second burn-in enable signal whose level is the active level is generated to be active;
and taking the clock signal in the continuous clock with the driving indication signal being at the effective level as the second aging clock signal.
And 235, generating the MBIST self-reset signal according to the output signal of the MBIST output end.
Specifically, when the output signal of the MBIST output terminal is at an effective level, delaying for a preset time after the start time when the output signal of the MBIST output terminal is at the effective level, and generating the MBIST self-reset signal.
And 103, transmitting the burn-in signal to a burn-in unit in the integrated circuit, so that the burn-in unit executes a burn-in process according to the burn-in signal.
The aging unit executes an aging process according to the aging signal, which can be realized by the following examples but is not limited to the following examples:
1) and when the burn-in unit is a burn-in chain formed by serially connecting registers of logic function units in the integrated circuit, the burn-in chain conducts burn-in on the logic function units of the integrated circuit according to the first burn-in enabling signal, the first burn-in clock signal and the burn-in data.
2) And when the burn-in unit is an MBIST in the integrated circuit, the MBIST conducts burn-in on an embedded storage unit of the integrated circuit according to the second burn-in enabling signal, the MBIST self-reset signal and the second burn-in clock signal.
3) When the burn-in unit comprises a burn-in chain and an MBIST, transmitting the first burn-in signal to the burn-in chain so that the burn-in chain can burn in the logic function unit of the integrated circuit according to the first burn-in signal; wherein the first aging signal comprises: a first burn-in enable signal, a first burn-in clock signal, a burn-in control signal, and the burn-in data. Simultaneously, transmit the second burn-in signal to the MBIST to cause the MBIST to burn-in the embedded memory cell of the integrated circuit according to the second burn-in signal, wherein the second burn-in signal includes: the second burn-in enable signal, the MBIST self-reset signal, and the second burn-in clock signal.
In this embodiment, a JTAG interface is used to receive a burn-in demand signal required for burn-in of an integrated circuit, and a burn-in signal is generated according to the obtained burn-in demand signal, so that a burn-in unit in the integrated circuit conducts burn-in according to the burn-in signal. The embodiment reuses the JTAG interface for the I/O port test, does not need to redesign a burn-in scheme, is simpler and more convenient to connect the burn-in test interface, simplifies the burn-in test process of the integrated circuit, and simultaneously reduces the burn-in cost.
Further, after step 103 of the method according to the first embodiment, the method further includes: and outputting a burn-in result through a TDO interface of the JTAG interface. Specifically, when the burn-in unit is a burn-in chain, a logic function unit burn-in result is output through the TDO interface of the JTAG interface. And when the burn-in unit is an MBIST, outputting a burn-in result of the embedded storage unit through a TDO interface of the JTAG interface. When the burn-in unit comprises a burn-in chain and an MBIST, the TDO interface of the JTAG interface needs to output two burn-in results, and the following method can be adopted to output the burn-in results:
generating a burn-in result output control signal according to a preset output strategy; when the output control signal is a first control signal, outputting a logic function unit aging result through a TDO interface in the JTAG interface; and when the output control signal is a second control signal, outputting an aging result of the embedded memory cell through a TDO interface in the JTAG interface.
As shown in fig. 2, a schematic structural diagram of a aging device according to a second embodiment of the present invention is provided. As shown in fig. 2, the aging apparatus according to the second embodiment includes: the device comprises a receiving module 1, a generating module 2 and a transmitting module 3. The receiving module 1 is configured to receive a burn-in demand signal through a JTAG interface. And the generating module 2 is used for generating a burn-in signal according to the burn-in demand signal. The transmission module 3 is configured to transmit the burn-in signal to a burn-in unit in the integrated circuit, so that the burn-in unit executes a burn-in process of the integrated circuit according to the burn-in signal.
In this embodiment, a JTAG interface is used to receive a burn-in demand signal required for burn-in of an integrated circuit, and a burn-in signal is generated according to the obtained burn-in demand signal, so that a burn-in unit in the integrated circuit conducts burn-in according to the burn-in signal. The embodiment reuses the JTAG interface for the I/O port test, does not need to redesign a burn-in scheme, is simpler and more convenient to connect the burn-in test interface, simplifies the burn-in test process of the integrated circuit, and simultaneously reduces the burn-in cost.
In practical applications, the integrated circuit is divided into: integrated circuits that include only combinational logic circuits and sequential circuits, integrated circuits that include only memory cells, and integrated circuits that include both combinational logic circuits and sequential circuits as well as memory cells. The specific implementation of the modules in the burn-in apparatus described in the second embodiment above may therefore be different for the burn-in of different integrated circuits. If the integrated circuit only comprises a combinational logic circuit and a sequential circuit, the burn-in unit is a burn-in chain formed by serially connecting registers in a logic function unit; if the integrated circuit only comprises an embedded storage unit, the burn-in unit is a storage built-in self test unit (MBIST) in the integrated circuit; if the integrated circuit comprises a combinational logic circuit, a sequential circuit and an embedded storage unit, the burn-in unit is a burn-in chain formed by serially connecting registers in a logic function unit in the integrated circuit and an MBIST in the integrated circuit. Specifically, the following contents are as follows:
when the burn-in unit is a burn-in chain formed by serially connecting registers in a logic function unit of the integrated circuit, the burn-in demand signal comprises: a clock signal, a mode select signal, and burn-in data. Correspondingly, the receiving module in the second embodiment is specifically configured to receive the clock signal through a TCK interface in the JTAG interface; receiving the mode selection signal through a TMS interface in the JTAG interface; and receiving the aging data through a TDI interface in the JTAG interface. The aging signal comprises: a first burn-in enable signal, a first burn-in clock signal, a burn-in control signal, and the burn-in data. Accordingly, the generating module can be implemented by adopting the following structure. Specifically, the generating module includes: a TAP controller, a burn-in controller, and a mode selector. The TAP controller is used for generating a burn-in mode signal and a state control signal according to the clock signal and the mode selection signal. Specifically, the TAP controller is configured to generate a burn-in mode signal that continues to be at an active level when the clock signal is at an active level; generating a scan control signal of which the level is an effective level when the mode selection signal is a first selection timing signal; and generating a pause control signal with the level being the effective level when the mode selection signal is the second selection timing signal. The burn-in controller is used for generating a burn-in control signal, a first burn-in enable signal and a first burn-in clock signal according to the clock signal, the burn-in mode signal and the state control signal. Specifically, the burn-in controller is configured to use the clock signal in the continuous clock in which the scan control signal is at an active level and the clock signal in the continuous clock in which the pause control signal is at an active level as the first burn-in clock signal; when the scanning control signal is at an effective level, generating that the first burn-in enabling signal with the effective level is effective; and when the burn-in mode signal is at an effective level, the burn-in control signal with the level being at the effective level is generated to be effective. And the mode selector is used for acquiring the aging data in the aging demand signal when the aging control signal is an effective signal.
When the burn-in unit is an MBIST for performing storage self-test on an embedded storage unit in the integrated circuit, the burn-in demand signal comprises: clock signal, mode selection signal and output signal of MBIST output terminal. Correspondingly, the receiving module in the second embodiment is specifically configured to receive the clock signal through a TCK interface in the JTAG interface; receiving the mode selection signal through a TMS interface in the JTAG interface; and acquiring an output signal of the output end of the MBIST at the signal receiving side of the TDO interface in the JTAG interface. The aging signal comprises: a second burn-in enable signal, a second burn-in clock signal, and an MBIST self reset signal. Accordingly, the generating module can be implemented by adopting the following structure, specifically, the generating module includes: a TAP controller and a burn-in controller. The TAP controller is used for generating a burn-in mode signal and a driving indication signal according to the clock signal and the mode selection signal. Specifically, the TAP controller is configured to generate a burn-in mode signal that continues to be at an active level when the clock signal is at an active level; and when the mode selection signal is the first selection timing signal, generating a driving indication signal with the active level. The burn-in controller is used for generating a second burn-in enable signal and a second burn-in clock signal according to the clock signal, the burn-in mode signal and the driving indication signal; and generating the MBIST self-reset signal according to the output signal of the MBIST output end. Specifically, the burn-in controller is configured to generate the second burn-in enable signal with an active level to be active when the driving indication signal is at the active level; taking the clock signal in the continuous clock with the driving indication signal being at the active level as the second aging clock signal; and when the output signal of the MBIST output end is at an effective level, delaying for a preset time after the initial moment when the output signal of the MBIST output end is at the effective level, and generating the MBIST self-reset signal.
When the aging unit comprises: the register of the logic function unit in the integrated circuit is connected in series to form a burn-in chain, and when the MBIST in the integrated circuit, the burn-in demand signal comprises: clock signal, mode selection signal, aging data and output signal of MBIST output terminal. Correspondingly, the receiving module in the second embodiment is specifically configured to receive the clock signal through a TCK interface in the JTAG interface; receiving the mode selection signal through a TMS interface in the JTAG interface; receiving the aging data through a TDI interface in the JTAG interface; and acquiring an output signal of the output end of the MBIST at the signal receiving side of the TDO interface in the JTAG interface. The aging signal comprises: a first aging signal and a second aging signal, wherein the first aging signal comprises: first burn-in enable signal, first burn-in clock signal, burn-in control signal and burn-in data, the second burn-in signal includes: a second burn-in enable signal, a second burn-in clock signal, and an MBIST self reset signal. Accordingly, the generating module can be implemented by adopting the following structure. Specifically, the generating module includes: a TAP controller, a burn-in controller, and a mode selector. The TAP controller is used for generating a burn-in mode signal, a state control signal and a driving indication signal according to the clock signal and the mode selection signal. Specifically, the TAP controller is configured to generate a burn-in mode signal that continues to be at an active level when the clock signal is at an active level; generating a scan control signal of which the level is an effective level when the mode selection signal is a first selection timing signal; generating a pause control signal of which the level is an effective level when the mode selection signal is a second selection timing signal; and when the mode selection signal is the first selection timing signal, generating a driving indication signal with the active level. The burn-in controller is used for generating a burn-in control signal, a first burn-in enable signal and a first burn-in clock signal according to the clock signal, the burn-in mode signal and the state control signal; generating a second burn-in enable signal and a second burn-in clock signal according to the clock signal, the burn-in mode signal and the driving indication signal; and generating the MBIST self-reset signal according to the output signal of the MBIST output end. Specifically, the burn-in controller is configured to use the clock signal in the continuous clock in which the scan control signal is at an active level and the clock signal in the continuous clock in which the pause control signal is at an active level as the first burn-in clock signal; when the scanning control signal is at an effective level, generating that the first burn-in enabling signal with the effective level is effective; when the burn-in mode signal is at an effective level, the burn-in control signal with the level being at the effective level is generated to be effective; when the driving indication signal is at an active level, generating the second burn-in enable signal with the active level as the active level to be active; taking the clock signal in the continuous clock with the driving indication signal being at the active level as the second aging clock signal; and when the output signal of the MBIST output end is at an effective level, delaying for a preset time after the initial moment when the output signal of the MBIST output end is at the effective level, and generating the MBIST self-reset signal. And the mode selector is used for acquiring the aging data in the aging demand signal when the aging control signal is an effective signal. Correspondingly, the transmission module is specifically configured to transmit the first burn-in signal to the burn-in chain, so that the burn-in chain burns out a logic function unit of the integrated circuit according to the first burn-in signal; and transmitting the second aging signal to the MBIST so that the MBIST executes an embedded storage unit aging process according to the second aging signal.
Further, in order to obtain the burn-in result to monitor the quality of the integrated circuit, the burn-in apparatus according to the second embodiment further includes: and an output module. And the output module is used for outputting the aging result through a TDO interface in the JTAG interface. Here, it should be noted that: when the aging unit in the integrated circuit is an aging chain or an MBIST, the aging device only needs the output module and is used for outputting the aging result of the logic function unit or the aging result of the embedded storage unit through the TDO interface in the JTAG interface. However, when the burn-in unit in the integrated circuit includes a burn-in chain and an MBIST, at this time, there are two burn-in results obtained by the burn-in of the integrated circuit, which are respectively a logic function unit burn-in result and an embedded memory unit burn-in result, and there is only one TDO interface in the JTAG interface, so the burn-in apparatus described in the second embodiment above should also include; and an output selection module. Specifically, the output selection module is configured to generate a burn-in result output control signal according to a preset output policy. The output module is used for outputting a logic function unit aging result through a TDO interface in the JTAG interface when the output control signal is a first control signal; and when the output control signal is a second control signal, outputting an aging result of the embedded memory cell through a TDO interface in the JTAG interface.
The aging method of the integrated circuit provided by the invention is further described below by combining specific application examples.
As shown in fig. 3, a schematic diagram of a method for aging an integrated circuit according to a third embodiment of the present invention is provided. As shown in fig. 3, in this embodiment, a triple burn-in object is a logic function circuit of an integrated circuit, that is, a burn-in signal is sent to a burn-in chain 4 in the integrated circuit, so that the burn-in chain burns out a logic function unit of the integrated circuit according to the burn-in signal. As shown in fig. 3, the aging apparatus according to the third embodiment includes: a receiving module, a TAP controller 1, a burn-in controller 2, a mode selector 5, and an output module 6. Wherein,
the receiving module is configured to receive the clock signal TCK through a test clock TCK interface 31 in the JTAG interface, receive the mode selection signal TMS through a test mode selection signal TMS interface 32 in the JTAG interface, and receive the burn-in data burn _ si through a test input data TDI interface 33 in the JTAG interface.
The TAP controller 1 is configured to generate a burn-in mode signal and a state control signal (shift _ dr _ c or Pause _ dr _ c shown in fig. 3) according to the clock signal TCK and the mode select signal TMS.
The burn-in controller 2 is configured to generate a burn-in control signal burn _ mode, a first burn-in enable signal Scan _ en, and a first burn-in clock signal Scan _ clk according to the clock signal TCK, the burn-in mode signal, and the state control signal.
The mode selector 5 is configured to acquire the burn-in data in the burn-in demand signal when the burn-in control signal is an active signal, that is, the burn-in data received through the TDI interface of the JIAG interface.
The burn-in chain 4 is configured to burn in the logic function unit of the integrated circuit according to the first burn-in enable signal Scan _ en, the first burn-in clock signal Scan _ clk, and the burn-in data Burnin _ si.
And the output module 6 is configured to output the logic function burn-in result Burnin _ so through the TDO interface of the JIAG interface.
In the embodiment of the present invention, the TAP controller 1 and the burn-in controller 2 send a first burn-in enable signal Scan _ en and a first burn-in clock Scan _ clk to the burn-in chain 4, and burn-in data is input through the TDI port when the burn-in control signal is an active signal, so that a logic function unit inside an integrated circuit is turned over. The input of the burn-in chain is connected to a TDI port of a JTAG interface, and the data input into the burn-in chain can be controlled by controlling the input of the TDI, so that the burn-in data input into the burn-in chain can be controlled to overturn a logic function unit in the integrated circuit in the burn-in process, and a good burn-in effect can be achieved.
Here, it should be noted that: the burn-in chain described in this embodiment is composed of registers in logic units of the integrated circuit connected in series (not shown in fig. 3), and has two states, one is a scan shift state, and the other is a scan capture state, in which the burn-in chain is sequentially shifted into data of the TDI port, and in which the burn-in chain is in a function flip state. The switching of the two states is controlled by a first burn-in enabling signal Scan _ en, and when the Scan _ en is effective, a burn-in chain is in a scanning shift state; the burn chain is in the Scan capture state when Scan _ en is inactive. The more registers forming the burn-in chain, that is, the more logic units participating in burn-in, the better the burn-in effect of the integrated circuit, so that in practical application, the registers of all the logic units in the integrated circuit can be connected in series to form the burn-in chain.
The embodiment of the invention utilizes a JTAG interface to be accessed into a register of a logic function unit in an integrated circuit, namely a TAP controller and a burn-in controller of the JTAG interface send a first burn-in enabling signal and a first burn-in clock signal to a burn-in chain formed by serially connecting registers of the logic function unit in the integrated circuit, and send burn-in data to the burn-in chain through a TDI interface, so that the burn-in chain can burn-in the logic function unit of the integrated circuit according to the first burn-in enabling signal, the first burn-in clock signal and the burn-in data. The embodiment of the invention makes the burn-in test interface simple and convenient by using the JTAG interface, simplifies the burn-in test process of the integrated circuit, and simultaneously reduces the burn-in cost because the embodiment of the invention reuses the JTAG interface for testing the I/O port and does not need to redesign the burn-in scheme.
Further, in the third embodiment, the state control signal may specifically be a scan Shift control signal Shift _ dr _ c or a Pause control signal Pause _ dr _ c. Correspondingly, the TAP controller described in the third embodiment is specifically configured to: outputting a scan Shift control signal Shift _ DR _ c when the TAP controller is in the Shift _ DR state of fig. 4; when the TAP controller is in the Passe _ DR state of FIG. 4, a pause signal Passe _ DR _ c is output. In particular, FIG. 4 provides a schematic diagram of the TAP controller outputting a state control signal. The TAP controller operates in synchronization with the TCK signal and responds to the TMS signal. Under the control of the TCK signal and the TMS signal, the TAP controller selectively outputs different states. Specifically, regardless of the current state, as long as TMS keeps 5 TCK clocks high (i.e., 5 TCK clocks, TMS = 1), the TAP controller will return to the Test _ logic _ Reset0xF state. As shown in fig. 4, when burn-in Test is required, TMS is low (i.e., TMS = 0), the TAP controller jumps out of the Test _ logic _ Reset0xF state and enters Run _ Test/Idle0xC, as shown in fig. 5, in the 1 st, 2 nd and 3 rd TCK clocks, TMS =100 state and at the rising edge of the 3 rd TCK clock, the TAP controller enters the Shift _ DR state and outputs the scan Shift control signal Shift _ DR _ c, i.e., the first output terminal (Shift _ DR _ c signal output terminal shown in fig. 3) of the TAP controller outputs high level, as shown in fig. 5. As shown in fig. 4, if the TMS in the subsequent TCK clock is continuously 0, that is, as shown in fig. 5, the TMS in the 4 th to 7 th TCK clocks is continuously 0, the TAP controller is continuously in the Shift _ DR state, the Shift _ DR state is in the scan Shift state, and the time length of Shift _ DR is determined by the length of the Shift chain, that is, the number of clock cycles in the Shift _ DR state is equal to the number of registers in the Shift chain, so as to ensure that all registers in the Shift chain acquire the burn data from TDO in the Shift _ DR state. When all registers in the burn-in chain have shifted into the burn-in data at the TDI input, as in the example of fig. 3, the TAP controller jumps out of the Shift _ DR state into the Exit1-DR state on the rising edge of the 8 th TCK clock when TMS =1 in the 8 th TCK clock. As shown in fig. 5, if TMS =0 immediately in the 9 th TCK clock, the TAP controller transitions from the Exit1-DR state into the Pause _ DR state at the rising edge of the 9 th TCK clock, and outputs the Pause scan Shift control signal Shift _ DR _ c, that is, the second output terminal (the Pause _ DR _ c signal output terminal shown in fig. 3) of the TAP controller outputs a high level, as shown in fig. 5. If TMS =1 in the 10 th TCK clock, the TAP controller transits from the Pause _ DR state to the Exit2-DR state at the rising edge of the 10 th TCK clock; TMS =0 in the 11 th TCK clock, the TAP controller transitions from the Exit2-DR state to the Shift _ DR state on the rising edge of the 11 th TCK clock. In the burn-in period of the integrated circuit supporting the JTAG standard according to the embodiment of the present invention, the TAP controller may use the timing signal diagram shown in fig. 5 to cyclically be in the Shift _ DR state-Exit 1-DR state-Pause _ DR state-Exit 2-DR-Shift _ DR state, that is, cyclically output the scan Shift control signal Shift _ DR _ c and the Pause scan Shift control signal Shift _ DR _ c, so that the burn-in controller outputs the corresponding first burn-in enable signal and first burn-in clock signal to perform the burn-in test on the integrated circuit until the burn-in is finished. In addition, the end condition of the aging test is usually the aging time. The aging time can be determined by referring to the statistical data of aging faults and fault analysis collected previously, or the aging intensity and time can be determined according to the actual requirement of the user.
What needs to be added here is: since the embodiment is to reuse the JTAG interface for I/O port test to burn in the integrated circuit, the integrated circuit described in this embodiment can enter two operating modes: one is a custom dedicated burn-in mode and test instructions specific to the JTAG protocol such as EXTEST, SAMPLE/PRELOAD, BYPASS. As shown in fig. 3 and 5, the integrated circuit enters the burn-in mode when the burn-in mode signal is active, such as high. When the burn-in mode is inactive, e.g., low, the integrated circuit enters a test mode. The TAP controller 1 can complete the configuration of a burn-in control instruction according to the clock signal TCK and the mode selection signal TMS, generate the burn-in mode signal according to the burn-in control instruction, output the burn-in mode signal to the burn-in controller 2, and generate the burn-in mode signal by the burn-in controller 2, so that the integrated circuit enters the burn-in mode, and a register connected with an internal logic function unit in the burn-in mode is a burn-in chain. Specifically, the burn-in control instruction generated by the TAP controller 1 is generated by the TAP controller according to the schematic diagram shown in fig. 4, specifically, the TAP controller may enter the instruction Scan state Select-IR-Scan0x4 according to the mode selection signal TMS shown in fig. 4, pass through the Capture-IR state, and move into the burn-in instruction in the Shift-IR state, and then pass through the Exit1-IR state-use-IR state-Exit 2-IR state to enter the Update-IR state, and Update the moved burn-in instruction to the current instruction in the Update-IR state, and the burn-in controller executes the current instruction and outputs the burn-in _ mode as valid.
Further, the burn-in controller 2 in the third embodiment is specifically configured to enable the first burn-in enable signal when the state control signal is a scan shift control signal.
Further, the burn-in controller 2 is further configured to, when the state control signal is a scan pause shift control signal, disable the first burn-in enable signal, and pause execution of a burn-in chain shift-in data process, so that the integrated circuit is in a normal functional state.
Further, the burn-in controller is further configured to, when the state control signal is in a scan Shift control signal duration and in a scan pause Shift control signal Shift _ dr _ c duration, acquire a clock signal TCK in the scan Shift control signal duration and in the scan pause Shift control signal Shift _ dr _ c duration as a first burn-in clock, and send the first burn-in clock to a register of the burn-in chain, so that the burn-in chain performs scan Shift in the scan Shift control signal duration as the state control signal, and sequentially transfers burn-in data into the burn-in chain from the TDO port; and the burn-in chain carries out logic inversion of a normal function path in a continuous section of the state control signal being a pause scanning Shift control signal Shift _ dr _ c.
Specifically, as shown in fig. 6, when the state control signal is a Scan Shift control signal, i.e., Shift _ dr _ c shown in fig. 6 is active (high level shown in fig. 6), the burn-in controller first burn-in enable signal Scan _ en is active (high level shown in fig. 6); when shift _ dr _ c is inactive (low level as shown in fig. 6), the first burn-in enable signal Scan _ en is inactive. When the state is a Scan Shift control signal or a Pause signal, that is, Shift _ dr _ c is at a high level or Pause _ dr _ c is at a high level, the TCK is acquired as the first burn-in clock signal Scan _ clk. When the first burn-in enable signal Scan _ en is valid, the burn-in chain sequentially shifts in data of the TDO, and when the first burn-in enable signal Scan _ en is invalid and the Pause _ dr _ c is valid, the burn-in chain does not perform a shift operation and performs logic inversion of a normal function path. The scan shift process of the burn-in chain (scan _ en active period) and the burn-in chain logic flip process (scan _ en inactive and Pause _ dr _ c active) constitute the burn-in process of the integrated circuit. The internal logic of the integrated circuit is in the staggered circulation of aging chain shift and function turnover until the aging is finished.
Based on the above, the method for aging an integrated circuit provided in the third embodiment includes the following steps:
step 201, the receiving module receives a clock signal TCK through a TCK interface 31 of a JTAG interface, receives a mode selection signal TMS through a TMS interface 32 of the JTAG interface, and receives burn-in data through a TDI interface 33 of the JTAG interface.
In step 202, the TAP controller 1 generates a burn-in mode signal and a state control signal according to the clock signal TCK and the mode select signal TMS.
Step 203, the burn-in controller 2 generates a burn-in control signal burn _ mode, a first burn-in enable signal Scan _ en, and a first burn-in clock signal Scan _ clk according to the clock signal TCK, the burn-in mode signal, and the state control signal.
And 204, when the burn-in control signal burn _ mode is an effective signal, the mode selector 5 acquires the burn-in data in the burn-in demand signal.
Step 205, transmitting the obtained burn-in data, the first burn-in enable signal and the first burn-in clock signal to the burn-in chain 4, so that the burn-in chain 4 conducts burn-in on the logic function unit of the integrated circuit according to the burn-in data, the first burn-in enable signal and the first burn-in clock signal.
And step 206, the output module 6 outputs a logic function aging result through the TDO interface of the JTAG interface.
Here, it should be noted that: for the specific implementation principle and implementation process of each step, reference may be made to the related contents described in the third embodiment before the above method step, and details are not described here again.
The embodiment of the invention utilizes a JTAG interface to be accessed into a register of a logic function unit in an integrated circuit, namely a TAP controller and a burn-in controller of the JTAG interface send a first burn-in enabling signal and a first burn-in clock to a burn-in chain formed by serially connecting registers of the logic function unit in the integrated circuit, and send burn-in data to the burn-in chain through a TDI interface, so that the burn-in chain can burn-in the logic function unit of the integrated circuit according to the first burn-in enabling signal, the first burn-in clock signal and the burn-in data. The embodiment of the invention makes the burn-in test interface simple and convenient by using the JTAG interface, simplifies the burn-in test process of the integrated circuit, and simultaneously reduces the burn-in cost because the embodiment of the invention reuses the JTAG interface for testing the I/O port and does not need to redesign the burn-in scheme.
As shown in fig. 7, a schematic diagram of a method for aging an integrated circuit according to a fourth embodiment of the present invention is provided. As shown in fig. 7, the four aging targets of the present embodiment are memory cells of an integrated circuit. In which the relevant functional circuit implanted in the circuit when the integrated circuit is designed is used as a self-test unit for providing a self-test function, i.e., MBIST shown in fig. 7. The MBIST includes test circuitry for loading, reading and comparing test patterns. In the aging process, the memory cell of the integrated circuit enters an operation state of operating the MBIST, and the memory cell of the integrated circuit is subjected to cyclic read-write operation through the MBIST so as to realize aging of the memory cell. As shown in fig. 7, the aging apparatus according to the fourth embodiment includes: a receiving module, a TAP controller 1, a burn-in controller 2, and an output module 6. Wherein,
the receiving module is used for receiving the clock signal through a TCK interface in the JTAG interface; receiving the mode selection signal through a TMS interface in the JTAG interface; the signal receiving side 34 of the test output data TDO interface in the JTAG interface obtains the output signal Bist _ end at the output terminal of MBIST 7.
The TAP controller 1 is configured to generate a burn-in mode signal and a driving indication signal run _ idle _ c according to the clock signal TCK and the mode select signal TMS.
The burn-in controller 2 is configured to generate a second burn-in enable signal Bist _ en and a second burn-in clock signal Bist _ clk according to the clock signal TCK, the burn-in mode signal, and the drive indication signal run _ idle _ c; and generating the MBIST self-reset signal Bist _ reset according to the output signal Bist _ end of the output end of the MBIST.
The MBIST7 is configured to perform a burn-in process of the embedded memory cell according to the second burn-in enable signal Bist _ en, the MBIST self-reset signal Bist _ reset, and the second burn-in clock signal Bist _ clk.
And the output module 6 is used for outputting the aging result of the embedded storage unit through the TDO interface of the JTAG interface.
In the embodiment, the JTAG interface is accessed to the MBIST in the integrated circuit, that is, the TAP controller and the burn-in controller of the JTAG interface send the second enable signal, the MBIST self-reset signal and the second burn-in clock signal to the MBIST, so as to implement the read-write operation of the memory cell of the integrated circuit through the MBIST, thereby achieving the purpose of burn-in the memory cell. The embodiment of the invention reuses the JTAG interface for the I/O port test, does not need to redesign the burn-in scheme, has simpler and more convenient connection of the burn-in test interface, simplifies the burn-in test process of the integrated circuit, and simultaneously reduces the burn-in cost.
When the TAP controller is in the non-run _ test/Idle state in fig. 4, as shown in fig. 8, when the output signal Bist _ end of the MBIST output terminal is low, the MBIST self-reset signal Bist _ reset is high; the MBIST carries out read-write operation on a storage unit of the integrated circuit; when the output signal Bist _ end signal of the output end of the MBIST is high, a certain delay t is passed, so that the MBIST self-reset signal Bist _ reset is low level. The MBIST is customizable from the time that the reset signal Bist _ reset is low. In the aging process, after the TAP controller leaves the run _ test/Idle state, the execution of the MBIST is completely controlled by the Bist _ end and is in a self-circulation state. And reading and writing the storage unit by using an MBIST self-circulation mode until the aging is finished. Wherein the aging finish condition is generally an aging time. The aging time is determined by a model and a universal formula which are not precisely fixed, and can be determined by referring to the previously collected statistical data of aging faults and fault analysis, or the aging strength and the aging time can be determined according to the actual requirements of the user.
Here, it should be noted that: prior to burn-in testing, the TAP controller is brought into a Run _ test/Idle (0XC) state according to the state machine principles of FIG. 4. Waiting for a specific time in the state, wherein the time can be customized by the sequence number of TMS signals. In this state, the bit _ reset is controlled to low level, and MBIST is initialized.
Further, the burn-in controller 2 in the second embodiment is specifically configured to generate the second burn-in enable signal according to the clock signal, and acquire the clock signal as the second burn-in clock signal; and when the output signal of the output end of the MBIST is at an effective level, generating the MBIST self-reset signal after a preset delay time.
Specifically, as shown in fig. 8, the burn-in controller 2 in this embodiment generates the second burn-in enable signal Bist _ en after receiving the burn-in mode signal sent by the TAP controller, and as shown in fig. 8, the second burn-in enable signal Bist _ en starts to be continuously at a high level after the burn-in mode signal is high. The burn-in controller 2 takes the received TCK clock signal as the second burn-in clock signal Bist _ clk. The bit _ rest shown in fig. 8 is active low, that is, when the bit _ rest is active low, MBIST is in a reset state, and MBIST does not perform read/write operations on the memory cells in the integrated circuit. When Bist _ rest is high, the MBIST operates to read and write the memory cells in the integrated circuit. When the output end of the MBIST is at a low level, the Bist _ rest is always at a high level, and when the output end of the MBIST is at the high level, the Bist _ rest is changed from the high level to the low level after a preset delay time t. The purpose of the delay time t is to wait for the end of the MBIST operation and then perform a reset operation on the MBIST.
Here, it should be noted that: in fact, it can be designed to be effective when the bist _ reset is high or effective when the bist _ reset is low according to the difference of the design of MBIST. The low-to-high cycling of the Bist _ reset period can control the periodic start of the MBIST. No matter the MBIST is reset at high level or low level, the self-circulation starting mode can be used, and the MBIST circulation is used for carrying out read-write operation on the storage unit, so that the purpose of aging the storage unit is achieved.
Based on the above, the method for aging an integrated circuit provided in the fourth embodiment includes the following steps:
301, the receiving module receives the clock signal TCK through a TCK interface 31 in the JTAG interface; receiving the mode select signal TMS through a TMS interface 32 in the JTAG interface; the output signal BIST _ end at the MBIST output is taken at the signal receiving side 34 of the test output data TDO interface in the JTAG interface.
In step 302, the TAP controller 1 generates a burn-in mode signal and a driving indication signal run _ idle _ c according to the clock signal TCK and the mode select signal TMS.
The implementation principle of generating the burn-in mode signal by the TAP control according to the clock signal TCK and the mode select signal TMS in this embodiment is the same as that described in the third embodiment, and details are not repeated here. In addition, the TAP controller operates in synchronization with the TCK signal and responds to a TMS signal. Under the control of the TCK signal and the TMS signal, the TAP controller selectively outputs different states. As shown in fig. 4, when the TAP controller is in a Run/Test _ idle state, the TAP controller generates the driving indication signal Run _ idle _ c to be active.
Step 303, the burn-in controller 2 generates a second burn-in enable signal Bist _ en and the second burn-in clock signal Bist _ clk according to the clock signal TCK, the burn-in mode signal, and the driving indication signal run _ idle _ c.
Here, it should be noted that: prior to burn-in testing, the TAP controller is brought into a Run _ test/Idle (0XC) state according to the state machine principles of FIG. 4. Waiting for a specific time in the state, wherein the time can be customized by the sequence number of TMS signals. In this state, the bit _ reset is controlled to low level, and MBIST is initialized.
And step 304, the aging controller 2 generates the MBIST self-reset signal according to the output signal of the MBIST output end.
And 305, the MBIST executes the burn-in process of the embedded memory cell according to the second burn-in enable signal Bist _ en, the MBIST self-reset signal Bist _ reset and the second burn-in clock signal Bist _ clk.
And step 306, the output module 6 outputs the aging result of the embedded memory unit through the TDO interface of the JTAG interface.
Here, it should be noted that: for the specific implementation principle and implementation process of each step, reference may be made to the related contents described in the fourth embodiment before the above method step, and details are not described here again.
In the fourth embodiment, the JTAG interface is accessed to the MBIST in the integrated circuit, that is, the TAP controller and the burn-in controller of the JTAG interface send the second enable signal, the MBIST self-reset signal and the second burn-in clock signal to the MBIST, so as to implement the read-write operation of the memory cell of the integrated circuit through the MBIST, thereby achieving the purpose of burn-in of the memory cell. The embodiment of the invention reuses the JTAG interface for the I/O port test, does not need to redesign the burn-in scheme, has simpler and more convenient connection of the burn-in test interface, simplifies the burn-in test process of the integrated circuit, and simultaneously reduces the burn-in cost.
As shown in fig. 9, a schematic diagram of a method for aging an integrated circuit according to a fifth embodiment of the present invention is provided. As shown in fig. 9, the aging target of the fifth embodiment is a logic function circuit and a storage unit of an integrated circuit, that is, the aging method provided by the fifth embodiment can implement simultaneous aging of the logic function circuit and the storage unit. As shown in fig. 9, the aging apparatus according to the fifth embodiment includes: a receiving module, a TAP controller 1, a burn-in controller 2, a mode selector 5, an output selection module 8, and an output module 6. Wherein,
the receiving module is configured to receive the clock signal through a TCK interface 31 in the JTAG interface; receiving the mode selection signal through a TMS interface 32 in the JTAG interface; receiving the aging data through a TDI interface 33 in the JTAG interface; the output signal at the MBIST output is taken at the signal receive side 34 of the TDO interface of the JTAG interfaces.
The TAP controller 1 is configured to generate a burn-in mode signal, a state control signal (Shift _ dr _ c or sweep _ dr _ c shown in fig. 9), and a driving indication signal run _ idle _ c according to the clock signal TCK and the mode select signal TMS.
The burn-in controller 2 is configured to generate a burn-in control signal burn-in _ mode, a first burn-in enable signal Scan _ en, and a first burn-in clock signal Scan _ clk according to the clock signal TCK, the burn-in mode signal TMS, and the state control signal (Shift _ dr _ c or sweep _ dr _ c shown in fig. 9); and generating a second burn-in enable signal Bist _ en and a second burn-in clock signal Bist _ clk according to the clock signal TCK, the burn-in mode signal TMS and the driving indication signal run _ idle _ c.
The mode selector 5 is configured to acquire the burn-in data in the burn-in demand signal when the burn-in control signal burn-mode is an active signal.
For example, when the burn-in control signal is at a high level, i.e., burn-in _ mode =1, the burn-in data in the burn-in demand signal is acquired.
The burn-in chain 4 is configured to burn in the logic function unit of the integrated circuit according to the first burn-in enable signal Scan _ en, the first burn-in clock signal Scan _ clk, and the burn-in data Burnin _ si.
The MBIST7 is configured to burn in the embedded memory cell of the integrated circuit according to the second burn-in enable signal Bist _ en, the MBIST self-reset signal Bist _ reset, and the second burn-in clock signal Bist _ clk.
And the output selection module 8 is used for generating a burn-in result output control signal according to a preset output strategy.
The output module 6 is configured to output a logic function unit aging result through a TDO interface in the JTAG interface when the output control signal is a first control signal; and when the output control signal is a second control signal, outputting an aging result of the embedded memory cell through a TDO interface in the JTAG interface.
Specifically, as shown in fig. 9, when the Output control signal Output _ mode =1, a logic function burn-in result is Output through the TDO interface in the JTAG interface; and when the Output control signal Output _ mode =0, outputting an aging result of the embedded memory cell through a TDO interface in the JTAG interface. When the Output control signal Output _ mode is at a high level (i.e., Output _ mode = 1), the TDO interface 5 outputs a logic function burn-in result; when the Output control signal Output _ mode is low (i.e., Output _ mode = 0), the TDO interface 5 outputs the aging result of the embedded memory cell. Of course, the way of outputting the aging result of the logic function and the aging result of the embedded storage unit by the TDO interface according to the embodiment of the present invention is not limited to the above implementation way, and the corresponding aging result may be output within a predetermined time by presetting, such as setting time.
The embodiment of the invention can realize the simultaneous burn-in of the logic unit and the memory unit by utilizing the JTAG interface, and because the JTAG interface for the I/O port test is multiplexed, the burn-in scheme does not need to be redesigned, the connection of the burn-in test interface is simpler and more convenient, the burn-in test process of the integrated circuit is simplified, and the burn-in cost is also reduced.
Here, it should be noted that: for the specific implementation principle and implementation process of each step, reference may be made to the relevant contents described in the third embodiment and the fourth embodiment, which are not described herein again.
It should be noted that: while, for purposes of simplicity of explanation, the foregoing method embodiments have been described as a series of acts or combination of acts, it will be appreciated by those skilled in the art that the present invention is not limited by the illustrated ordering of acts, as some steps may occur in other orders or concurrently with other steps in accordance with the invention. Further, those skilled in the art should also appreciate that the embodiments described in the specification are preferred embodiments and that the acts and modules referred to are not necessarily required by the invention.
In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.
Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (20)
1. A method of aging an integrated circuit, comprising:
receiving a burn-in demand signal through a Joint Test Action Group (JTAG) interface, the burn-in demand signal comprising: clock signals, mode selection signals, and burn-in data;
generating a burn-in signal required by a burn-in unit in the integrated circuit for burn-in by adopting a preset signal generation rule according to the burn-in demand signal;
transmitting the burn-in signal to a burn-in unit in the integrated circuit, so that the burn-in unit executes a burn-in process of the integrated circuit according to the burn-in signal;
the burn-in unit is a burn-in chain formed by serially connecting registers in a logic function unit of the integrated circuit;
the aging signal comprises: a first burn-in enable signal, a first burn-in clock signal, a burn-in control signal, and the burn-in data;
according to burn-in demand signal adopts the signal generation rule of predetermineeing to generate the unit of burn-in the integrated circuit and carries out the required signal of burn-in, include:
when the clock signal is at an effective level, generating a burn-in mode signal which is continuously at the effective level;
generating a scan control signal of which the level is an effective level when the mode selection signal is a first selection timing signal; generating a pause control signal of which the level is an effective level when the mode selection signal is a second selection timing signal;
taking the clock signal in the continuous clock with the scanning control signal being at the active level and the clock signal in the continuous clock with the pause control signal being at the active level as the first burn-in clock signal;
when the scanning control signal is at an effective level, generating that the first burn-in enabling signal with the effective level is effective;
when the burn-in mode signal is at an effective level, the burn-in control signal with the level being at the effective level is generated to be effective;
and when the aging control signal is at an effective level, acquiring the aging data in the aging demand signal.
2. The method of claim 1, wherein the burn-in unit performs a burn-in process of the integrated circuit based on the burn-in signal, specifically:
and the burn-in chain is used for burn-in the logic function unit of the integrated circuit according to the burn-in signal.
3. The method of claim 1 or 2, wherein when the burn-in unit is a burn-in chain of registers in a logic functional unit of the integrated circuit in series;
accordingly, the receiving the burn-in demand signal through the JTAG interface includes:
receiving the clock signal through a test clock TCK interface in the JTAG interface;
receiving the mode selection signal through a TMS interface in the JTAG interface;
and receiving the burn-in data through a test input data TDI interface in the JTAG interface.
4. A method of aging an integrated circuit, comprising:
receiving a burn-in demand signal through a Joint Test Action Group (JTAG) interface, the burn-in demand signal comprising: clock signals, mode selection signals and output signals of an MBIST output end;
generating a burn-in signal required by a burn-in unit in the integrated circuit for burn-in by adopting a preset signal generation rule according to the burn-in demand signal;
transmitting the burn-in signal to a burn-in unit in the integrated circuit, so that the burn-in unit executes a burn-in process of the integrated circuit according to the burn-in signal;
the burn-in unit is an MBIST for performing storage self-test on an embedded storage unit in the integrated circuit;
the aging signal comprises: a second burn-in enable signal, a second burn-in clock signal, and an MBIST self-reset signal;
according to burn-in demand signal adopts the signal generation rule of predetermineeing to generate the unit of burn-in the integrated circuit and carries out the required signal of burn-in, include:
when the clock signal is at an effective level, generating a burn-in mode signal which is continuously at the effective level;
when the mode selection signal is a first selection timing signal, generating a driving indication signal with an effective level;
when the driving indication signal is at an active level, generating the second burn-in enable signal with the active level as the active level to be active;
taking the clock signal in the continuous clock with the driving indication signal being at the active level as the second aging clock signal;
and when the output signal of the MBIST output end is at an effective level, delaying for a preset time after the initial moment when the output signal of the MBIST output end is at the effective level, and generating the MBIST self-reset signal.
5. The method of claim 4, wherein the burn-in unit performs a burn-in process of the integrated circuit based on the burn-in signal, specifically:
and the MBIST is used for aging the embedded storage unit of the integrated circuit according to the aging signal.
6. The method of claim 4 or 5, wherein receiving the burn-in demand signal via the JTAG interface comprises:
receiving the clock signal through a TCK interface in the JTAG interface;
receiving the mode selection signal through a TMS interface in the JTAG interface;
and acquiring an output signal of the output end of the MBIST at a signal receiving side of a test output data TDO interface in the JTAG interface.
7. The method of claim 4 or 5, wherein transmitting the burn-in signal to a burn-in unit in the integrated circuit such that the burn-in unit performs a burn-in process based on the burn-in signal further comprises:
and outputting a burn-in result through a TDO interface in the JTAG interface.
8. A method of aging an integrated circuit, comprising:
receiving a burn-in demand signal through a Joint Test Action Group (JTAG) interface, the burn-in demand signal comprising: clock signals, mode selection signals, burn-in data and output signals of an MBIST output end;
generating a burn-in signal required by a burn-in unit in the integrated circuit for burn-in by adopting a preset signal generation rule according to the burn-in demand signal;
transmitting the burn-in signal to a burn-in unit in the integrated circuit, so that the burn-in unit executes a burn-in process of the integrated circuit according to the burn-in signal;
wherein, the unit of smelting always includes: the register of the logic function unit in the integrated circuit is connected in series to form a burn-in chain, and the MBIST in the integrated circuit;
the aging signal comprises: a first aging signal and a second aging signal, wherein the first aging signal comprises: first burn-in enable signal, first burn-in clock signal, burn-in control signal and burn-in data, the second burn-in signal includes: a second burn-in enable signal, a second burn-in clock signal, and an MBIST self-reset signal;
according to burn-in demand signal adopts the signal generation rule of predetermineeing to generate the unit of burn-in the integrated circuit and carries out the required signal of burn-in, include:
when the clock signal is at an effective level, generating a burn-in mode signal which is continuously at the effective level;
generating a scan control signal of which the level is an effective level when the mode selection signal is a first selection timing signal; generating a pause control signal of which the level is an effective level when the mode selection signal is a second selection timing signal;
taking the clock signal in the continuous clock with the scanning control signal being at the active level and the clock signal in the continuous clock with the pause control signal being at the active level as the first burn-in clock signal;
when the scanning control signal is at an effective level, generating that the first burn-in enabling signal with the effective level is effective;
when the burn-in mode signal is at an effective level, the burn-in control signal with the level being at the effective level is generated to be effective;
when the burn-in control signal is at an effective level, the burn-in data in the burn-in demand signal is obtained;
when the mode selection signal is a first selection timing signal, generating a driving indication signal with an effective level;
when the driving indication signal is at an active level, generating the second burn-in enable signal with the active level as the active level to be active;
taking the clock signal in the continuous clock with the driving indication signal being at the active level as the second aging clock signal;
and when the output signal of the MBIST output end is at an effective level, delaying for a preset time after the initial moment when the output signal of the MBIST output end is at the effective level, and generating the MBIST self-reset signal.
9. The method of claim 8, wherein receiving the burn-in demand signal via a JTAG interface comprises:
receiving the clock signal through a TCK interface in the JTAG interface;
receiving the mode selection signal through a TMS interface in the JTAG interface;
receiving the aging data through a TDI interface in the JTAG interface;
and acquiring an output signal of the output end of the MBIST at the signal receiving side of the TDO interface in the JTAG interface.
10. The method of claim 9, wherein transmitting the burn-in signal to a burn-in unit in the integrated circuit to cause the burn-in unit to perform a burn-in process for the integrated circuit based on the burn-in signal comprises:
transmitting the first burn-in signal to the burn-in chain, so that the burn-in chain can burn in the logic function unit of the integrated circuit according to the first burn-in signal;
and transmitting the second burn-in signal to the MBIST so that the MBIST burns in the embedded storage unit of the integrated circuit according to the second burn-in signal.
11. The method of any of claims 8-10, wherein said transmitting said burn-in signal to a burn-in unit in said integrated circuit such that said burn-in unit performs said integrated circuit burn-in process based on said burn-in signal further comprises:
generating a burn-in result output control signal according to a preset output strategy;
when the output control signal is a first control signal, outputting a logic function unit aging result through a TDO interface in the JTAG interface;
and when the output control signal is a second control signal, outputting an aging result of the embedded memory cell through a TDO interface in the JTAG interface.
12. An aging device, comprising:
a receiving module, configured to receive a burn-in demand signal through a JTAG interface, where the burn-in demand signal includes: clock signals, mode selection signals, and burn-in data;
the generating module is used for generating a burn-in signal required by a burn-in unit in the integrated circuit for burn-in by adopting a preset signal generating rule according to the burn-in demand signal;
the transmission module is used for transmitting the burn-in signal to a burn-in unit in the integrated circuit so that the burn-in unit executes the burn-in process of the integrated circuit according to the burn-in signal;
the burn-in unit is a burn-in chain formed by serially connecting registers in a logic function unit of the integrated circuit;
the aging signal comprises: a first burn-in enable signal, a first burn-in clock signal, a burn-in control signal, and the burn-in data;
the generation module comprises:
a Test Access Port (TAP) controller, configured to generate a burn-in mode signal that continues to be at an active level when the clock signal is at an active level; generating a scan control signal of which the level is an effective level when the mode selection signal is a first selection timing signal; generating a pause control signal of which the level is an effective level when the mode selection signal is a second selection timing signal;
a burn-in controller for taking the clock signal in the continuous clock in which the scan control signal is at an active level and the clock signal in the continuous clock in which the pause control signal is at an active level as the first burn-in clock signal; when the scanning control signal is at an effective level, generating that the first burn-in enabling signal with the effective level is effective; when the burn-in mode signal is at an effective level, the burn-in control signal with the level being at the effective level is generated to be effective;
and the mode selector is used for acquiring the burn-in data in the burn-in demand signal when the burn-in control signal is at an effective level.
13. The aging apparatus of claim 12,
the receiving module is specifically configured to receive the clock signal through a TCK interface in the JTAG interface; receiving the mode selection signal through a TMS interface in the JTAG interface; and receiving the aging data through a TDI interface in the JTAG interface.
14. An aging device, comprising:
a receiving module, configured to receive a burn-in demand signal through a JTAG interface, where the burn-in demand signal includes: clock signals, mode selection signals and output signals of an MBIST output end;
the generating module is used for generating a burn-in signal required by a burn-in unit in the integrated circuit for burn-in by adopting a preset signal generating rule according to the burn-in demand signal;
the transmission module is used for transmitting the burn-in signal to a burn-in unit in the integrated circuit so that the burn-in unit executes the burn-in process of the integrated circuit according to the burn-in signal;
wherein the burn-in unit is a memory built-in self test unit (MBIST) in the integrated circuit;
the aging signal comprises: a second burn-in enable signal, a second burn-in clock signal, and an MBIST self-reset signal; accordingly, the generating module comprises:
the TAP controller is used for generating a burn-in mode signal which is continuously at an effective level when the clock signal is at the effective level; when the mode selection signal is a first selection timing signal, generating a driving indication signal with an effective level;
the burn-in controller is used for generating a second burn-in enabling signal with the level being the effective level to be effective when the driving indication signal is the effective level; taking the clock signal in the continuous clock with the driving indication signal being at the active level as the second aging clock signal; and when the output signal of the MBIST output end is at an effective level, delaying for a preset time after the initial moment when the output signal of the MBIST output end is at the effective level, and generating the MBIST self-reset signal.
15. The aging apparatus of claim 14,
the receiving module is specifically configured to receive the clock signal through a TCK interface in the JTAG interface; receiving the mode selection signal through a TMS interface in the JTAG interface; and acquiring an output signal of the output end of the MBIST at the signal receiving side of the TDO interface in the JTAG interface.
16. The aging apparatus as set forth in claim 14 or 15, further comprising:
and the output module is used for outputting the aging result through the TDO interface in the JTAG interface.
17. An aging device, comprising:
a receiving module, configured to receive a burn-in demand signal through a JTAG interface, where the burn-in demand signal includes: clock signals, mode selection signals, burn-in data and output signals of an MBIST output end;
the generating module is used for generating a burn-in signal required by a burn-in unit in the integrated circuit for burn-in by adopting a preset signal generating rule according to the burn-in demand signal;
the transmission module is used for transmitting the burn-in signal to a burn-in unit in the integrated circuit so that the burn-in unit executes the burn-in process of the integrated circuit according to the burn-in signal;
wherein, the unit of smelting always includes: the register of the logic function unit in the integrated circuit is connected in series to form a burn-in chain, and the MBIST in the integrated circuit;
the aging signal comprises: a first aging signal and a second aging signal, wherein the first aging signal comprises: first burn-in enable signal, first burn-in clock signal, burn-in control signal and burn-in data, the second burn-in signal includes: a second burn-in enable signal, a second burn-in clock signal, and an MBIST self-reset signal;
the generation module comprises:
the TAP controller is used for generating a burn-in mode signal which is continuously at an effective level when the clock signal is at the effective level; generating a scan control signal of which the level is an effective level when the mode selection signal is a first selection timing signal; generating a pause control signal of which the level is an effective level when the mode selection signal is a second selection timing signal; when the mode selection signal is a first selection timing signal, generating a driving indication signal with an effective level;
a burn-in controller for taking the clock signal in the continuous clock in which the scan control signal is at an active level and the clock signal in the continuous clock in which the pause control signal is at an active level as the first burn-in clock signal; when the scanning control signal is at an effective level, generating that the first burn-in enabling signal with the effective level is effective; when the burn-in mode signal is at an effective level, the burn-in control signal with the level being at the effective level is generated to be effective; when the driving indication signal is at an active level, generating the second burn-in enable signal with the active level as the active level to be active; taking the clock signal in the continuous clock with the driving indication signal being at the active level as the second aging clock signal; when the output signal of the MBIST output end is at an effective level, delaying for a preset time after the initial moment when the output signal of the MBIST output end is at the effective level, and generating an MBIST self-reset signal;
and the mode selector is used for generating a driving indication signal with the active level when the mode selection signal is the first selection timing signal.
18. The aging apparatus of claim 17,
the receiving module is specifically configured to receive the clock signal through a TCK interface in the JTAG interface; receiving the mode selection signal through a TMS interface in the JTAG interface; receiving the aging data through a TDI interface in the JTAG interface; and acquiring an output signal of the output end of the MBIST at the signal receiving side of the TDO interface in the JTAG interface.
19. The burn-in apparatus of claim 17, wherein said transmitting module is specifically configured to transmit said first burn-in signal to said burn-in chain, such that said burn-in chain will burn-in logic functional units of said integrated circuit based on said first burn-in signal; and transmitting the second burn-in signal to the MBIST so that the MBIST burns in the embedded storage unit of the integrated circuit according to the second burn-in signal.
20. The aging apparatus of any of claims 17-19, further comprising:
the output selection module is used for generating a burn-in result output control signal according to a preset output strategy;
the output module is used for outputting a logic function unit aging result through a TDO interface in the JTAG interface when the output control signal is a first control signal; and when the output control signal is a second control signal, outputting an aging result of the embedded memory cell through a TDO interface in the JTAG interface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310728263.XA CN103698689B (en) | 2013-12-25 | 2013-12-25 | The ageing method and ageing device of integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310728263.XA CN103698689B (en) | 2013-12-25 | 2013-12-25 | The ageing method and ageing device of integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103698689A CN103698689A (en) | 2014-04-02 |
| CN103698689B true CN103698689B (en) | 2018-04-24 |
Family
ID=50360284
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310728263.XA Active CN103698689B (en) | 2013-12-25 | 2013-12-25 | The ageing method and ageing device of integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103698689B (en) |
Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105184413B (en) * | 2015-09-22 | 2019-01-25 | 北京航空航天大学 | A method for estimating optimal burn-in test time for products considering manufacturing quality deviation loss |
| CN106649180B (en) * | 2016-09-09 | 2019-08-20 | 锐捷网络股份有限公司 | A kind of releasing I2The method and device of C bus deadlock |
| CN106569124A (en) * | 2016-11-09 | 2017-04-19 | 中国空间技术研究院 | Universal dynamic aging system for Virtex-5 FPGAs (field programmable gate arrays) |
| CN108257895B (en) * | 2018-01-18 | 2024-04-12 | 深圳市振华微电子有限公司 | Power aging method and aging device for semiconductor power module |
| CN110118921B (en) * | 2018-02-07 | 2021-08-03 | 龙芯中科技术股份有限公司 | Integrated circuit input end testing device and integrated circuit |
| CN110441672A (en) * | 2019-08-06 | 2019-11-12 | 西安太乙电子有限公司 | A kind of SoC type integrated circuit dynamic device and method |
| CN111161788A (en) * | 2019-12-18 | 2020-05-15 | 航天科工防御技术研究试验中心 | Aging testing device of memory |
| CN113985248B (en) * | 2021-10-26 | 2023-07-11 | 西安微电子技术研究所 | High-temperature dynamic aging system and method for PCIe (peripheral component interconnect express) switching circuit |
| CN115113021A (en) * | 2022-06-20 | 2022-09-27 | 西安微电子技术研究所 | A test device and method for PCIe switching circuit |
| CN116243137B (en) * | 2022-12-22 | 2023-12-01 | 无锡麟聚半导体科技有限公司 | Test mode protection circuit and chip |
| CN118376909B (en) * | 2024-06-25 | 2024-08-16 | 中国人民解放军国防科技大学 | Integrated circuit, system and method with built-in dynamic burn-in control |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1225724A (en) * | 1996-05-17 | 1999-08-11 | 佛姆法克特股份有限公司 | Wafer Level Burn-in and Test |
| US6681359B1 (en) * | 2000-08-07 | 2004-01-20 | Cypress Semiconductor Corp. | Semiconductor memory self-test controllable at board level using standard interface |
| JP2005180935A (en) * | 2003-12-16 | 2005-07-07 | Renesas Technology Corp | Semiconductor integrated circuit |
| US7275188B1 (en) * | 2003-10-10 | 2007-09-25 | Integrated Device Technology, Inc. | Method and apparatus for burn-in of semiconductor devices |
| CN101719088A (en) * | 2009-11-23 | 2010-06-02 | 北京龙芯中科技术服务中心有限公司 | Device and method for detecting processor chip on line |
| CN102419415A (en) * | 2011-08-31 | 2012-04-18 | 北京时代民芯科技有限公司 | TAP (Test Access Port) interface optimization circuit based on boundary scanning circuit |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN202385229U (en) * | 2011-11-18 | 2012-08-15 | 北京牡丹视源电子有限责任公司 | Signal source applicable to stereotelevision crosstalk measurement |
-
2013
- 2013-12-25 CN CN201310728263.XA patent/CN103698689B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1225724A (en) * | 1996-05-17 | 1999-08-11 | 佛姆法克特股份有限公司 | Wafer Level Burn-in and Test |
| US6681359B1 (en) * | 2000-08-07 | 2004-01-20 | Cypress Semiconductor Corp. | Semiconductor memory self-test controllable at board level using standard interface |
| US7275188B1 (en) * | 2003-10-10 | 2007-09-25 | Integrated Device Technology, Inc. | Method and apparatus for burn-in of semiconductor devices |
| JP2005180935A (en) * | 2003-12-16 | 2005-07-07 | Renesas Technology Corp | Semiconductor integrated circuit |
| CN101719088A (en) * | 2009-11-23 | 2010-06-02 | 北京龙芯中科技术服务中心有限公司 | Device and method for detecting processor chip on line |
| CN102419415A (en) * | 2011-08-31 | 2012-04-18 | 北京时代民芯科技有限公司 | TAP (Test Access Port) interface optimization circuit based on boundary scanning circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103698689A (en) | 2014-04-02 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103698689B (en) | The ageing method and ageing device of integrated circuit | |
| KR100267096B1 (en) | Adaptive scan chain for debug and manufacturing test purposes | |
| US12013434B2 (en) | Programmable test compression architecture input/output shift register coupled to SCI/SCO/PCO | |
| CA2421047C (en) | Method and apparatus for optimized parallel testing and access of electronic circuits | |
| US6101457A (en) | Test access port | |
| US6560739B1 (en) | Mechanism for enabling compliance with the IEEE standard 1149.1 for boundary-scan designs and tests | |
| JP3890126B2 (en) | Integrated circuit test clock generation method and circuit | |
| US11041905B2 (en) | Combinatorial serial and parallel test access port selection in a JTAG interface | |
| US10429441B2 (en) | Efficient test architecture for multi-die chips | |
| US20040006729A1 (en) | Hierarchical test methodology for multi-core chips | |
| US20160349320A1 (en) | Remote bus wrapper for testing remote cores using automatic test pattern generation and other techniques | |
| US7870448B2 (en) | In system diagnostics through scan matrix | |
| US20080001616A1 (en) | Testing Components of I/O Paths of an Integrated Circuit | |
| US7447962B2 (en) | JTAG interface using existing I/O bus | |
| US10890619B2 (en) | Sequential test access port selection in a JTAG interface | |
| KR100694315B1 (en) | Cable Delay Failure Test Controller for System-on-Chip with Multiple System Clocks and Heterogeneous Cores | |
| EP0837336B1 (en) | A method and apparatus for scan testing of electrical circuits | |
| Chunmei et al. | A Implementation for Built-in Self-Testing of RapidIO by JTAG | |
| Devadze et al. | Turning JTAG inside out for fast extended test access | |
| KR20010053900A (en) | Test circuit using delay chain circuit in semiconductor and testing method of the same | |
| Stout et al. | Innovative Test Solutions for Pin-Limited Microcontrollers | |
| Bleeker et al. | Hardware Test Innovations | |
| HK1064444B (en) | Method and apparatus for optimized parallel testing and access of electronic circuits |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CP03 | Change of name, title or address | ||
| CP03 | Change of name, title or address |
Address after: 100095 Building 2, Longxin Industrial Park, Zhongguancun environmental protection technology demonstration park, Haidian District, Beijing Patentee after: Loongson Zhongke Technology Co.,Ltd. Address before: 100190 No. 10 South Road, Haidian District Academy of Sciences, Beijing Patentee before: LOONGSON TECHNOLOGY Corp.,Ltd. |