CN103715135B - A kind of via hole and preparation method thereof, array base palte - Google Patents

Abstract

Embodiments of the present invention provide a via hole, a manufacturing method thereof, and an array substrate, which relate to the field of display technology and can improve the problems of excessive contact resistance and disconnection in the via hole technology. The via hole includes a first electrode and a metal layer sequentially formed on the substrate; the metal layer is electrically connected to the first electrode. An insulating layer and a second electrode are sequentially formed on the surface of the metal layer, and a via hole is provided on the surface of the insulating layer, and the second electrode is electrically connected to the metal layer through the via hole.

Description

Via hole, manufacturing method thereof, and array substrate

technical field

The invention relates to the field of display technology, in particular to a via hole, a manufacturing method thereof, and an array substrate.

Background technique

TFT-LCD (ThinFilmTransistorLiquidCrystalDisplay, Thin Film Transistor Liquid Crystal Display), as a flat panel display device, is more and more used in high performance display field.

The manufacturing process of the TFT-LCD display panel includes: manufacturing the array (Array) substrate and the color filter (ColorFilter) substrate, and then aligning the array substrate and the color filter substrate and forming a cell (Cell). As shown in FIG. 1 , a typical TFT array substrate includes a transparent substrate 11 and a gate 120 on the surface of the transparent substrate 11, a gate insulating layer 13, an active layer 14, a drain 121 on both sides of the active layer 14, and The source level 122 , the passivation layer 15 on the surface of the active layer 14 , the drain electrode 121 and the source level 122 , and the ITO16 (Indium tin oxide, indium tin oxide) on the surface of the passivation layer 15 .

In the manufacturing process of the array substrate, the wiring design on the array substrate is a very important content. Among them, via holes are required to realize electrical connection between film layers at different levels such as data lines, gate lines, and common electrode lines. For example, a via hole is provided on the surface of the passivation layer 15 to make the ITO 16 conduct with the drain 121 of the thin film transistor. And considering the pixel aperture ratio, the via hole can be set as a half via hole 20 as shown in FIG. 1 . Part of the ITO 16 on the surface of the half via hole 20 is lapped on the surface of the drain electrode 121, and the other part is lapped on the surface of the gate insulating layer 13 at the bottom of the half via hole 20. Using such a half via hole can increase the pixel opening. Rate.

However, the half via hole in the prior art has the following defects: on the one hand, due to the small contact area between the film layers in contact with each other at the half via hole, the contact resistance thereof increases. As shown in Figure 1, the contact area between the transparent electrode 16 and the drain electrode 121 at the half via hole 20 is reduced, so its contact resistance will increase accordingly, so that the conductivity of the TFT will decrease and the charging time of the TFT will be prolonged; On the one hand, there is a certain gap at the edge of the film layer at the half via hole. As shown in Figure 1, there is a gap at the drain 121 at the half via hole 20. When chamfering, the ITO16 located at the slope angle or the chamfer of the drain 121 will be disconnected, so that the drain 121 and the ITO16 cannot be connected. Thus, the performance of the display device is affected and the product quality is reduced. Of course, the above problems also exist in other types of vias.

Contents of the invention

Embodiments of the present invention provide a via hole, a manufacturing method thereof, and an array substrate. It can improve the problem of excessive contact resistance and open circuit in the via hole technology.

In order to achieve the above object, embodiments of the present invention adopt the following technical solutions:

An aspect of the embodiments of the present invention provides a method for manufacturing a via, including:

forming a pattern of the first electrode on the substrate through a patterning process;

A metal layer is formed on the surface of the substrate on which the first electrode pattern is formed; the metal layer is electrically connected to the pattern of the first electrode;

forming an insulating layer on the surface of the substrate on which the metal layer is formed;

forming via holes on the surface of the insulating layer through a patterning process;

forming a pattern of the second electrode on the surface of the substrate formed with the via hole through a patterning process;

Wherein, the second electrode is electrically connected to the metal layer through the via hole.

Another aspect of the embodiments of the present invention provides a via, including:

A first electrode is formed on the substrate;

A metal layer is formed on the surface of the first electrode; the metal layer is electrically connected to the first electrode;

an insulating layer is formed on the surface of the metal layer;

via holes are formed on the surface of the insulating layer;

A second electrode is formed on the surface of the via hole;

Wherein, the second electrode is electrically connected to the metal layer through the via hole.

Still another aspect of the embodiments of the present invention provides an array substrate, including any one of the above-mentioned via holes.

Embodiments of the present invention provide a via hole, a manufacturing method thereof, and an array substrate. The via hole includes a first electrode and a metal layer sequentially formed on the substrate; the metal layer is electrically connected to the first electrode. An insulating layer and a second electrode are sequentially formed on the surface of the metal layer, and a via hole is provided on the surface of the insulating layer, and the second electrode is electrically connected to the metal layer through the via hole. In this way, the depth of the via hole can be reduced, and the contact area between the electrically connected film layers can be increased, thereby improving the problems of excessive contact resistance and open circuit in the via hole technology.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only These are some embodiments of the present invention. Those skilled in the art can also obtain other drawings based on these drawings without creative work.

FIG. 1 is a schematic structural diagram of an array substrate provided by the prior art;

FIG. 2 is a flow chart of a manufacturing process of a via provided by an embodiment of the present invention;

FIG. 3 is a schematic structural diagram of a via provided by an embodiment of the present invention;

FIG. 4 is a schematic structural diagram of another via provided by an embodiment of the present invention;

FIG. 5 is a schematic structural diagram of another via provided by an embodiment of the present invention;

FIG. 6 is a schematic structural diagram of an array substrate provided by an embodiment of the present invention.

detailed description

The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

An embodiment of the present invention provides a method for manufacturing a via, as shown in FIG. 2 , including:

S101 , as shown in FIG. 3 , forming a pattern of the first electrode 21 on the substrate 10 through a patterning process.

S102 , forming a metal layer 22 on the surface of the substrate on which the pattern of the first electrode 21 is formed; the metal layer 22 is electrically connected to the pattern of the first electrode 21 .

S103 , forming an insulating layer 23 on the surface of the substrate on which the metal layer 22 is formed.

S104 , forming a via hole 24 on the surface of the insulating layer 23 through a patterning process.

S105 , forming a pattern of the second electrode 25 on the surface of the substrate on which the via hole 24 is formed by a patterning process.

Wherein, the second electrode 25 is electrically connected to the metal layer 22 through the via hole 24 .

It should be noted that the patterning process in the embodiment of the present invention may refer to a photolithography process, or include a photolithography process and an etching step, and may also include printing, inkjet and other processes for forming predetermined patterns; Photolithography process refers to the process of forming patterns by using photoresist, mask plate, exposure machine, etc., including film formation, exposure, development and other processes. The corresponding patterning process can be selected according to the structure formed in the present invention.

Embodiments of the present invention provide a via hole, a manufacturing method thereof, and an array substrate. The manufacturing method of the via hole includes sequentially forming the pattern of the first electrode and the metal layer on the substrate; the metal layer is electrically connected with the pattern of the first electrode. An insulating layer and a pattern of the second electrode are sequentially formed on the surface of the metal layer pattern, and a via hole is formed on the surface of the insulating layer pattern, and the second electrode is electrically connected to the metal layer through the via hole. In this way, the depth of the via hole can be reduced, and the contact area between the electrically connected film layers can be increased, thereby improving the problems of excessive contact resistance and open circuit in the via hole technology.

Further, as shown in FIG. 4 , the method of forming the via hole 24 on the surface of the insulating layer 23 through a patterning process may further include:

Via holes 24 are formed on the surface of the insulating layer 23 at positions corresponding to the metal layer 22 and the first electrode 21 through a patterning process.

Wherein, the second electrode 25 is electrically connected to the first electrode 21 and the metal layer 22 through the via hole 24 .

It should be noted that the above-mentioned positions on the surface of the insulating layer 23 corresponding to the metal layer 22 and the first electrode 21 specifically refer to the exposed part of the metal layer 22 at the bottom of the via hole 24 formed on the surface of the insulating layer 23 through a patterning process such as an etching process. and the first electrode 21. In this way, in the next step, the pattern of the second electrode 25 formed on the surface of the insulating layer 23 can cover the via hole 24 and be electrically connected to the metal layer 22 and the first electrode 21 through the via hole 24 .

It should be noted that the aforementioned via hole 24 is a half via hole, through which the electrical connection between the second electrode 25 and the metal layer 22 can be realized, and at the same time not only the aperture ratio can be increased, but also the metal layer 22 and the first electrode 21 can be increased. The contact area of the second electrode 25 can reduce the contact resistance between the metal layer 22 and the electrode, thereby improving the conductivity of the array substrate. In addition, although there is a gap in the metal layer 22 at the half via hole, when the slope angle at the gap is large or chamfering occurs due to the etching process, it will cause a gap at the slope angle or chamfer of the metal layer 22. When the second electrode 25 is disconnected, the metal layer 22 can still be connected to the second electrode 25 through the first electrode 21 , so as to avoid disconnection of the array substrate.

Alternatively, as shown in FIG. 5 , the method of forming the via hole 24 through a patterning process on the surface of the insulating layer 23 may also include:

A via hole 24 is formed on the surface of the insulating layer 23 at a position corresponding to the first electrode 21 through a patterning process.

Wherein, the second electrode 25 is electrically connected to the first electrode 21 through the via hole 24 .

It should be noted that the position on the surface of the insulating layer 23 corresponding to the pattern of the first electrode 21 specifically refers to the pattern of the first electrode 21 exposed at the bottom of the via hole 24 formed on the surface of the insulating layer 23 through a patterning process such as an etching process. In this way, in the next step, the pattern of the second electrode 25 formed on the surface of the insulating layer 23 can cover the via hole 24 and be electrically connected to the pattern of the first electrode 21 through the via hole 24 . In this way, not only the electrical connection between the second electrode 25 and the metal layer 22 can be realized, but also the contact area between the metal layer 22 and the first electrode 21 and the contact area between the first electrode 21 and the second electrode 25 can be reduced. Small contact resistance between electrically connected film layers. Therefore, the conductivity of the array substrate is improved. In addition, due to the first electrode 21 between the second electrode 25 and the substrate 10, the gap of the via hole 24 is reduced, thereby reducing the probability of the second electrode 25 breaking at the chamfer of the via hole, thereby improving the The quality of the array substrate.

Preferably, both the first electrode 21 and the second electrode 25 can be transparent conductive materials. For example: indium tin oxide (IndiumTinOxide, referred to as ITO).

Further, the first electrode 21 may include at least one film layer. Since the first electrode 21 and the metal layer 22 can be electrically connected, the film layer on the side of the first electrode 21 close to the metal layer 22 has a conductive function. In this way, on the premise of ensuring the electrical connection between the first electrode 21 and the metal layer 22, those skilled in the art can increase or decrease the number of film layers in the first electrode 21 according to actual needs during the production and processing process, so that the number of film layers in the first electrode 21 can be controlled. The depth of via 24.

An embodiment of the present invention provides a via, as shown in FIG. 3 , including:

A first electrode 21 is formed on the substrate 10 .

A metal layer 22 is formed on the surface of the first electrode 21 ; the metal layer 22 is electrically connected to the first electrode 21 .

An insulating layer 23 is formed on the surface of the metal layer 22 .

Via holes 24 are formed on the surface of the insulating layer 23 .

The second electrode 25 is formed on the surface of the via hole 24 .

Wherein, the second electrode 25 is electrically connected to the metal layer 22 through the via hole 24 .

An embodiment of the present invention provides a via hole. The via hole includes a first electrode and a metal layer sequentially formed on the substrate; the metal layer is electrically connected to the first electrode. A pattern of an insulating layer and a second electrode is sequentially formed on the surface of the metal layer, and a via hole is formed on the surface of the insulating layer, and the second electrode is electrically connected to the metal layer through the via hole. In this way, the depth of the via hole can be reduced, and the contact area between the electrically connected film layers can be increased, thereby improving the problems of excessive contact resistance and open circuit in the via hole technology.

Further, as shown in FIG. 4 , the positions of the via holes 24 correspond to the positions of the metal layer 22 and the first electrode 21 .

Wherein, the second electrode 25 is electrically connected to the first electrode 21 and the metal layer 22 through the via hole 24 .

It should be noted that the position of the via hole 24 corresponds to the position of the metal layer 22 and the first electrode 21, which specifically means that the bottom of the via hole 24 formed on the surface of the insulating layer 23 through a patterning process such as an etching process exposes part of the metal layer. 22 and the first electrode 21. In this way, in the next step, the pattern of the second electrode 25 formed on the surface of the insulating layer 23 can cover the via hole 24 and be electrically connected to the metal layer 22 and the first electrode 21 through the via hole 24 .

It should be noted that the aforementioned via hole 24 is a half via hole, through which the electrical connection between the second electrode 25 and the metal layer 22 can be realized, and at the same time not only the aperture ratio can be increased, but also the metal layer 22 and the first electrode 21 can be increased. The contact area of the second electrode 25 can reduce the contact resistance between the metal layer 22 and the electrode, thereby improving the conductivity of the array substrate. In addition, although there is a gap in the metal layer 22 at the half via hole, when the slope angle at the gap is large or chamfering occurs due to the etching process, it will cause a gap at the slope angle or chamfer of the metal layer 22. When the second electrode 25 is disconnected, the metal layer 22 can still be connected to the second electrode 25 through the first electrode 21 , so as to avoid disconnection of the array substrate.

Alternatively, as shown in FIG. 5 , the positions of the via holes 24 correspond to the positions of the first electrodes 21 .

Wherein, the second electrode 25 is electrically connected to the first electrode 21 through the via hole 24 .

It should be noted that the position of the via hole 24 corresponds to the position of the first electrode 21, specifically refers to the pattern in which a part of the first electrode 21 is exposed at the bottom of the via hole 24 formed on the surface of the insulating layer 23 through a patterning process such as an etching process. . In this way, in the next step, the pattern of the second electrode 25 formed on the surface of the insulating layer 23 can cover the via hole 24 and be electrically connected to the pattern of the first electrode 21 through the via hole 24 . In this way, not only the electrical connection between the second electrode 25 and the metal layer 22 can be realized, but also the contact area between the metal layer 22 and the first electrode 21 and the contact area between the first electrode 21 and the second electrode 25 can be reduced. Small contact resistance between electrically connected film layers. Therefore, the conductivity of the array substrate is improved. In addition, due to the first electrode 21 between the second electrode 25 and the substrate 10, the gap of the via hole 24 is reduced, thereby reducing the probability of the second electrode 25 breaking at the chamfer of the via hole, thereby improving the The quality of the array substrate.

An embodiment of the present invention provides an array substrate, including any one of the aforementioned via holes. It has the same beneficial effects as the via holes provided in the foregoing embodiments of the present invention, and since the via holes have been described in detail in the foregoing embodiments, details will not be repeated here.

An embodiment of the present invention provides an array substrate. The array substrate includes a via hole, and the via hole includes a first electrode and a metal layer sequentially formed on the substrate; the metal layer is electrically connected to the first electrode. An insulating layer and a second electrode are sequentially formed on the surface of the metal layer, and a via hole is provided on the surface of the insulating layer, and the second electrode is electrically connected to the metal layer through the via hole. In this way, the depth of the via hole can be reduced, and the contact area between the electrically connected film layers can be increased, thereby improving the problems of excessive contact resistance and open circuit in the via hole technology.

Further, as shown in FIG. 6, the above-mentioned array substrate further includes:

A gate 120 is formed on the surface of the transparent substrate 11 .

A gate insulating layer 13 and an active layer 14 are sequentially formed on the surface of the gate 120 .

The first electrode 21 is formed on the surface of the gate insulating layer 13 .

An active level 122 and a drain 121 are formed on both sides of the surface of the active layer 14 .

A passivation layer 15 is covered on the surface of the substrate formed with the above pattern.

A via hole 24 is provided on the surface of the passivation layer 15 at a position corresponding to the first electrode 21 and the drain electrode 121 .

A second electrode 25 is formed on the surface of the substrate provided with the via hole 24 .

Wherein, the via hole 24 is a half via hole, and the second electrode 25 is electrically connected to the first electrode 21 and the drain electrode 121 through the half via hole.

On the aforementioned array substrate, the TFT drain 121 at the half via hole is located between the first electrode 21 and the second electrode 25 , and the TFT drain 121 exposed in the half via hole is surrounded by the electrodes. In this way, while increasing the aperture ratio, the contact area between the TFT drain 121 and the first and second electrodes can be increased, thereby reducing the contact resistance between the electrically connected film layers and improving the conductivity of the TFT. . In addition, since there is a gap in the drain 121 at the half via hole, when the slope angle at the gap is large or chamfering occurs due to the etching process, the first hole at the slope angle or chamfer of the drain 121 will be caused. When the second electrode 25 is disconnected, the drain 121 can still be connected to the second electrode 25 through the first electrode 21, so as to ensure that the TFT can work normally.

The above is only a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Anyone skilled in the art can easily think of changes or substitutions within the technical scope disclosed in the present invention. Should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be determined by the protection scope of the claims.

Claims (9)

1. A method for making a via, comprising: forming a pattern of the first electrode for reducing the depth of the via hole on the substrate through a patterning process; A metal layer is formed on the surface of the substrate on which the first electrode pattern is formed; the metal layer is electrically connected to the pattern of the first electrode; forming an insulating layer on the surface of the substrate on which the metal layer is formed; forming via holes on the surface of the insulating layer through a patterning process; forming a pattern of the second electrode on the surface of the substrate formed with the via hole through a patterning process; Wherein, the second electrode is electrically connected to the metal layer through the via hole. 2. The manufacturing method according to claim 1, wherein the method of forming vias on the surface of the insulating layer through a patterning process further comprises: forming via holes on the surface of the insulating layer corresponding to the metal layer and the first electrode through a patterning process; Wherein, the second electrode is electrically connected to the first electrode and the metal layer through the via hole. 3. The manufacturing method according to claim 1, wherein the method of forming vias on the surface of the insulating layer through a patterning process further comprises: forming the via hole at a position corresponding to the first electrode on the surface of the insulating layer through a patterning process; Wherein, the second electrode is electrically connected to the first electrode through the via hole. 4. The manufacturing method according to any one of claims 1-3, wherein the first electrode and the second electrode are both transparent conductive materials. 5. The manufacturing method according to claim 4, wherein the first electrode layer comprises at least one film layer. 6. A via, characterized in that it comprises: A first electrode for reducing the depth of the via hole is formed on the substrate; A metal layer is formed on the surface of the first electrode; the metal layer is electrically connected to the first electrode; an insulating layer is formed on the surface of the metal layer; via holes are formed on the surface of the insulating layer; A second electrode is formed on the surface of the via hole; Wherein, the position of the via hole corresponds to the position of the metal layer and the first electrode; the second electrode is electrically connected to the first electrode and the metal layer through the via hole. 7. A via, characterized in that it comprises: A first electrode for reducing the depth of the via hole is formed on the substrate; A metal layer is formed on the surface of the first electrode; the metal layer is electrically connected to the first electrode; an insulating layer is formed on the surface of the metal layer; via holes are formed on the surface of the insulating layer; A second electrode is formed on the surface of the via hole; Wherein, the position of the via hole corresponds to the position of the first electrode; the second electrode is electrically connected to the first electrode through the via hole. 8. An array substrate, comprising: the via hole according to any one of claims 6-7. 9. The array substrate according to claim 8, further comprising: A gate is formed on the surface of the transparent substrate; A gate insulating layer and an active layer are sequentially formed on the surface of the gate; a first electrode is formed on the surface of the gate insulating layer; A source electrode and a drain electrode are formed on both sides of the surface of the active layer; A passivation layer is covered on the surface of the substrate formed with the above pattern; The via hole is provided at a position corresponding to the first electrode and the drain on the surface of the passivation layer; A second electrode is formed on the surface of the substrate provided with the via hole; Wherein, the second electrode is electrically connected to the first electrode and the drain through the via hole.