CN103715201B - A kind of array base palte and manufacture method, GOA unit and display device - Google Patents

Abstract

The embodiment of the present invention provides a kind of array base palte and manufacture method, GOA unit and display device, relates to Display Technique field。Array base palte includes being formed at the grid of substrate surface, gate insulation layer, active layer and source and drain metal level, described source and drain metal level is for forming source-drain electrode and the channel region of TFT, described array base palte includes a multiple TFT and multiple 2nd TFT, the length of the length of the channel region of the described TFT channel region less than described 2nd TFT。The open circuit that such a array base palte can be avoided TFT channel region in GOA unit to disconnect and cause is bad。

Description

A kind of array substrate and its manufacturing method, GOA unit and display device

technical field

The present invention relates to the field of display technology, in particular to an array substrate and a manufacturing method thereof, a GOA unit and a display device.

Background technique

In order to improve the display effect of the display device, more and more people begin to pay attention to the narrow frame design of the display device. In the prior art, the production of the narrow frame display is usually realized by compressing the process margin to the limit. A very important technology is the realization of the mass production of the array substrate row drive (GateDriveronArray, GOA for short). Use GOA technology to integrate the gate switch circuit on the array substrate of the display panel to form a scan drive for the display panel, so that the gate drive integrated circuit part can be saved, which can not only reduce the product cost in terms of material cost and manufacturing process , and the display panel can achieve a beautiful design with symmetrical sides and narrow borders.

TFTs (ThinFilmTransistor, Thin Film Field Effect Transistor) of various sizes and shapes are usually formed in the GOA unit, so that in the process of forming the source and drain of the TFT through the patterning process, the half-tone mask used in the ashing process of the source and drain electrodes The light transmittance of the film plate (HalfToneMask, HTM) needs to change according to the size of the TFT. The change of the light transmittance of the HTM will cause the thickness of the photoresist at the corresponding position of the channel of different TFTs in the ashing process to be inconsistent, which will eventually lead to Poor disconnection of channels in TFTs with relatively weak photoresist after subsequent etching occurs.

In the GOA unit, there are usually two kinds of TFTs located in different regions. The sizes of the two kinds of TFTs are different. The cross-sectional views of the two kinds of TFTs can be shown in Figure 1 and Figure 2 respectively, and the structures and formation processes of the two kinds of TFTs are the same. , all including a gate 2, a gate insulating layer (not shown in the figure), an active layer 3 and a source-drain metal layer 4 sequentially formed on the surface of the transparent substrate 1. In order to form a channel, the surface of the source-drain metal layer is formed with For the photoresist layer 5, after exposure and development using HTM, the photoresist layer 5 above the source-drain metal layer 4 corresponding to the position of the TFT channel has different thicknesses of the photoresist. It can be seen that the It is shown that the thickness of the photoresist layer 5 corresponding to the channel region in the TFT structure is h1, and the thickness of the photoresist layer 5 corresponding to the channel region in the TFT structure shown in FIG. 2 is h2, h1<h2. Due to the small thickness of h1, in the process of further forming the channel through the patterning process, unnecessary etching may occur on the active layer 3, which will cause the channel region in the TFT to be disconnected and cause defects, so that the TFT cannot realize the corresponding function.

Contents of the invention

Embodiments of the present invention provide an array substrate and a manufacturing method thereof, a GOA unit, and a display device, which can avoid poor disconnection caused by disconnection of TFT channel regions in the GOA unit.

An aspect of the embodiments of the present invention provides an array substrate, including a gate formed on the surface of the substrate, a gate insulating layer, an active layer, and a source-drain metal layer, and the source-drain metal layer is used to form the source-drain of a TFT and a channel region, the array substrate includes a plurality of first TFTs and a plurality of second TFTs, the length of the channel region of the first TFT is smaller than the length of the channel region of the second TFT.

Specifically, before the source/drain and channel regions of the TFT are formed, a photoresist layer is formed on the surface of the source/drain metal layer.

Wherein, the thickness of the photoresist layer corresponding to the channel region of the TFT is smaller than the thickness corresponding to the source and drain regions of the TFT.

The thickness of the photoresist layer corresponding to the channel region of the first TFT is equal to the thickness corresponding to the channel region of the second TFT.

In an embodiment of the present invention, the photoresist layer is formed by exposing and developing with a gray tone mask.

Wherein, the gray-tone mask plate includes a gray-tone film layer, the gray-tone film layer includes a plurality of first regions and a plurality of second regions, and the first regions correspond to the channel regions of the first TFT, The second region corresponds to the channel region of the second TFT.

The thickness of the gray tone film layer located in the first area is greater than the thickness of the gray tone film layer located in the second area.

Specifically, the difference between the thickness of the gray tone film layer located in the first area and the thickness of the gray tone film layer located in the second area is

The length of the channel region of the first TFT is 4.0-5.0 μm.

The length of the channel region of the second TFT is 5.0-6.0 μm.

An embodiment of the present invention also provides an array substrate, including a plurality of first TFTs and second TFTs as described above.

On the other hand, an embodiment of the present invention further provides a display device, which includes the above-mentioned array substrate or includes the above-mentioned GOA unit.

In addition, an embodiment of the present invention also provides a method for manufacturing an array substrate, including:

A gate, a gate insulation layer, an active layer, and a source-drain metal layer are sequentially formed on the surface of the substrate.

On the surface of the substrate on which the source-drain metal layer is formed, source-drain electrodes and channel regions of a plurality of first TFTs and second TFTs are formed through patterning process, and the length of the channel regions of the first TFTs is shorter than the length of the first TFT. The length of the channel region of the second TFT.

In the array substrate and its manufacturing method, GOA unit and display device provided by the embodiments of the present invention, in the process of forming the TFT channel, when the thickness of the photoresist layer in the first TFT channel region is smaller than that of the second TFT channel region When the thickness of the photoresist layer is lower, by reducing the length of the channel region of the first TFT, the exposure amount of the photoresist layer of the first TFT channel region will be reduced correspondingly, thereby the first TFT channel region can be effectively realized. There is no obvious step difference between the thickness of the photoresist layer and the thickness of the photoresist layer in the channel region of the second TFT. Through such a compensation method, in the process of using HTM to form the TFT channel region, when TFTs of different sizes or shapes form the channel region, the thickness of the photoresist corresponding to the channel region will not be affected by the HTM. The light transmittance is larger and becomes thinner, thereby avoiding the disconnection of the channel region caused by the excessive etching thickness of the TFT in the GOA unit when the channel region is formed, thereby avoiding the poor disconnection of the TFT channel region , significantly improving the quality of the product.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only These are some embodiments of the present invention. Those skilled in the art can also obtain other drawings based on these drawings without creative work.

FIG. 1 is a schematic structural diagram of an array substrate in the prior art;

2 is a schematic structural view of another array substrate in the prior art;

3 is a schematic diagram of the formation structure of a first TFT in an array substrate provided by an embodiment of the present invention;

4 is a schematic diagram of the formation structure of a second TFT in an array substrate provided by an embodiment of the present invention;

5 is a schematic structural diagram of a gray-tone mask forming the array substrate provided by the embodiment of the present invention;

6 is a schematic diagram of the relationship between the length L of the channel region of the TFT and the thickness T of the gray tone film layer 50 in an embodiment of the present invention;

FIG. 7 is a schematic flowchart of a method for manufacturing an array substrate provided by an embodiment of the present invention;

FIG. 8 is a schematic flowchart of a method for forming a channel region of a TFT.

detailed description

The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

The array substrate provided by the embodiment of the present invention, as shown in FIG. 3 and FIG. 4 , includes a gate 31 formed on the surface of the substrate 30, a gate insulating layer (not shown in the figure), an active layer 32, and a source-drain metal layer 33 , the source-drain metal layer 33 is used to form the source-drain and channel regions of TFTs, wherein the array substrate includes a plurality of first TFTs and a plurality of second TFTs, the structure of the first TFTs may be as shown in FIG. 3 , the first The structure of the two TFTs can be as shown in FIG. 4 , wherein the length L1 of the channel region of the first TFT is smaller than the length L2 of the channel region of the second TFT.

Wherein, the substrate 30 may specifically be a transparent substrate made of materials such as glass or transparent resin, and the gate 31 , the gate insulating layer 32 and the active layer may be sequentially formed on the surface of the transparent substrate 30 through a patterning process. The source and drain metal layer 33 can be processed by one patterning process to respectively form the source and drain and the channel region of the TFT, wherein the source and drain metal layer 34 is disconnected at the position corresponding to the active layer, thereby forming the channel region of the TFT.

It should be noted that both the first TFT and the second TFT may be located in the GOA unit, and the size or shape of the first TFT and the second TFT are different. In the embodiment of the present invention, the description is made by taking the size of the first TFT smaller than that of the second TFT as an example. When the size of the first TFT is smaller than the size of the second TFT, the first TFT usually has a If the etch thickness is too large, the disconnection of the channel region may easily occur. Certainly, this embodiment of the present invention is only an example here, rather than limiting the present invention. In this embodiment of the present invention, the first TFT may include a groove that appears due to an excessively large etching thickness when forming the channel region. Such a type of TFT in which the track region is disconnected.

In the array substrate provided by the embodiment of the present invention, in the process of forming the TFT channel, when the thickness of the photoresist layer in the first TFT channel region is smaller than the thickness of the photoresist layer in the second TFT channel region, by reducing The length of the channel region of the first TFT will reduce the exposure amount of the photoresist layer of the first TFT channel region accordingly, thereby can effectively realize the thickness of the photoresist layer of the first TFT channel region and the thickness of the second TFT There is no obvious step difference between the thicknesses of the photoresist layer in the channel region. Through such a compensation method, in the process of using HTM to form the TFT channel region, when TFTs of different sizes or shapes form the channel region, the thickness of the photoresist corresponding to the channel region will not be affected by the HTM. The light transmittance is larger and becomes thinner, thereby avoiding the disconnection of the channel region caused by the excessive etching thickness of the TFT in the GOA unit when the channel region is formed, thereby avoiding the poor disconnection of the TFT channel region , significantly improving the quality of the product.

Further, as shown in FIG. 3 or FIG. 4 , before the source/drain and channel regions of the TFT are formed, a photoresist layer 34 may be formed on the surface of the source/drain metal layer 33 .

Wherein, the thickness of the photoresist layer 34 corresponding to the channel region of the TFT is smaller than the thickness corresponding to the source and drain regions of the TFT.

Preferably, in the array substrate structure shown in FIG. 3 and FIG. 4 , the thickness t1 of the photoresist layer 34 corresponding to the channel region of the first TFT may be equal to the thickness t2 corresponding to the channel region of the second TFT. In this way, it can be further ensured that the channel region of the first TFT will not be disconnected due to excessive etching thickness when the channel region is formed, thereby avoiding poor disconnection of the channel region of the TFT.

Further, the photoresist layer 34 can be formed by exposing and developing with a gray tone mask.

Wherein, the structure of the gray-tone mask plate can be as shown in FIG. 5 , including a gray-tone film layer 50, wherein the gray-tone film layer 50 includes a plurality of first regions 51 and a plurality of second regions 52, and the first region 51 corresponds to the channel region of the first TFT, and the second region 52 corresponds to the channel region of the second TFT.

The thickness T1 of the gray tone film layer 50 located in the first area 51 is greater than the thickness T2 of the gray tone film layer 50 located in the second area 52 .

It should be noted that, in the manufacturing process of TFT, the shorter the length of the channel region of TFT is, the exposure amount of the photoresist layer in the channel region of TFT should be correspondingly reduced when patterning process is performed to form the channel region. When a gray-tone mask is used, as the thickness of the gray-tone film increases, the light transmittance of the mask will gradually decrease, and correspondingly, the exposure amount of the photoresist layer in the TFT channel region will also decrease.

Specifically, when other external conditions remain unchanged, the relationship between the length L of the channel region of the TFT and the thickness T of the gray tone film layer 50 can be shown in Figure 6, where the unit of the length L of the channel region of the TFT is is μm, and the unit of the thickness T of the gray tone film layer 50 is It can be seen that as the length L of the TFT channel region increases, the required light transmittance also increases, and the thickness T of the corresponding gray tone film layer 50 decreases accordingly to achieve an increase in light transmittance. When the TFT When the length L of the channel region increases to more than 6 μm, the thickness T of the gray tone film layer 50 will no longer decrease with the increase of the length L of the TFT channel region.

As a preferred embodiment, the difference between the thickness T1 of the gray tone film layer 50 located in the first region 51 and the thickness T2 of the gray tone film layer 50 located in the second region 52 can be Correspondingly, the length L1 of the channel region of the first TFT may be 4.0˜5.0 μm, and the length L2 of the channel region of the second TFT may be 5.0˜6.0 μm. For example, L1 can be specifically selected as 4.5 μm, and L2 can be specifically selected as 5.5 μm. The channel length design of such a size TFT can effectively reduce the exposure amount of the photoresist layer in the channel region of the first TFT, so that the thickness of the photoresist layer in the channel region of the first TFT can be effectively realized to be equal to the thickness of the photoresist layer in the channel region of the first TFT. There is no obvious step difference between the thicknesses of the photoresist layers in the channel regions of the two TFTs.

Through such a compensation method, in the process of using HTM to form the TFT channel region, when TFTs of different sizes or shapes form the channel region, the thickness of the photoresist corresponding to the channel region will not be affected by the HTM. The light transmittance is larger and becomes thinner, thereby avoiding the disconnection of the channel region caused by the excessive etching thickness of the TFT in the GOA unit when the channel region is formed, thereby avoiding the poor disconnection of the TFT channel region , significantly improving the quality of the product.

It should be noted that the above-mentioned TFTs are all described by taking the bottom gate structure as an example, and the array substrate with such a structure provided by the embodiment of the present invention can also adopt the TFT with the top gate structure. The difference from TFT with bottom gate structure is that in TFT with top gate structure, the source and drain metal layer, active layer, gate insulating layer and gate are sequentially formed on the surface of the substrate, and the source and drain metal layer is used to form The source and drain of the TFT and the channel region of the TFT. In order to avoid disconnection of the channel region caused by the excessive etching thickness of the TFT when forming the channel region, the length L1 of the channel region of the first TFT can also be used to be smaller than the length L2 of the channel region of the second TFT. kind of design.

The GOA unit provided by the embodiment of the present invention includes a plurality of first TFTs and second TFTs as described above.

In the GOA unit of such a structure, in the process of forming the TFT channel, when the thickness of the photoresist layer in the first TFT channel region is smaller than the thickness of the photoresist layer in the second TFT channel region, by reducing the thickness of the photoresist layer in the second TFT channel region, The length of the channel region of a TFT will reduce the exposure amount of the photoresist layer of the first TFT channel region accordingly, thereby can effectively realize that the thickness of the photoresist layer of the first TFT channel region is the same as that of the second TFT channel region. There is no obvious step difference between the thickness of the photoresist layer in the track area. Through such a compensation method, in the process of using HTM to form the TFT channel region, when TFTs of different sizes or shapes form the channel region, the thickness of the photoresist corresponding to the channel region will not be affected by the HTM. The light transmittance is larger and becomes thinner, thereby avoiding the disconnection of the channel region caused by the excessive etching thickness of the TFT in the GOA unit when the channel region is formed, thereby avoiding the poor disconnection of the TFT channel region , significantly improving the quality of the product.

In addition, an embodiment of the present invention also provides a display device, specifically, the display device may include the above-mentioned array substrate or include the above-mentioned GOA unit.

It should be noted that the display device provided by the present invention can be any product or component with display function such as liquid crystal panel, electronic paper, OLED panel, liquid crystal TV, liquid crystal display, digital photo frame, mobile phone, and tablet computer.

Since the structure of the array substrate or the GOA unit has been described in detail in the foregoing embodiments, it will not be repeated here.

The method for manufacturing an array substrate provided in an embodiment of the present invention, as shown in FIG. 7 , includes:

S701 , sequentially forming a gate, a gate insulating layer, an active layer, and a source-drain metal layer on a surface of a substrate.

S702. Form the source, drain and channel regions of a plurality of first TFTs and second TFTs through a patterning process on the surface of the substrate on which the source and drain metal layers are formed. The length of the channel regions of the first TFTs is shorter than that of the second TFTs. The length of the channel region.

It should be noted that both the first TFT and the second TFT may be located in the GOA unit, and the size or shape of the first TFT and the second TFT are different. In the embodiment of the present invention, the description is made by taking the size of the first TFT smaller than that of the second TFT as an example. When the size of the first TFT is smaller than the size of the second TFT, the first TFT usually has a If the etch thickness is too large, the disconnection of the channel region may easily occur. Certainly, this embodiment of the present invention is only an example here, rather than limiting the present invention. In this embodiment of the present invention, the first TFT may include a groove that appears due to an excessively large etching thickness when forming the channel region. Such a type of TFT in which the track region is disconnected.

In the method for manufacturing an array substrate provided by an embodiment of the present invention, in the process of forming the TFT channel, when the thickness of the photoresist layer in the first TFT channel region is smaller than the thickness of the photoresist layer in the second TFT channel region, By reducing the length of the channel region of the first TFT, the exposure amount of the photoresist layer in the channel region of the first TFT will be reduced correspondingly, so that the thickness of the photoresist layer in the channel region of the first TFT can be effectively realized to be equal to the thickness of the first TFT channel region. There is no obvious step difference between the thicknesses of the photoresist layers in the channel regions of the two TFTs. Through such a compensation method, in the process of using HTM to form the TFT channel region, when TFTs of different sizes or shapes form the channel region, the thickness of the photoresist corresponding to the channel region will not be affected by the HTM. The light transmittance is larger and becomes thinner, thereby avoiding the disconnection of the channel region caused by the excessive etching thickness of the TFT in the GOA unit when the channel region is formed, thereby avoiding the poor disconnection of the TFT channel region , significantly improving the quality of the product.

Further, as shown in FIG. 8 , the process of forming the source, drain and channel regions of a plurality of first TFTs and second TFTs through patterning process on the surface of the substrate on which the source and drain metal layers are formed may specifically include:

S801, forming a photoresist layer on the surface of the source-drain metal layer.

S802. Exposing and developing the photoresist layer by using a gray tone mask, so that the thickness of the photoresist layer corresponding to the channel region of the TFT is smaller than the thickness of the source and drain regions of the TFT, and the photoresist layer corresponds to the first The thickness of the channel region of the TFT is equal to the thickness of the channel region of the corresponding second TFT.

Wherein, the structure of the gray-tone mask plate can be as shown in FIG. 5 , including a gray-tone film layer 50, wherein the gray-tone film layer 50 includes a plurality of first regions 51 and a plurality of second regions 52, and the first region 51 corresponds to the channel region of the first TFT, and the second region 52 corresponds to the channel region of the second TFT. The thickness T1 of the gray tone film layer 50 located in the first area 51 is greater than the thickness T2 of the gray tone film layer 50 located in the second area 52 .

S803 , etching away the photoresist layer corresponding to the channel region of the TFT, and peeling off the remaining photoresist layer to form source, drain and channel regions of a plurality of first TFTs and second TFTs.

As a preferred embodiment, the thickness difference between the thickness T1 of the gray tone film layer located in the first area and the thickness T1 of the gray tone film layer located in the second area can be Correspondingly, the length of the channel region of the first TFT may be 4.0˜5.0 μm, and the length of the channel region of the second TFT may be 5.0˜6.0 μm. For example, the length of the channel region of the first TFT can be specifically selected as 4.5 μm, and the length of the channel region of the second TFT can be specifically selected as 5.5 μm. The channel length design of such a size TFT can effectively reduce the exposure amount of the photoresist layer in the channel region of the first TFT, so that the thickness of the photoresist layer in the channel region of the first TFT can be effectively realized to be equal to the thickness of the photoresist layer in the channel region of the first TFT. There is no obvious step difference between the thicknesses of the photoresist layers in the channel regions of the two TFTs.

Through such a compensation method, in the process of using HTM to form the TFT channel region, when TFTs of different sizes or shapes form the channel region, the thickness of the photoresist corresponding to the channel region will not be affected by the HTM. The light transmittance is larger and becomes thinner, thereby avoiding the disconnection of the channel region caused by the excessive etching thickness of the TFT in the GOA unit when the channel region is formed, thereby avoiding the poor disconnection of the TFT channel region , significantly improving the quality of the product.

The above is only a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Anyone skilled in the art can easily think of changes or substitutions within the technical scope disclosed in the present invention. Should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be determined by the protection scope of the claims.

Claims (9)

1. an array base palte, including being formed at the grid of substrate surface, gate insulation layer, active layer and source and drain metal level, described source and drain metal level is for forming source-drain electrode and the channel region of TFT, it is characterized in that, described array base palte includes a multiple TFT and multiple 2nd TFT, the length of the length of the channel region of the described TFT channel region less than described 2nd TFT；Before the source-drain electrode forming TFT and channel region, the surface of described source and drain metal level is also formed with photoresist layer；Described photoresist layer adopts gray tone mask plate exposure imaging to be formed；

Described gray tone mask plate includes gray tone rete, and described gray tone rete includes multiple first area and multiple second area, the channel region of the corresponding described TFT in described first area, the channel region of corresponding described 2nd TFT of described second area；

It is positioned at the thickness of gray tone rete of described first area more than the thickness of the gray tone rete being positioned at described second area。

2. array base palte according to claim 1, it is characterised in that

The thickness of the thickness of the channel region of the described photoresist layer correspondence TFT source drain region less than corresponding TFT；

The thickness of the channel region of the corresponding described TFT of described photoresist layer is equal with the thickness of the channel region of corresponding described 2nd TFT。

3. array base palte according to claim 1, it is characterised in that the thickness of gray tone rete being positioned at described first area with the thickness difference of the gray tone rete being positioned at described second area is

4. according to the arbitrary described array base palte of claim 1-3, it is characterised in that

The length of the channel region of a described TFT is 4.0～5.0 μm；

The length of the channel region of described 2nd TFT is 5.0～6.0 μm。

5. a GOA unit, it is characterised in that include multiple as arbitrary in claim 1-4 as described in TFT and the two TFT。

6. a display device, it is characterised in that include as arbitrary in claim 1-4 as described in array base palte or include GOA unit as claimed in claim 5。

7. the manufacture method of an array base palte, it is characterised in that including:

Grid, gate insulation layer, active layer and source and drain metal level is sequentially formed on the surface of substrate；

It is being formed with the surface of substrate of described source and drain metal level and is being formed by patterning processes process source-drain electrode and the channel region of multiple TFT and the two TFT, the length of the length of the channel region of the described TFT channel region less than described 2nd TFT；Photoresist layer is formed on the surface of described source and drain metal level；

Adopt gray tone mask plate that described photoresist layer is exposed development, so that the thickness of the source drain region that the thickness of the channel region of described photoresist layer correspondence TFT is less than corresponding TFT, and the thickness of the channel region of the corresponding described TFT of described photoresist layer is equal with the thickness of the channel region of corresponding described 2nd TFT；

Etch away the described photoresist layer that the channel region of TFT is corresponding, peel off remaining photoresist layer, form source-drain electrode and the channel region of multiple TFT and the two TFT。

8. the manufacture method of array base palte according to claim 7, it is characterised in that the thickness of the gray tone rete of the channel region of a described TFT with the thickness difference of the gray tone rete of the channel region being positioned at described 2nd TFT is

9. the manufacture method according to the arbitrary described array base palte of claim 7-8, it is characterised in that

The length of the channel region of a described TFT is 4.0～5.0 μm；

The length of the channel region of described 2nd TFT is 5.0～6.0 μm。