CN103730150B

CN103730150B - A kind of level shift circuit

Info

Publication number: CN103730150B
Application number: CN201410005964.5A
Authority: CN
Inventors: 黄明永; 杨光军
Original assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Current assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date: 2014-01-07
Filing date: 2014-01-07
Publication date: 2016-08-17
Anticipated expiration: 2034-01-07
Also published as: CN103730150A

Abstract

The present invention relates to a kind of level shift circuit.Described level shift circuit includes: electric current provides unit, is adapted to provide for controlling electric current；Electrical level shift units, including being suitable to input the signal input node of the first level signal and be suitable to export the signal output node of second electrical level signal；Described electrical level shift units provides unit to be connected with described electric current, is suitable to input described control electric current, to control the level conversion speed of described output node.The present invention can control level shift circuit level conversion speed under different high level.

Description

Level shift circuit

Technical Field

The present invention relates to semiconductor circuits, and more particularly, to a level shift circuit.

Background

In the information age, information storage is one of the most important technical contents in information technology. Memories such as DRAM, EEPROM, flash memory, etc. are increasingly used.

To achieve operations such as reading and programming of information, the memory needs to be switched between different levels to obtain the required operating voltages: for example, in a 90nm high speed Flash memory, in different operation modes, a column decoder (also called a Y decoder) needs to provide different bit line voltages to a target memory cell, for example, in a read operation, the column decoder needs to apply a read voltage of 3V to a selected bit line, and in a program operation, the column decoder needs to apply a programming voltage of 5V or more to the selected bit line to select the bit line, and in this case, the bit line voltage is generally 8V. The column decoder obtains a desired operation voltage through a level shift circuit.

A level shifting circuit as shown in fig. 1, comprising: inverter INV, PMOS transistors P1 and P2, NMOS transistors N1 and N2; wherein,

the input signal Data is input into a grid electrode of an NMOS tube N1 and an input end of an inverter INV, and the output of the inverter INV is connected with a grid electrode of an NMOS tube N2;

the source electrode of the NMOS tube N1 is grounded GND, the drain electrode is connected with the drain electrode of the PMOS tube P1 and the grid electrode of the PMOS tube P2, and the source electrode of the PMOS tube P1 is connected with the power supply voltage VDD;

the source of the NMOS transistor N2 is grounded GND, the drain is connected with the drain of the PMOS transistor P2 and the gate of the PMOS transistor P1, and the source of the PMOS transistor P2 is connected with the power supply voltage VDD.

Continuing to refer to fig. 1, when the input signal Data is in a high level state, the node V11 is in a low level, the node V12 is in a high level, the NMOS transistor N1 is turned on, the NMOS transistor N2 is turned off, the PMOS transistor P2 is turned on, and the PMOS transistor P1 is turned off, when the input signal Data is turned from a high level to a low level, the NMOS transistor N1 is turned off, and the NMOS transistor N2 is turned on, at this time, because the node V11 is still kept in a low level, the node V12 is still kept in a high level, the NMOS transistor N2 and the PMOS transistor P2 are in a conducting state and pass through current flows, so that the node V12 is lowered to a low level; when the node 12 is low, the PMOS transistor P1 is turned on and generates a through current, raising the node V11 to high. In the above process, in order to lower the node V12 to a low level, the transistor size of the NMOS transistor N2 needs to be increased; in order to raise the node V11 to a high level, the transistor size of the PMOS transistor P1 needs to be increased.

Similarly, when the input signal Data is changed from low level to high level, the transistor size of the NMOS transistor N1 needs to be increased in order to lower the node V11 to low level; in order to raise the node V12 to a high level, the transistor size of the PMOS transistor P2 needs to be increased.

However, the high level of the level shift circuit is different corresponding to different operation voltages required for the memory. For the high level voltage output after level shifting, in some operation modes of the memory, for example, during a programming operation, if the slew rate is too fast, a high voltage may be applied to other devices of the memory, such as a column decoder or other memory cells, and the memory device may be damaged. The level shift rate of the level shift circuit in the prior art is determined by the transistor characteristics, and for the level shift circuit shown in fig. 1, the through current obtained according to the transistor size can make the level shift circuit switch between levels quickly, but the level shift rate of the level shift circuit cannot be controlled further.

Disclosure of Invention

The technical problem solved by the technical scheme of the invention is as follows: how to control the level shift rate of the level shifting circuit.

In order to solve the above technical problem, a technical solution of the present invention provides a level shift circuit, including:

a current providing unit adapted to provide a control current;

a level shift unit including a signal input node adapted to input a first level signal and a signal output node adapted to output a second level signal; the level shifting unit is connected with the current providing unit and is suitable for inputting the control current so as to control the level conversion rate of the output node.

Optionally, the level shift unit further comprises a first power supply node adapted to be connected to a first power supply and a second power supply node adapted to be connected to a second power supply; the level value of the second level signal is converted between the level value of the first power source and the level value of the second power source.

Optionally, the first power supply is adapted to provide a first level and a second level;

the current providing unit is adapted to provide the control current when the first power supply provides the first level and stop providing the control current when the first power supply provides the second level.

Optionally, the current providing unit is a first current providing unit or a second current providing unit, or the current providing unit includes a first current providing unit and a second current providing unit;

the first current providing unit is adapted to provide a first control current to the first power supply node, and the second current providing unit is adapted to provide a second control current to the second power supply node.

Optionally, the first current providing unit includes a PMOS current mirror formed by an input PMOS transistor and a mirror PMOS transistor, a source of the mirror PMOS transistor is connected to the first power supply, and a drain of the mirror PMOS transistor is connected to the first power supply node;

the second current providing unit comprises an NMOS current mirror formed by an input NMOS tube and a mirror NMOS tube, the source electrode of the mirror NMOS tube is connected with the second power supply, and the drain electrode of the mirror NMOS tube is connected with the second power supply node.

Optionally, the first current providing unit further includes a control NMOS transistor, a drain of which is connected to a gate of the mirror PMOS transistor, the gate inputs a first control signal, and the source inputs a level suitable for turning on the mirror PMOS transistor;

the second current providing unit further comprises a control PMOS tube, the drain electrode of the control PMOS tube is connected with the grid electrode of the mirror image NMOS tube, a second control signal is input to the grid electrode, and the source electrode of the control PMOS tube is input with a level suitable for enabling the mirror image NMOS tube to be conducted.

Optionally, the first power supply provides a first level and a second level;

the first control signal is suitable for controlling the control NMOS tube to be switched off when the first power supply provides a first level and controlling the control NMOS tube to be switched on when the first power supply provides a second level;

the second control signal is suitable for controlling the control PMOS tube to be switched off when the first power supply provides a first level and controlling the control PMOS tube to be switched on when the first power supply provides a second level.

Optionally, the current providing unit includes a first current providing unit and a second current providing unit, and further includes: and the current source unit is connected between the input PMOS tube and the input NMOS tube.

Optionally, the first power supply provides a first level and a second level; the current supply unit further includes: the control tube is connected between the current source unit and the input PMOS tube or between the current source unit and the input NMOS tube;

and a third control signal is input to the grid electrode of the control tube, and is suitable for controlling the control tube to be switched on when the first power supply provides a first level and to be switched off when the first power supply provides a second level.

Optionally, the signal output node includes a first output node and a second output node, and the level shift unit further includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, and a phase inverter;

the drain electrode of the first PMOS tube, the drain electrode of the first NMOS tube and the grid electrode of the second PMOS tube are connected with the first output node;

the drain electrode of the second PMOS tube, the drain electrode of the second NMOS tube and the grid electrode of the first PMOS tube are connected with the second output node;

the signal input node is connected with the grid electrode of the first NMOS tube through the phase inverter and is connected with the grid electrode of the second NMOS tube;

the source electrode of the first PMOS tube and the source electrode of the second PMOS tube are connected with the first power supply node;

and the source electrode of the first NMOS tube and the source electrode of the second NMOS tube are connected with the second power supply node.

The technical scheme of the invention at least comprises the following beneficial effects:

by providing the control current for the level shifting unit, the output node of the level shifting unit slows down the rate of level conversion, especially for the level conversion of high level, so that the voltage impact on other devices of the memory can be avoided, and the devices are prevented from being damaged.

In the alternative, the control current comprises a first control current and a second control current, and the first control current and the second control current can be provided alternatively or completely, wherein the first control current can slow the low-level to high-level transition rate, and the second control current can slow the high-level to low-level transition rate;

in an alternative, the supply of the control current is related to the magnitude of the high level of the level transition, and if the magnitude of the high level is low (first level), the supply of the control current may be stopped in consideration of the fact that the first level may be a read voltage or other voltage that does not cause a voltage shock to the device or that requires an increase in the level transition rate, and if the magnitude of the high level is high (second level), the supply of the control current may be resumed in consideration of preventing a voltage shock to the memory device caused by a fast transition of the second level to slow down the level transition rate; therefore, power consumption can be saved, and the current utilization efficiency can be maximized.

Drawings

FIG. 1 is a schematic diagram of a level shift circuit according to the prior art;

fig. 2 is a schematic structural diagram of a level shift circuit according to embodiment 1;

fig. 3 is a schematic structural diagram of a level shift circuit according to embodiment 2.

Detailed Description

In order to make the objects, features and effects of the present invention more comprehensible, embodiments of the present invention are described in detail below with reference to the accompanying drawings.

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced in other ways than those specifically described herein, and thus the present invention is not limited to the specific embodiments disclosed below.

As mentioned in the background section, the level conversion efficiency of the prior art level shifters has a profound correlation with transistor size:

referring to fig. 1, when the input signal Data changes from high level to low level, the node V12 is lowered to low level by the through current (hereinafter referred to as a first through current) flowing through the NMOS transistor N2 and the PMOS transistor P2; the PMOS transistor P1 generates a through current (hereinafter referred to as a second through current) to raise the node V11 to a high level. In practice, the level falling rate of the node V12 and the level rising rate of the node V11 are related to the magnitudes of the first through current and the second through current, respectively. In the prior art, the first through current is increased by increasing the transistor size of an NMOS transistor N2, and the second through current is increased by increasing the transistor size of a PMOS transistor P1. First, increasing the size of a transistor is a limited means, and the size of the transistor affects the circuit area of a memory, and in the field of semiconductor technology, the size of the transistor is always controlled within a certain range; secondly, the magnitude of the level transition varies, and from the rate of level transition, the transition rate of the level is required to be fast and also to be slow for the level magnitude in a specific situation, and based on the diversity of the operating voltages in the memory and the difference in the level transition rate requirements, the prior art level shifter can only compromise setting the transistor size or fixing the transistor size:

for example, for a 90nm high-speed Flash memory, in which a voltage conversion of 0V to 3V can be satisfied in a read operation to output a read voltage, it is assumed that a level conversion rate of the level shift circuit shown in fig. 1 can satisfy a read rate required by the read operation;

however, the level shift circuit of fig. 1 needs to satisfy the voltage transition from 0V to 8V in the programming operation, and at this time, the voltage transition rate is fast, and the voltage of 8V may cause a transient voltage impact on other memories such as a column decoder and a memory cell, and the level transition rate is expected to be slow.

The analysis shows that: for the level shift circuit of the prior art, the transistor size is determined, the sizes of the first through current and the second through current are also determined, and the rate of level shift is mainly based on the first through current and the second through current formed in the transistor; therefore, it is considered that the level conversion rate is controlled by controlling the magnitude of the current flowing in the transistor.

Based on the above thought, the technical solution of the present invention provides a level shift circuit, which is described in detail below with reference to the accompanying drawings and embodiments.

Example 1

In view of the above problem, the present embodiment provides a level shift circuit as shown in fig. 2, including:

a current providing unit 100 adapted to provide a control current;

a level shift unit 200 including signal input nodes adapted to input the first level signal data and signal output nodes (out1, out2) adapted to output the second level signals (vout1, vout 2); the level shifting unit is connected with the current providing unit and is suitable for inputting the control current.

In this embodiment, the first level signal data is an input signal of the level shift unit 200, and the level shift unit 200 converts the second level signals (vout1, vout2) of the signal output nodes (out1, out2) between a low level and a high level according to the first level signal data. The high level may be provided by a first power supply external or internal to the level shifting circuit, and the low level may be provided by a second power supply external or internal to the level shifting circuit; the second power supply may provide a ground level (typically 0V).

When the first level signal data makes the output node out1 switch from high level to low level and the output node out2 switches from low level to high level, the current providing unit 100 may provide one path of control current (the second control current I2) to the output node out1, so that the level on the output node out1 slowly decreases, and the current providing unit 100 may also provide another path of control current (the first control current I1) to the output node out2, so that the level on the output node out2 slowly increases; the present embodiment does not require a through current provided by a transistor within the level shift unit 200, but rather, the level of the output nodes (out1, out2) is converted by the control current, so that the rate of level conversion of the circuit is controlled by controlling the magnitude of the control current.

Further, the second control current I2 may be considered to be loaded on the NMOS transistor on the side of the corresponding output node out1, and the first control current I1 may be considered to be loaded on the PMOS transistor on the side of the corresponding output node out 2. The first control current I1 and the second control current I2 may be provided alternatively or simultaneously.

Similarly, when the first level signal data makes the output node out2 switch from high to low and the output node out1 switches from low to high, the current providing unit 100 may provide the second control current I2 to the output node out2 to make the level at the output node out2 slowly decrease, and the current providing unit 100 may also provide the first control current I1 to the output node out1 to make the level at the output node out1 slowly increase. In the above case, the second control current I2 may be considered to be loaded on the NMOS transistor on the side of the corresponding output node out2, and the first control current I1 may be considered to be loaded on the PMOS transistor on the side of the corresponding output node out 1. The first control current I1 and the second control current I2 may be provided alternatively or simultaneously.

The present embodiment does not limit the specific structure of the level shift unit 200: the level shift unit 200 includes two corresponding output nodes out1, out2 and a signal input node datain; one of the output nodes may be used as the signal output node, or both of the output nodes may be used as the signal output node, and the selection of the output node is related to the function of the level shift circuit, so the present embodiment is not limited.

Example 2

This embodiment provides another more specific level shift circuit based on embodiment 1, as shown in fig. 3:

the level shift unit includes:

a first power supply node VH and a second power supply node VL;

a first output node out1 and a second output node out 2;

a first PMOS transistor P10, a second PMOS transistor P20, a first NMOS transistor N10 and a second NMOS transistor N20.

The first power supply node VH is adapted to be connected to said first power supply, the second power supply node VL is adapted to be connected to said second power supply, the first power supply provides a high level value vdd, the second power supply provides a low level value, in this embodiment, the second power supply node VL is directly connected to Ground (GND) and obtains a ground level.

The drain of the first PMOS transistor P10, the drain of the first NMOS transistor N10, and the gate of the second PMOS transistor P20 are connected to the first output node out1, respectively;

the drain of the second PMOS transistor P20, the drain of the second NMOS transistor N20, and the gate of the first PMOS transistor P10 are connected to the second output node out2, respectively;

the gate of the first NMOS transistor N10 is a signal input node datain, which is connected to the gate of the second NMOS transistor N20 through an inverter INV 1;

the source electrode of the first PMOS pipe P10 and the source electrode of the second PMOS pipe P20 are respectively suitable for being connected with a first power supply node VH;

the source of the first NMOS transistor N10 and the source of the second NMOS transistor N20 are each adapted to be coupled to a second power supply node VL.

The present embodiment uses the gate of the first NMOS transistor N10 as the signal input node, the first output node out1 and the second output node out2 as the signal output nodes, respectively, and the level values of the second level signals (vout1, vout2) are converted between the high level value vdd and the ground level.

In other embodiments, the signal input nodes of the level shift unit 200 may also include a gate of the first NMOS transistor N10 and a gate of the second NMOS transistor N20, which respectively input signals with opposite phases, for example, the gate of the first NMOS transistor N10 inputs the first level signal, and the gate of the second NMOS transistor N20 inputs the opposite phase of the first level signal.

The specific structure of the current supply unit of the present embodiment is described below.

With continued reference to fig. 3, the current providing unit of the present embodiment includes a first current providing unit for providing the first control current I1 as described in embodiment 1 and a second current providing unit for providing the second control current I2 as described in embodiment 1.

As shown in fig. 3, the first current supply unit includes:

and the PMOS current mirror is composed of an input PMOS tube P30 and a mirror image PMOS tube P40, wherein the source electrode of the mirror image PMOS tube P40 is connected with the first power supply, namely is connected with a high level vdd, and the drain electrode of the mirror image PMOS tube P40 is connected with a first power supply node VH.

In the present embodiment, the first control current I1 is generated by mirroring the first source-to-drain current formed in the input PMOS transistor P30 to the mirror PMOS transistor P40; the first control current I1 is input to the first power supply node VH, so that a small current from a source to a drain is formed in the first PMOS transistor P10 or the second PMOS transistor P20 during the level shift, and the small current is smaller than (or equal to) a source-drain current of a PMOS transistor in the level shift unit, and the small current can enable the voltage of a corresponding output node to slowly rise, so as to control the conversion efficiency from a low level to a high level of the output node, and reduce the conversion efficiency from the low level to the high level at the moment.

With continued reference to fig. 3, the second current supply unit includes:

and the NMOS current mirror is composed of an input NMOS transistor N30 and a mirror NMOS transistor N40, wherein the source electrode of the mirror NMOS transistor N40 is connected with the second power supply, namely, the second power supply is grounded, and the drain electrode of the mirror NMOS transistor N40 is connected with a second power supply node VL.

In the present embodiment, the second control current I2 is generated by mirroring the second drain-to-source current formed in the input NMOS transistor N30 to the mirror NMOS transistor N40; the second control current I2 is input to the second power supply node VL, so that a small current from a drain to a source is formed in the first NMOS transistor N10 or the second NMOS transistor P20 during the level shift, and the small current is smaller than (or equal to) the source-drain current of the NMOS transistor in the level shift unit, and the small current can slowly decrease the voltage of the corresponding output node, thereby reducing the conversion efficiency from the high level to the low level of the output node. The current value of the second control current I2 may be relatively greater than the current value of the first control current I1.

In general, the first control current I1 may be 30uA and the second control current I2 may be 60uA, compatible with 90nm high speed Flash memory. The values of the first control current and the second control current may be different for different types of memories.

In addition, the first current may be equal to the first control current I1 (when the transistor sizes of the input PMOS transistor P30 and the mirror PMOS transistor P40 are equal), or the proportional relationship between the first current and the first control current I1 may be set by adjusting the transistor sizes of the input PMOS transistor P30 and the mirror PMOS transistor P40, so as to obtain the required magnitude of the first control current I1;

similarly, the second current may be equal to the second control current I2 (when the transistor sizes of the input NMOS transistor N30 and the mirror NMOS transistor N40 are equal), or the proportional relationship between the second current and the second control current I2 may be set by adjusting the transistor sizes of the input NMOS transistor N30 and the mirror NMOS transistor N40, so as to obtain the required magnitude of the second control current I2.

Further, with reference to fig. 3: the first current in the input PMOS transistor P30 and the second current in the input NMOS transistor N30 may be provided by the current source unit a, where the first current and the second current are equal, the source of the input PMOS transistor P30 is connected to the high level vdd, the drain is connected to one end of the current source unit a, the source of the input NMOS transistor N30 is grounded, and the drain is connected to the other end of the current source unit a.

The current supply unit further comprises a control tube C0, wherein the control tube C0 is arranged between any two elements of a link formed by the first power supply (vdd), the input PMOS tube P30, the current supply unit a, the input NMOS tube N30 and the second power supply (GND), including between the input PMOS tube P30 and the current supply unit a and between the current supply unit a and the input NMOS tube N30. The control transistor C0 of the present embodiment is disposed between the input PMOS transistor P30 and the current source unit a. The control tube C0 actually controls the conduction of the link, controls the generation of the first current and the second current, and also acts as an input control for the first control current and the second control current.

It should be noted that, in other embodiments, the first current and the second current may also be provided by different first current source units and second current source units, respectively. At this time, the first power supply (vdd), the input PMOS transistor P30, the first current source unit, and the second power supply (GND) form a first link; the second current source unit, the input NMOS transistor N30, and the second power supply (GND) constitute a second link. The first link can be controlled to be conducted by the first control tube, and the second link can be controlled to be conducted by the second control tube.

The structure can control the slew rate of the level shift circuit during high level amplitude conversion, and particularly slow down the slew rate.

On the premise of the above scheme, in terms of saving power consumption, the level shift circuit of this embodiment can also selectively provide the first control current and the second control current based on different high level amplitudes, and further control to disable or provide the control current. This design is considered based on the level diversity required inside the memory and the different rate requirements for the level shifting input. The types of the high levels provided by the level shift circuit can be classified according to the difference of the values of the levels required by the memory, the level with the amplitude higher than the threshold value can be classified as a first level, and the level with the amplitude lower than or equal to the threshold value can be classified as a second level, that is, the high level vdd in fig. 3 can be the first level, or can be the second level, for example, corresponding to the example of a 90nm high-speed Flash memory, the threshold value can be set to 5V, when the high level is a read voltage, the amplitude 3V of the required read voltage can be considered as belonging to the second level, and when the high level is a program voltage, the required program voltage 8V can be considered as belonging to the first level.

When the high level vdd is the first level, the control current is input to the level conversion unit to slow down the level conversion rate, because the fast conversion of the low level to the first level may cause voltage impact of the first level on other devices of the memory;

when the high level vdd is the second level, since the read rate requirement is that the level shift has a faster shift rate, and the second level does not cause voltage impact to other devices of the memory, the generation and input of the control current can be stopped, and the level shift can be realized directly through the through current of the level shift unit transistor, so as to obtain a faster level shift rate.

The level shift circuit shown in fig. 3 is a specific circuit capable of disabling or providing a control current to a level shift unit according to the kind of the high level and different level shift requirements:

in the current supply unit of the present embodiment:

the first current providing unit further comprises a control NMOS transistor N50, a drain of which is connected to the gate of the mirror PMOS transistor P40, a gate of the control NMOS transistor N50 is inputted with a first control signal, and a source of which is inputted with a level suitable for turning on the mirror PMOS transistor, in this embodiment, a source of the control NMOS transistor N50 is connected to the second power supply, i.e., grounded. The first control signal is suitable for controlling the control NMOS tube to be switched off when the first power supply provides a first level and controlling the control NMOS tube to be switched on when the first power supply provides a second level.

The second current providing unit further includes a control PMOS transistor P50, a drain of which is connected to the gate of the mirror NMOS transistor N40, a gate of the control PMOS transistor P50 receives a second control signal, and a source of which receives a level suitable for turning on the mirror NMOS transistor, in this embodiment, the source of the control PMOS transistor P50 is connected to the first power supply, i.e., is connected to the high level vdd. The second control signal is suitable for controlling the control PMOS tube to be switched off when the first power supply provides a first level and controlling the control PMOS tube to be switched on when the first power supply provides a second level.

The gate of the control tube C0 is inputted with a third control signal, which is suitable for controlling the control tube C0 to be turned on when the first power supply provides the first level and controlling the control tube C0 to be turned off when the first power supply provides the second level.

The first control signal, the second control signal, and the third control signal may be different control signals independently from each other, or as shown in fig. 3, the control signal EN may be the second control signal and the third control signal, and the inverted signal ENb of the control signal EN may be the first control signal.

In other embodiments, the current providing unit may also include only the first current providing unit or the second current providing unit, as needed:

when the current providing unit only comprises the first current providing unit, the second power supply node VL is directly connected with the second power supply, and the level shifting unit can obtain the slow down of the low-level to high-level transition rate of the signal output node. The structure of the first current providing unit can refer to fig. 3, wherein the first current can be provided by the current source unit a; the control tube C0 may be disposed between the first current providing unit and the current source unit a, and the first control current is controlled and provided through the control NMOS tube N50 and the control tube C0.

When the current supply unit includes only the second current supply unit, the first power supply node VH is directly connected to the first power supply vdd, and the level shift unit can obtain a slow down of the high-level to low-level slew rate of the signal output node. The structure of the second current providing unit can refer to fig. 3, wherein the second current can be provided by the current source unit a; the control tube C0 may be disposed between the second current providing unit and the current source unit a, and the second control current is controlled and provided by controlling the PMOS tube P50 and the control tube C0.

It should be noted that, for simplicity, the high-level driving end of each transistor or element in this embodiment is connected to the first power supply to obtain a high level, and the low-level driving end is connected to the second power supply (ground) to obtain a low level, but in the specific implementation process, it is understood that it is also within the scope of the present invention if other high-level power supplies or low-level power supplies are used as the level input of the driving end. Although the present invention has been described with reference to the preferred embodiments, it is not intended to limit the present invention, and those skilled in the art can make variations and modifications of the present invention without departing from the spirit and scope of the present invention by using the methods and technical contents disclosed above.

Claims

1. A level shifting circuit, comprising:

a current providing unit adapted to provide a control current;

a level shift unit including a signal input node adapted to input a first level signal and a signal output node adapted to output a second level signal; the level shifting unit is connected with the current providing unit and is suitable for inputting the control current so as to control the level conversion rate of the output node;

when the first level signal makes the signal output node switch from a low level to a high level, the current providing unit is suitable for providing the control current to the signal output node so as to reduce the level rising rate of the signal output node.

2. The level shifting circuit of claim 1, wherein the level shifting cell further comprises a first power supply node adapted to connect to a first power supply and a second power supply node adapted to connect to a second power supply; the level value of the second level signal is converted between the level value of the first power source and the level value of the second power source.

3. The level shifting circuit of claim 2, wherein the first power supply is adapted to provide a first level and a second level;

4. The level shift circuit according to claim 2, wherein the current supply unit is a first current supply unit or a second current supply unit, or the current supply unit includes a first current supply unit and a second current supply unit;

5. The level shifting circuit of claim 4,

the first current providing unit comprises a PMOS current mirror consisting of an input PMOS tube and a mirror image PMOS tube, wherein the source electrode of the mirror image PMOS tube is connected with the first power supply, and the drain electrode of the mirror image PMOS tube is connected with the first power supply node;

6. The level shifting circuit of claim 5,

the first current providing unit also comprises a control NMOS tube, the drain electrode of the control NMOS tube is connected with the grid electrode of the mirror image PMOS tube, the grid electrode inputs a first control signal, and the source electrode inputs a level suitable for enabling the mirror image PMOS tube to be conducted;

7. The level shifting circuit of claim 6, wherein the first power supply provides a first level and a second level;

8. The level shift circuit according to claim 5, wherein the current supply unit includes a first current supply unit and a second current supply unit, further comprising: and the current source unit is connected between the input PMOS tube and the input NMOS tube.

9. The level shifting circuit of claim 8, wherein the first power supply provides a first level and a second level; the current supply unit further includes: the control tube is connected between the current source unit and the input PMOS tube or between the current source unit and the input NMOS tube;

10. The level shifting circuit of claim 2, wherein the signal output node comprises a first output node and a second output node, the level shifting unit further comprising a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, and an inverter;