CN103730422A - Semiconductor device manufacturing method - Google Patents
Semiconductor device manufacturing method Download PDFInfo
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- CN103730422A CN103730422A CN201210393777.XA CN201210393777A CN103730422A CN 103730422 A CN103730422 A CN 103730422A CN 201210393777 A CN201210393777 A CN 201210393777A CN 103730422 A CN103730422 A CN 103730422A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 20
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 239000010410 layer Substances 0.000 claims abstract description 114
- 238000000034 method Methods 0.000 claims abstract description 49
- 239000011241 protective layer Substances 0.000 claims abstract description 31
- 229910052751 metal Inorganic materials 0.000 claims abstract description 16
- 239000002184 metal Substances 0.000 claims abstract description 16
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims abstract description 8
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 27
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 27
- 238000000151 deposition Methods 0.000 claims description 19
- 230000008021 deposition Effects 0.000 claims description 15
- 229920002120 photoresistant polymer Polymers 0.000 claims description 14
- 239000000758 substrate Substances 0.000 claims description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 10
- 238000005530 etching Methods 0.000 claims description 9
- 238000002513 implantation Methods 0.000 claims description 2
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 2
- 238000000206 photolithography Methods 0.000 claims 3
- 125000006850 spacer group Chemical group 0.000 claims 1
- 230000007797 corrosion Effects 0.000 abstract description 8
- 238000005260 corrosion Methods 0.000 abstract description 8
- 230000007547 defect Effects 0.000 abstract description 5
- 238000001039 wet etching Methods 0.000 abstract description 5
- 230000010354 integration Effects 0.000 abstract 1
- 230000004888 barrier function Effects 0.000 description 20
- 238000009413 insulation Methods 0.000 description 12
- 230000006835 compression Effects 0.000 description 9
- 238000007906 compression Methods 0.000 description 9
- 239000000463 material Substances 0.000 description 9
- 238000001259 photo etching Methods 0.000 description 7
- 239000007772 electrode material Substances 0.000 description 4
- 238000000059 patterning Methods 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 239000003989 dielectric material Substances 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 239000002800 charge carrier Substances 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 229910052735 hafnium Inorganic materials 0.000 description 2
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 238000006467 substitution reaction Methods 0.000 description 2
- 229910003855 HfAlO Inorganic materials 0.000 description 1
- 229910004129 HfSiO Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910010413 TiO 2 Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 229910000765 intermetallic Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 229910052761 rare earth metal Inorganic materials 0.000 description 1
- 150000002910 rare earth metals Chemical class 0.000 description 1
- 238000012163 sequencing technique Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Images
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
- H10D84/0172—Manufacturing their gate conductors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/01—Manufacture or treatment
- H10D64/017—Manufacture or treatment using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/02—Manufacture or treatment characterised by using material-based technologies
- H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
- H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
- H10D30/792—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions comprising applied insulating layers, e.g. stress liners
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
本发明提供了一种应力半导体制造方法。本发明中，首先在NMOS区域形成张应力层以在PMOS区域形成压应力层，沉积TEOS并进行平坦化处理，接着全面沉积保护层；采用栅极线条掩模版对保护层进行光刻和刻蚀，打开虚设栅极，由于在张应力层和压应力层之上完全覆盖了保护层，并且保护层在湿法腐蚀液中的腐蚀速率很小，因此张应力层和压应力层不会受到任何损伤，克服了现有技术中的缺陷；接着，形成栅极凹槽后，完成高K栅绝缘层和金属栅极制造，实现了后栅工艺与双应变应力层的工艺集成。
The invention provides a stress semiconductor manufacturing method. In the present invention, firstly, a tensile stress layer is formed in the NMOS region to form a compressive stress layer in the PMOS region, TEOS is deposited and planarized, and then a protective layer is deposited in an all-round way; the protective layer is photolithographically and etched using a grid line mask , open the dummy gate, since the protective layer is completely covered on the tensile stress layer and the compressive stress layer, and the corrosion rate of the protective layer in the wet etching solution is very small, so the tensile stress layer and the compressive stress layer will not be affected by any The defect in the prior art is overcome; then, after forming the gate groove, the high-K gate insulating layer and the metal gate are manufactured, realizing the process integration of the last gate process and the double strain stress layer.
Description
Technical field
The present invention relates to method, semi-conductor device manufacturing method field, especially, relate to the integrated approach of two strain stress layers of grid technique after a kind of CMOS of being applied to.
Background technology
Semiconductor integrated circuit technology is entering into after the technology node of 90nm characteristic size, maintains or to improve transistor performance more and more challenging.After 90nm node, stress technique is used to improve the performance of device gradually.With it simultaneously, aspect manufacturing process, the high-K metal gate technology in rear grid technique (gate last) is also used to tackle along with device constantly reduces and the challenge that brings gradually.In stress technique, two strain stress layers (DSL, dual stress liner) technology and common process compatibility is high, cost is lower, therefore, is adopted by Ge great semiconductor manufacturer.
DSL technology, refers in dissimilar MOSFET region, forms the stressor layers respectively with tensile stress and compression, conventionally, forms tensile stress layer in territory, nmos area, forms compressive stress layer in PMOS region.Referring to accompanying drawing 1, figure is the step having adopted in the CMOS manufacturing process of DSL technology.Wherein, on substrate 1, be formed with NMOS 2 and PMOS3, different MOS transistor are kept apart by sti structure 4.NMOS 2 comprises NMOS dummy gate electrode 6 and dummy gate electrode insulating barrier 5 thereof, PMOS 3 comprises PMOS dummy gate electrode 8 and dummy gate electrode insulating barrier 7 thereof, dummy gate electrode (dummy gate) and dummy gate electrode insulating barrier thereof are used to rear grid technique, dummy gate electrode is generally polysilicon or amorphous silicon grid, dummy gate electrode insulating barrier is generally silicon oxide layer, after completing transistor miscellaneous part, remove dummy gate electrode and dummy gate electrode insulating barrier thereof, form grid groove, then in grid groove, form high K gate insulation layer and metal gates.On NMOS 2, be coated with tensile stress layer 9, be coated with compressive stress layer 10 on PMOS 3, stressor layers material is generally silicon nitride.These two kinds of stressor layers provide stress to the channel region of NMOS and PMOS respectively, to increase the mobility of channel region charge carrier, guarantee the performance of transistor in deep-submicron field.Then,, in step after this, need to open dummy gate electrode.Method is at present, after forming stressor layers, deposition TEOS layer 20, and then carry out CMP, open dummy gate electrode, referring to accompanying drawing 2, then remove dummy gate electrode and dummy gate electrode insulating barrier, but, adopt the problem that this method faces to be exactly: dummy gate electrode insulating barrier is generally silica, removing method is DHF wet etching, particularly, at room temperature (23 degrees Celsius), the speed of the DHF corrosion oxidation silicon of 1: 100 is 30 ± 1 A/min of clocks, but, meanwhile, tensile stress silicon nitride corrosion rate in the DHF of this condition is 498 A/min of clocks, corrosion rate much larger than silica in DHF, owing to understanding some tensile stress layer 9 after CMP, come out and by TEOS layer 20, do not covered, referring to position shown in dotted line circle in Fig. 2, like this, when removing illusory gate insulation layer, thereby the tensile stress layer 9 exposing is corroded and forms hole, referring to accompanying drawing 3, thereby will cause causing hafnium and metal gate material to be filled in follow-up high-K metal gate technique in hole, causing the deteriorated of device performance if do not addressed this problem, simultaneously, due to stressor layers loss, caused the integrated failure of DSL.
Therefore, a kind of new integrated approach that is applied to two strain stress layers of grid technique after CMOS need to be provided, above-mentioned defect can be overcome.
Summary of the invention
The invention provides a kind of transistorized manufacture method, utilize the extra material layer forming as protective layer, and adopt grid reticle to carry out photoetching, avoided the defect of tensile stress layer loss in prior art.
According to an aspect of the present invention, the invention provides a kind of method, semi-conductor device manufacturing method, integrated for the two strain stress layers at rear grid technique, it comprises the steps:
Semiconductor substrate is provided, in this Semiconductor substrate, forms sti structure, and carry out well region injection, form territory, nmos area and PMOS region;
Form nmos pass transistor and PMOS transistor, described nmos pass transistor and described PMOS transistor comprise dummy gate electrode and dummy gate electrode insulating barrier, and described dummy gate electrode is by grid lines lithography layout case;
On described nmos pass transistor, form tensile stress layer, on described PMOS transistor, form compressive stress layer;
Carry out CMP technique, expose the upper surface of described dummy gate electrode, and make the upper surface of described dummy gate electrode, described tensile stress layer, described compressive stress layer in same plane;
Comprehensive deposition protective layer;
With grid lines reticle, described protective layer is carried out to photoetching and etching, remove the described protective layer that is positioned at described dummy gate electrode upper surface, expose described dummy gate electrode upper surface;
Remove successively described dummy gate electrode and described dummy gate electrode insulating barrier, form grid groove;
In described grid groove, form respectively the transistorized high K gate insulation layer of described nmos pass transistor and described PMOS and metal gates.
According to an aspect of the present invention, forming nmos pass transistor and PMOS transistor specifically comprises:
Form described dummy gate electrode and described dummy gate electrode insulating barrier;
Form grid gap wall;
Form transistorized source and drain areas.
According to an aspect of the present invention, on described nmos pass transistor, forming tensile stress layer specifically comprises:
Deposition tensile stress silicon nitride film comprehensively; with the photoresist layer protection of patterning, be positioned at the described tensile stress silicon nitride film of described nmos pass transistor; removal is positioned at the transistorized described tensile stress silicon nitride film of described PMOS, then removes photoresist layer, forms described tensile stress layer.
According to an aspect of the present invention, on described PMOS transistor, forming compressive stress layer specifically comprises:
Deposition compression silicon nitride film comprehensively; be positioned at the transistorized described compression silicon nitride film of described PMOS with the photoresist layer protection of patterning; removal is positioned at the described compression silicon nitride film of described nmos pass transistor, then removes photoresist layer, forms described compressive stress layer.
According to an aspect of the present invention, described protective layer is silica, compression silicon nitride or unstressed silicon nitride, and thickness is 100 dusts.
According to an aspect of the present invention, before CMP technique, comprehensive deposition TEOS layer.
The invention has the advantages that: first in territory, nmos area, form tensile stress layer and in PMOS region, form compressive stress layer, deposition TEOS also carries out planarization, then comprehensive deposition protective layer; Adopt grid lines mask to carry out photoetching and etching to protective layer, open dummy gate electrode, owing to having covered protective layer completely on tensile stress layer and compressive stress layer, and the corrosion rate of protective layer in wet etching liquid is very little, therefore tensile stress layer and compressive stress layer can not be subject to any damage, have overcome defect of the prior art; Then, form after grid groove, complete high K gate insulation layer and metal gates manufacture, realized rear grid technique integrated with the technique of two strain stress layers.
Accompanying drawing explanation
The integrated approach of the two strain stress layers of the existing rear grid technique in Fig. 1-3;
The integrated approach of the two strain stress layers of Fig. 4-9 rear grid technique of the present invention.
Embodiment
Below, by the specific embodiment shown in accompanying drawing, the present invention is described.But should be appreciated that, these descriptions are exemplary, and do not really want to limit the scope of the invention.In addition, in the following description, omitted the description to known configurations and technology, to avoid unnecessarily obscuring concept of the present invention.
The invention provides a kind of method, semi-conductor device manufacturing method, relate to especially a kind of transistor fabrication process that utilizes clearance wall technology, referring to accompanying drawing 4-9, will describe method, semi-conductor device manufacturing method provided by the invention in detail.
First, referring to accompanying drawing 4, in Semiconductor substrate 1, be formed with NMOS 2 and PMOS 3, different MOS transistor are kept apart by sti structure 4.Wherein, in the present embodiment, adopt monocrystalline substrate, alternatively, also can adopt germanium substrate or other suitable Semiconductor substrate.The method that forms sti structure 4 in Semiconductor substrate 1 specifically comprises, first in Semiconductor substrate 1, be coated with photoresist, then make sti structure 4 figures by lithography, and Semiconductor substrate 1 is carried out to anisotropic etching acquisition shallow trench, filled dielectric material in this shallow trench, as SiO
2thereby, form sti structure.After forming sti structure 4, carry out well region injection (not illustrating in the drawings), form territory, nmos area and PMOS region.The well region implanted dopant of PMOS is N-type impurity, and the well region implanted dopant of NMOS is p type impurity.
Then, form NMOS dummy gate electrode 6 and dummy gate electrode insulating barrier 5, PMOS dummy gate electrode 8 and dummy gate electrode insulating barrier 7 thereof.Specifically comprise: first at substrate 1 surface deposition one deck dummy gate electrode insulating layer material, for example, be SiO
2, its thickness is preferably 0.5-10nm, and depositing operation is for example CVD.Afterwards, deposition dummy gate electrode material, after the present invention, in grid technique, dummy gate electrode material is for example polysilicon or amorphous silicon.In addition, on dummy gate electrode material layer, be also formed with hard mask layer (not shown).Then, carry out photoresist coating, with grid lines reticle, carry out photoetching, define dummy gate electrode figure, to dummy gate electrode material and dummy gate electrode insulating layer material order etching, thereby form dummy gate electrode and the dummy gate electrode insulating barrier thereof of NMOS and PMOS simultaneously.Dummy gate electrode (dummy gate) and dummy gate electrode insulating barrier thereof are used to rear grid technique, after completing transistor miscellaneous part, remove dummy gate electrode and dummy gate electrode insulating barrier thereof, form grid groove, then in grid groove, form high K gate insulation layer and metal gates.
Form after dummy gate electrode lines, form grid gap wall, adopt the mode of deposition and time etching.Afterwards, form respectively the source and drain areas of NMOS and PMOS, can adopt the mode of Implantation, also can first take dummy gate electrode as mask, carry out self aligned source and drain areas etching, form source and drain areas groove, then carry out source and drain areas epitaxial growth, thereby form transistorized source and drain areas.
Afterwards, on NMOS 2, form tensile stress layer 9.Specifically comprise: deposit tensile stress silicon nitride film first comprehensively, then with the photoresist layer of patterning, protect the tensile stress silicon nitride film in NMOS 2 regions, remove the tensile stress silicon nitride film in PMOS 3 regions, then remove photoresist layer, form tensile stress layer 9.The thickness of tensile stress layer 9 is h
1.
Afterwards, on PMOS 3, form compressive stress layer 10.Specifically comprise: deposit compression silicon nitride film first comprehensively, then with the photoresist layer of patterning, protect the compression silicon nitride film in PMOS 3 regions, remove the compression silicon nitride film in NMOS 2 regions, then remove photoresist layer, form compressive stress layer 10.The thickness of compressive stress layer 10 is h
2, wherein, h
2with h
1preferably equate, also can be unequal, but difference is no more than S0nm.
The formation sequencing of above two kinds of stressor layers can be exchanged, and they provide stress to the channel region of NMOS and PMOS respectively, to increase the mobility of channel region charge carrier, guarantees the performance of transistor in deep-submicron field.
Then, comprehensive deposition TEOS layer (not shown), carries out CMP technique, and planarization device architecture is opened dummy gate electrode upper surface, referring to accompanying drawing 5.And, in this step CMP technique, make the upper surface of dummy gate electrode, tensile stress layer 9, compressive stress layer 10 in same plane.After this step, the upper surface of dummy gate electrode 6 and 8 is exposed out.
Then, referring to accompanying drawing 6, comprehensive deposition protective layer 11, the material of protective layer 11 can be the corrosion rate material lower with respect to tensile stress layer 9 in DHF, is specially silica, compression silicon nitride, unstressed silicon nitride etc., thickness is for example 100nm.Protective layer 11 covers on whole device area simultaneously.
Then, referring to accompanying drawing 7, with grid lines reticle, protective layer 11 is carried out to photoetching and etching, remove the protective layer 11 that is positioned at dummy gate electrode upper surface.The object of this step is to open dummy gate electrode upper surface, because this figure is corresponding to grid lines, therefore can adopt grid lines reticle to carry out photoetching, just can expose dummy gate electrode upper surface.
Then, referring to accompanying drawing 8, remove successively dummy gate electrode and dummy gate electrode insulating barrier, form grid groove 12.Specifically comprise: first remove dummy gate electrode 6 and 8; Then, remove dummy gate electrode insulating barrier 5 and 7, removing method is DHF wet etching.Because protective layer 11 has covered whole tensile stress layers 9 and compressive stress layer 10; owing to comparing with dummy gate electrode insulating barrier 5,7 with tensile stress layer 9; DHF is to the corrosion rate of protective layer 11 little; consider the thickness that protective layer 11 has simultaneously; in the process of removal dummy gate electrode insulating barrier 5 and 7; protective layer 11 can not be completely removed; therefore; due to the protection of protective layer 11; DHF cannot corrode tensile stress silicon nitride; tensile stress layer 9 and compressive stress layer 10 all will not have any loss, thereby can provide enough stress to raceway groove.
Then, referring to accompanying drawing 9, in grid groove 12, form respectively high K gate insulation layer 13 and the metal gates 14 of NMOS 2, high K gate insulation layer 15 and the metal gates 16 of PMOS 3.High K gate insulation layer 13 and high K gate insulation layer 15 are selected from one or more layers of following material one or a combination set of formation: Al
2o
3, HfO
2, comprise HfSiO
x, HfSiON, HfAlO
x, HfTaO
x, HfLaO
x, HfAlSiO
xand HfLaSiO
xone of at least, at interior hafnium base high K dielectric material, comprise ZrO
2, La
2o
3, LaAlO
3, TiO
2, or Y
2o
3one of at least at interior rare earth based high K dielectric material.The thickness of high K gate insulation layer 13 and high K gate insulation layer 15 is 0.5-100nm, is preferably 1-10nm, and depositing operation is for example CVD.The material of metal gates 14 and metal gates 16 is metal or metallic compound, for example TiN, TaN, W.The grid of NMOS and PMOS and high-K gate insulating barrier formation order can be exchanged according to demand.
Like this, the manufacture of high-K metal grid completes, and has realized rear grid technique of the present invention and two strain stress layer integrated technique, can carry out afterwards the preparation of interlayer dielectric layer and interconnection line.
So far, the present invention proposes and describes in detail rear grid technique and two integrated method, semi-conductor device manufacturing method of strain stress layer.In the method for the invention, first in territory, nmos area, form tensile stress layer and in PMOS region, form compressive stress layer, deposition TEOS also carries out planarization, then comprehensive deposition protective layer; Adopt grid lines mask to carry out photoetching and etching to protective layer, open dummy gate electrode, owing to having covered protective layer completely on tensile stress layer and compressive stress layer, and the corrosion rate of protective layer in wet etching liquid is very little, therefore tensile stress layer and compressive stress layer can not be subject to any damage, have overcome defect of the prior art; Then, form after grid groove, complete high K gate insulation layer and metal gates manufacture, realized rear grid technique integrated with the technique of two strain stress layers.
With reference to embodiments of the invention, the present invention has been given to explanation above.But these embodiment are only used to the object of explanation, and are not intended to limit the scope of the invention.Scope of the present invention is limited by claims and equivalent thereof.Do not depart from the scope of the present invention, those skilled in the art can make a variety of substitutions and modifications, and these substitutions and modifications all should fall within the scope of the present invention.
Claims (6)
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| CN201210393777.XA CN103730422B (en) | 2012-10-16 | 2012-10-16 | Semiconductor device manufacturing method |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106024617A (en) * | 2015-03-31 | 2016-10-12 | 台湾积体电路制造股份有限公司 | Dry etching gas and method of manufacturing semiconductor device |
| CN110729236A (en) * | 2019-10-23 | 2020-01-24 | 成都中电熊猫显示科技有限公司 | Manufacturing method of array substrate, array substrate and display panel |
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| CN1349247A (en) * | 2000-10-13 | 2002-05-15 | 海力士半导体有限公司 | Method for forming metallic grid |
| US20120080755A1 (en) * | 2010-10-05 | 2012-04-05 | Jaeseok Kim | Methods for Forming Gates in Gate-Last Processes and Gate Areas formed by the Same |
| CN102543739A (en) * | 2010-12-22 | 2012-07-04 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor device |
| CN102543872A (en) * | 2010-12-24 | 2012-07-04 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor device |
-
2012
- 2012-10-16 CN CN201210393777.XA patent/CN103730422B/en active Active
Patent Citations (4)
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|---|---|---|---|---|
| CN1349247A (en) * | 2000-10-13 | 2002-05-15 | 海力士半导体有限公司 | Method for forming metallic grid |
| US20120080755A1 (en) * | 2010-10-05 | 2012-04-05 | Jaeseok Kim | Methods for Forming Gates in Gate-Last Processes and Gate Areas formed by the Same |
| CN102543739A (en) * | 2010-12-22 | 2012-07-04 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor device |
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| CN106024617A (en) * | 2015-03-31 | 2016-10-12 | 台湾积体电路制造股份有限公司 | Dry etching gas and method of manufacturing semiconductor device |
| CN106024617B (en) * | 2015-03-31 | 2019-08-09 | 台湾积体电路制造股份有限公司 | Method for manufacturing semiconductor device |
| CN110729236A (en) * | 2019-10-23 | 2020-01-24 | 成都中电熊猫显示科技有限公司 | Manufacturing method of array substrate, array substrate and display panel |
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| CN103730422B (en) | 2017-09-26 |
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