CN103745933B - The formation method of encapsulating structure - Google Patents
The formation method of encapsulating structure Download PDFInfo
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- CN103745933B CN103745933B CN201310655148.4A CN201310655148A CN103745933B CN 103745933 B CN103745933 B CN 103745933B CN 201310655148 A CN201310655148 A CN 201310655148A CN 103745933 B CN103745933 B CN 103745933B
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- pin
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- metal coupling
- lead frame
- layer
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- NTSDHVIXFWZYSM-UHFFFAOYSA-N [Ag].[Sb].[Sn] Chemical compound [Ag].[Sb].[Sn] NTSDHVIXFWZYSM-UHFFFAOYSA-N 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
- H01L21/4814—Conductive parts
- H01L21/4885—Wire-like parts or pins
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18165—Exposing the passive side of the semiconductor or solid-state body of a wire bonded chip
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
A kind of formation method of encapsulating structure, comprise and lead frame is provided, described lead frame comprises first surface and relative second surface, lead frame having some is the load bearing unit of matrix arrangement and the middle muscle of fixing load bearing unit, each load bearing unit has some discrete pins, has opening between adjacent leads; The first metal coupling is formed at the first surface of pin; Preformed cover plate is provided, described preformed cover plate comprises the first plastic packaging layer, in first plastic packaging layer, there is some integrated units, there is in each integrated unit at least one semiconductor chip, described semiconductor chip surface have some pads, first plastic packaging layer exposes the pad on semiconductor chip, described pad has the second metal coupling, and the second metal coupling is formed with solder layer; By the upside-down mounting of preformed cover plate on the first surface of lead frame, the second metal coupling on semiconductor chip and the first metal coupling on pin are welded together.Encapsulating structure integrated level of the present invention improves.
Description
Technical field
The present invention relates to field of semiconductor package, particularly a kind of formation method of encapsulating structure.
Background technology
Along with electronic product is if mobile phone, notebook computer etc. are towards miniaturization, portable, ultrathin, multimedization and meet the low cost future development of public demand, the packing forms of high density, high-performance, high reliability and low cost and packaging technology thereof obtain and develop fast.Compared with the packing forms such as expensive BGA (BallGridArray), novel encapsulated technology fast-developing in recent years, as four limit flat non-pin QFN (QuadFlatNo-leadPackage) encapsulation, due to the advantage that it has good hot property and electrical property, size is little, cost is low and high production rate etc. is numerous, cause the revolution that of microelectronic packaging technology field is new.
Fig. 1 is the structural representation of existing QFN encapsulating structure, and described QFN encapsulating structure comprises: semiconductor chip 14, and described semiconductor chip 14 has pad 15; Pin 16 (lead frame), described pin 16 arranges around the surrounding of described semiconductor chip 14; Plain conductor 17, the pad 15 of semiconductor chip 14 is electrically connected with the pin 16 around described semiconductor chip 14 by plain conductor 17; Capsulation material 18, semiconductor chip 15, metal wire 17 and pin 16 seal by described capsulation material 18, and the surface exposure of pin 16, in the bottom surface of capsulation material, realizes the electrical connection of semiconductor chip 14 and external circuit by pin 16.
Existing leadframe package can only for the encapsulation of single semiconductor chip and lead frame, and packaging efficiency is lower.
Summary of the invention
The problem that the present invention solves how to improve the efficiency of encapsulation.
For solving the problem, the invention provides a kind of formation method of encapsulating structure, comprise: lead frame is provided, described lead frame comprises first surface and the second surface relative with first surface, described lead frame has some in matrix arrangement load bearing unit and between load bearing unit for muscle in fixing load bearing unit, each load bearing unit has some discrete pins, has opening between adjacent leads; The first metal coupling is formed at the first surface of pin; Preformed cover plate is provided, preformed cover plate, described preformed cover plate comprises the first plastic packaging layer, there is in first plastic packaging layer the integrated unit of some arrangements in matrix, have at least one semiconductor chip in each integrated unit, described semiconductor chip surface has some pads, the first plastic packaging layer exposes the pad on semiconductor chip, described pad has the second metal coupling, the second metal coupling is formed with solder layer; By the upside-down mounting of preformed cover plate on the first surface of lead frame, make the integrated unit in preformed cover plate corresponding with the load bearing unit in lead frame, the first metal coupling on pin in the second metal coupling on semiconductor chip in integrated unit and load bearing unit is welded together by solder layer, forms the encapsulation unit of some matrixes arrangement; Filling is expired the opening between pin and is filled the second plastic packaging layer in space between described preformed cover plate and the first surface of lead frame, and the second plastic packaging layer exposes the second surface of pin; Cut along encapsulation unit, form some discrete encapsulating structures.
Optionally, the forming process of described lead frame is: provide leadframe metal layer, described leadframe metal layer comprise some in matrix arrangement bearing area and between adjacent bearing area in muscle region; Etch the bearing area of described leadframe metal layer, form some discrete pins, between adjacent leads, there is opening, a side of pin is connected with middle muscle region, other three sides are unsettled, the some pins formed in each bearing area form the load bearing unit of lead frame, and the middle muscle region of fixing pin forms the middle muscle of lead frame.
Optionally, described opening comprises the first opening and the second opening that mutually run through, and the width of described first opening is less than the width of the second opening, and described first metal coupling is positioned on the surface of pin away from the second opening.
Optionally, described first opening with the forming process of the second opening is: described leadframe metal layer comprises first surface and the second surface relative with first surface, the first surface of the bearing area of etch lead frame metal level, forms some first openings in the bearing area of leadframe metal layer; The second surface of the bearing area of etch lead frame metal level, forms some second openings in the bearing area of leadframe metal layer, and the first opening and the second opening run through mutually, and the first opening and the second opening form opening.
Optionally, the surface of etching pin, forms groove, forms the first metal coupling in groove in pin, and the top surface of described first metal coupling is higher than the surface of slot opening.
Optionally, the width of described first metal coupling is less than the width of groove.
Optionally, described solder layer also covers sidewall and the lower surface of the groove of the first metal coupling both sides.
Optionally, described solder layer also covers the sidewall of the groove of the first metal coupling both sides and the part surface of lower surface and pin.
Optionally, also comprise: in the part first plastic packaging layer between the adjacent integrated unit of described preformed cover plate, form some discrete the first slotted eyes running through the first plastic packaging layer thickness.
Optionally, also comprise: formed in muscle in the part between described load bearing unit some discrete run through in the second slotted eye of muscle thickness.
Compared with prior art, technical scheme of the present invention has the following advantages:
The formation method of encapsulating structure of the present invention, by some semiconductor chip upside-down mountings side on the lead frames, by the first metal coupling, pad on some semiconductor chips is electrically connected with the pin surface in load bearing unit by the syndeton that solder layer and the second metal coupling are formed, pin to be arranged on around single semiconductor chip then by method for packing that the pad on semiconductor chip is connected with pin by plain conductor relative to existing, the encapsulating structure of the method for packing formation of the embodiment of the present invention realizes the integral packaging of multiple semiconductor chip and pin, improve the efficiency of encapsulation, and this method for packing can realize the encapsulation of the wafer scale of lead frame structure, improve the integrated level of encapsulating structure.In addition, the existence of the first metal coupling, on the one hand when by semiconductor chip upside-down mounting on the lead frames time, described first metal coupling can play the effect of location, on the other hand, the existence of the first metal coupling, directly be welded on pin compared to by the second metal coupling on semiconductor chip, after pin is formed the first metal coupling, when welding, the gradient steepening of the syndeton between semiconductor chip and pin, the area of the pin surface that syndeton occupies reduces, again on the one hand, the existence of the first metal coupling, distance between semiconductor chip and pin is increased, forming the second plastic packaging layer of semiconductor chip and pin described in the described plastic packaging of sealing, enhance the mobility of capsulation material, prevent from forming the defects such as space in the second plastic packaging layer between semiconductor chip and pin.Further, when filling the second plastic packaging layer, because the opening between pin communicates with the space between semiconductor chip and the space between semiconductor chip and the first surface of pin, improve the mobility of capsulation material, thus prevent from producing the defects such as space in the second plastic packaging layer.To the filling of the plastic packaging material of the opening between adjacent leads be by the second metal coupling on semiconductor chip and pin first metal coupling welding after carry out, prevent from filling after plastic packaging material before welding in the opening in advance, when carrying out reflux technique to opening in the damage of capsulation material.
Further, groove is formed in pin, the first metal coupling is formed in groove, the top surface of described first metal coupling is higher than the open surfaces of groove, the width of the first metal coupling is less than the width of groove, the both sides of the first metal coupling are made to have part recess not to be capped, when the second metal coupling on conductor chip is welded by solder layer with the first metal coupling on pin, make solder layer can cover sidewall and the lower surface of the groove of the first metal coupling both sides, make the contact area of solder layer and pin and the first metal coupling, improve adhesion and the mechanical stability between syndeton and pin that are formed between semiconductor chip and pin.
Further, formed in muscle in part between described load bearing unit some discrete run through in the second slotted eye of muscle thickness, on the one hand, the existence of the second slotted eye, follow-up by the upside-down mounting of preformed cover plate on the lead frames time, after pin in the upper metal coupling of preformed cover plate and load bearing unit is welded together, when forming the opening of filling between full pin and fill the two the second plastic packaging layer in space between described preformed cover plate and the first surface of lead frame, space between the first surface of the second slotted eye and lead frame and preformed cover plate communicates, be conducive to exhaust when capsulation material is filled, enhance the mobility of capsulation material, thus prevent from producing void defects in the two the second plastic packaging layers, on the other hand, the position of the second slotted eye on lead frame and the pin in adjacent bearing area is fixing, described second slotted eye can as by the upside-down mounting of preformed cover plate on the lead frames time alignment mark, by detecting this alignment mark, can very accurate by the upside-down mounting of preformed cover plate on the lead frames, realize the metal coupling in each integrated unit on preformed cover plate and accurately weld with the first surface of the pin in the corresponding load bearing unit of lead frame, again on the one hand, described second slotted eye between adjacent load bearing unit in muscle, extra area can not be occupied, again on the one hand, second slotted eye of the middle muscle of lead frame is empty or is filled by capsulation material, the hardness of the material in middle muscle region is reduced, when muscle forms some discrete encapsulating structures in cutting, reduces the difficulty of cutting and prevent the generation of cutting defect.
Further, some discrete the first slotted eyes running through the first plastic packaging layer thickness are formed in part first plastic packaging layer between the adjacent integrated unit of preformed cover plate, on the one hand, the stress gathered in described first slotted eye release preformed cover plate, reduces the war ping effect of preformed cover plate, on the other hand, by the upside-down mounting of preformed cover plate on the lead frames, the first upper metal coupling of the pin in the load bearing unit of the second metal coupling on the semiconductor chip in integrated unit and lead frame is welded together, formed and fill opening between full pin and between described preformed cover plate and the first surface of lead frame during the second plastic packaging layer in space, because the first slotted eye in preformed cover plate communicates with space between preformed cover plate and the first surface of lead frame, be conducive to exhaust when capsulation material is filled, enhance the mobility of capsulation material, thus prevent from producing void defects in the second plastic packaging layer, again on the one hand, additional space can not be occupied in the first plastic packaging layer of described first slotted eye between adjacent integrated unit, again on the one hand, when forming the second plastic packaging layer, second plastic packaging layer can fill full first slotted eye, packed layer and the opening between the first slotted eye and pin form the structure of similar " latch ", thus preformed cover plate and lead frame two parts are locked, when preventing preformed cover plate and lead frame from deformation occurring in the opposite direction, cause the problem that weld is bad.
Accompanying drawing explanation
Fig. 1 is the structural representation of existing QFN encapsulating structure;
Fig. 2 ~ Figure 10 is the structural representation of the forming process of embodiment of the present invention encapsulating structure.
Embodiment
When existing lead frame encapsulates, please refer to Fig. 1, first the semiconductor chip 14 wafer cutting formed one by one is needed, then metal wire 17 is formed by lead key closing process, pad 15 on semiconductor chip 14 links together with the pin 16 of surrounding by metal wire 17, finally by capsulation material 18 by semiconductor chip 14 and pin 16 plastic packaging, existing packaging technology can only realize the encapsulation of single semiconductor chip and pin, and packaging efficiency is lower.In addition, described pin 16 be around be arranged in semiconductor chip 14 around, pad 15 on semiconductor chip 14 needs to be electrically connected with the pin 16 of surrounding by plain conductor 17, and the volume that whole encapsulating structure is occupied is comparatively large, is unfavorable for the raising of encapsulating structure integrated level.
The invention provides a kind of formation method of encapsulating structure, by the upside-down mounting of some preformed cover plates on the lead frames, the second metal coupling on semiconductor chip and the first metal coupling on pin are welded together, thus achieve the integral packaging of multiple semiconductor chip and pin, improve the efficiency of encapsulation.
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail specific embodiments of the invention below in conjunction with accompanying drawing.When describing the embodiment of the present invention in detail, for ease of illustrating, schematic diagram can be disobeyed general ratio and be made partial enlargement, and described schematic diagram is example, and it should not limit the scope of the invention at this.In addition, the three-dimensional space of length, width and the degree of depth should be comprised in actual fabrication.
Fig. 2 ~ Figure 10 is the structural representation of the forming process of embodiment of the present invention encapsulating structure.
First, please refer to Fig. 2, leadframe metal layer 100 is provided.
The follow-up formation lead frame of described leadframe metal layer 100, described leadframe metal layer 100 has first surface 11 and the second surface 12 relative with first surface 11.
The material of described leadframe metal layer 100 is metal or alloy.The material of described leadframe metal layer 100 can be one or more in W, Al, Cu, Ti, Ag, Au, Pt, Ni.
Described leadframe metal layer 100 can be the metal of individual layer or the stacked structure of multiple layer metal.
Described leadframe metal layer 100 comprise some in matrix arrangement bearing area and between adjacent bearing area in muscle region (not indicating in figure), subsequently through the bearing area of the described leadframe metal layer of etching, form some discrete pins, between adjacent leads, there is opening, a side of pin is connected with middle muscle region, other three sides are unsettled, the some pins formed in each bearing area form the load bearing unit of lead frame, and the middle muscle region of fixing pin forms the middle muscle of lead frame.At formation encapsulating structure, remove muscle in lead-in wire metal level 100 by cutting, discharge the some discrete pin of each encapsulating structure.
Then, please refer to Fig. 3, etch the bearing area of described leadframe metal layer 100 (with reference to figure 2), form some discrete pins 103, have opening between adjacent leads 103, a side of pin is connected with middle muscle region, and other three sides are unsettled, the some pins formed in each bearing area form the load bearing unit of lead frame, and the middle muscle region of fixing pin forms the middle muscle of lead frame.
The forming process of described pin 103 is: on the first surface 11 of described leadframe metal layer 100, form the first patterned mask layer (not shown); With described first patterned mask layer for mask, the first surface 11 of the bearing area of etch lead frame metal level 100, forms some first openings 102 in the bearing area of leadframe metal layer 100; The second surface 12 of described leadframe metal layer 100 is formed the mask layer (not shown) of second graphical; With the mask layer of described second graphical for mask, the second surface 12 of the bearing area of etch lead frame metal level 100, some second openings 101 are formed in the bearing area of leadframe metal layer 100, first opening 102 and the second opening 101 run through mutually, first opening 102 and the second opening 101 form opening, are pin 103 between adjacent apertures.
The material of the mask layer of described first patterned mask layer or second graphical can be epoxide-resin glue or other suitable materials.The formation process of the mask layer of the first patterned mask layer or second graphical is for pasting dry film process or imprint process.The formation process of the mask layer of described first patterned mask layer or second graphical also can be spraying or spin coating proceeding.
The width of described first opening 102 is less than the width of the second opening 101, the area of the first surface 11 of the pin 103 formed is made to be greater than the area of second surface 12, because the area of the first surface 11 of pin 103 is larger, when the follow-up first surface at pin 103 forms the first metal coupling, reduce the difficulty of technique, the area of the second surface 12 of pin 103 is less, make the distance between the second surface 12 of adjacent leads 103 larger, it is follow-up when the second surface 12 of pin 103 is connected with external circuit (such as pcb board circuit), prevent the short circuit between adjacent leads 103.In addition, the width of the first opening 102 and the second opening 101 is different, and follow-up when filling full plastic packaging material in the first opening 102 and the second opening 101, make the increasing number of the contact-making surface of pin 103 and the second plastic packaging layer, pin is not easy to come off from plastic packaging material.
In other embodiments of the invention, after formation first opening 102 and the second opening 101, one deck dry film film can also be formed on the second surface 12 of described pin 103, the second surface 12 of pin 103 covers by described dry film film, during the follow-up plastic packaging material of filling in the opening, prevent plastic packaging material to the flash of the lower surface of pin 103.
In the embodiment of the present invention, etch lead frame metal level 100, after forming some discrete pins 103, lead frame is formed, described lead frame comprises first surface 11 and the second surface 12 relative with first surface 11, described lead frame has some in matrix arrangement load bearing unit and between load bearing unit for muscle in fixing load bearing unit, each load bearing unit has some discrete pins 103, has opening between adjacent leads 103.In other embodiments of the invention, after formation lead frame, also comprise: formed in muscle in the part between described load bearing unit some discrete run through in the second slotted eye of muscle thickness.It is formed that described second slotted eye can form pin at etch lead frame metal level simultaneously, and can be formed after follow-up formation first metal coupling, the size of the size of the second slotted eye or the opening between shape with pin or shape are not identical yet.On the one hand, the existence of the second slotted eye, follow-up by the upside-down mounting of preformed cover plate on the lead frames time, after pin in the upper metal coupling of preformed cover plate and load bearing unit is welded together, when forming the opening of filling between full pin and fill the two the second plastic packaging layer in space between described preformed cover plate and the first surface of lead frame, space between the first surface of the second slotted eye and lead frame and preformed cover plate communicates, be conducive to exhaust when capsulation material is filled, enhance the mobility of capsulation material, thus prevent from producing void defects in the two the second plastic packaging layers, on the other hand, the position of the second slotted eye on lead frame and the pin in adjacent bearing area is fixing, described second slotted eye can as by the upside-down mounting of preformed cover plate on the lead frames time alignment mark, by detecting this alignment mark, can very accurate by the upside-down mounting of preformed cover plate on the lead frames, realize the metal coupling in each integrated unit on preformed cover plate and accurately weld with the first surface of the pin in the corresponding load bearing unit of lead frame, again on the one hand, described second slotted eye between adjacent load bearing unit in muscle, extra area can not be occupied, again on the one hand, second slotted eye of the middle muscle of lead frame is empty or is filled by capsulation material, the hardness of the material in middle muscle region is reduced, follow-up when in cutting, muscle forms some discrete encapsulating structures, reduce the difficulty of cutting and prevent the generation of cutting defect.
Then, please refer to Fig. 4 and Fig. 5, the first surface 11 of pin 103 is formed the first metal coupling 104.
In the present embodiment, before formation first metal coupling 104, also comprise: the surface (follow-up form the surface of the first metal coupling or the first surface 11 of pin 103 thereon) of etching pin 103, formation groove 107 pin 103 in.Described groove 107 can be formed before the first opening 102 is formed or after being formed.Before formation groove 107, the first surface 11 of described pin 103 forms the 3rd patterned mask layer, the first surface 11 being pin described in mask etching 103 with described 3rd patterned mask layer, form groove 107.In other embodiments of the invention, described groove can not be formed.
After formation groove 107, the first metal coupling 104 is formed in groove 107, the top surface of described first metal coupling 104 is higher than the open surfaces of groove 107, the width of the first metal coupling 104 is less than the width of groove 107, the both sides of the first metal coupling 104 are made to have part recess 107 not to be capped, follow-up the second metal coupling on conductor chip is welded constantly with the first metal coupling on pin 103 by solder layer, make solder layer can cover sidewall and the lower surface of the groove 107 of the first metal coupling 104 both sides, make the contact area of solder layer and pin 103 and the first metal coupling 104, improve adhesion and the mechanical stability between syndeton and pin 103 that are formed between Subsequent semiconductor chip and pin.
The material of described first metal coupling 104 can be one or more in aluminium, nickel, tin, tungsten, platinum, copper, titanium, chromium, tantalum, gold, silver.
Described first metal coupling 104 comprises body and is positioned at the tip on body, the volume at described tip is less than the volume of body, the surface area of the first metal coupling 104 is increased, it is follow-up when the second metal coupling on conductor chip is welded by solder layer with the first metal coupling on pin, first metal coupling 104 is increased with the contact area of solder layer, enhance the binding ability of solder layer and the first metal coupling 104, when semiconductor chip upside-down mounting is square on the lead frames, when the second metal coupling on semiconductor chip pad is welded with the first metal coupling 104, improve the adhesion between the first metal coupling 104 and the second metal coupling and mechanical stability.In other embodiments of the invention, described first metal coupling can not have tip.
Form cuspidated first metal coupling 104 of tool and can adopt lead key closing process, form cuspidated first metal coupling 104 of not tool and can adopt lead key closing process or typography.In other embodiments of the invention, described first metal coupling 104 can also adopt other suitable technique to be formed.
The detailed process that wire bonding forms the first metal coupling 104 is: when carrying out wire bonding, and metal wire is reached its top through the bonding head (or in bonding head chopper capillary) of bonding apparatus; The body (body is spherical shape or other shape) of the metal wire melting formation metal coupling that electric spark makes to stretch out in bonding head is produced by oxyhydrogen flame or electrical system; Body is pressed together on (in the lower surface of groove 107) on the first surface 11 of pin 103 by bonding head; Bonding head moves (first surface 11 perpendicular to pin 103 moves upward) to the direction away from pin 103, exposes the part metals line on body; Chopper in bonding head cuts off metal wire, and on body, remaining metal wire forms most advanced and sophisticated.By the metal coupling that lead key closing process is formed, technique is simple, and efficiency is higher, and can not bring pollution.In other embodiments of the invention, described first metal coupling 104 can also adopt other suitable technique to be formed.
The process adopting typography to form the first metal coupling 104 is: by the first surface 11 of meshed for band web plate laminating pin 103, mesh exposes the part first surface 11 (bottom part surfaces of groove 107) of pin 103; In mesh, brush is as metal filled material (such as: scolding tin etc.); Then, remove web plate, on the first surface 11 of pin 103, (in groove 107) forms the first metal coupling 104.
In the embodiment of the present invention, pin 103 is formed the first metal coupling 104, in follow-up encapsulation process, on the one hand, the existence of the first metal coupling 104, when by semiconductor chip upside-down mounting on the lead frames time, described first metal coupling 104 can play the effect of location, on the other hand, the existence of the first metal coupling 104, compared to the second metal coupling on semiconductor chip is directly welded on pin 103, after pin 103 is formed the first metal coupling 104, when welding, the gradient steepening of the syndeton between semiconductor chip and pin 103, the area on pin 103 surface that syndeton occupies reduces, again on the one hand, the existence of the first metal coupling 104, distance between semiconductor chip and pin 103 is increased, fill opening between full pin and when filling the second plastic packaging layer in space between described preformed cover plate and the first surface of lead frame being formed, , enhance the mobility of capsulation material, prevent from forming the defects such as space in the second plastic packaging layer between semiconductor chip and pin.
Then, please refer to Fig. 6, preformed cover plate is provided, described preformed cover plate comprises in the first plastic packaging layer 205, first plastic packaging layer 205 integrated unit with some arrangements in matrix, has at least one semiconductor chip 200 in each integrated unit, described semiconductor chip 200 has some pads 201 on the surface, first plastic packaging layer 205 exposes the pad 201 on semiconductor chip, described pad 201 has on the second metal coupling 203, second metal coupling 203 and is formed with solder layer 105.
Described semiconductor chip 200 is formed by wafer cutting.In described semiconductor chip 200, there is integrated circuit (not shown), the surface of described semiconductor chip 200 has some pads 201, the pad 201 on semiconductor chip 200 surface is electrically connected with the integrated circuit in semiconductor chip, and described pad 201 is as the port of the integrated circuit in semiconductor chip 200 and external electrical connections.Some discrete semiconductor chips 200 are packaged together, form wafer-level packaging panel.
The forming process of described preformed cover plate is: provide support plate, and described support plate has cementing layer, and described cementing layer comprises the bonding zone of some arrangements in matrix; The one side with pad 201 of at least one semiconductor chip 200 is affixed on each bonding zone of described cementing layer; Form the first plastic packaging layer 205, by some semiconductor chip 200 plastic packagings together; Remove (stripping) described support plate and cementing layer, expose the pad 201 on semiconductor chip 200; Form the insulating barrier 206 covering described first plastic packaging layer 205, semiconductor chip 200 and pad 201, there is in described insulating barrier 206 first opening of the part surface of exposed pad 201; On described insulating barrier 206 and the sidewall of the first opening and bottom form conductive metal layer; Described conductive metal layer is formed photoresist mask, there is in described photoresist mask the second opening of the conductive metal layer on exposure first opening; Adopt electroplating technology to fill metal in described second opening, form metal column (the second metal coupling 203), metal column is formed solder layer 105; Remove described photoresist mask; The conductive metal layer of etching removal second metal coupling 203 both sides, forms convex lower metal layer 202 in the bottom of the second metal coupling 203.After formation solder layer, solder layer can be made spherical in shape by reflux technique.
By the first plastic packaging layer 205, some semiconductor chips 200 are packaged together, form preformed cover plate, each preformed cover plate has the integrated unit (not indicating in figure) of some matrixes arrangement, the position of each integrated unit is corresponding with the position of the bonding zone on cementing layer 301, and the semiconductor chip that each bonding zone on described cementing layer 301 is pasted is the integrated semiconductor chip in each integrated unit in preformed cover plate.Between the adjacent integrated unit of described preformed cover plate, region is cut zone.
Each bonding zone of cementing layer has at least one semiconductor chip 200, when the quantity of semiconductor chip 200 is greater than 1, the kind of semiconductor chip 200 can be identical or not identical.Have at least one semiconductor chip 200 in each integrated unit in corresponding preformed cover plate, when the quantity of semiconductor chip 200 is greater than 1, the kind of semiconductor chip 200 can be identical or not identical.
Described support plate can be glass substrate, silicon substrate or metal substrate.
The available material of cementing layer has multiple, and in the present invention's preferred embodiment, cementing layer adopts UV glue.UV glue be a kind of can to the aitiogenic glueing material of the UV-irradiation of special wavelength.UV glue can be divided into two kinds according to the change of viscosity after UV-irradiation, one is that UV solidifies glue, namely living radical or cation is produced after the light trigger in material or sensitising agent absorb ultraviolet light under ultraviolet irradiation, trigger monomer is polymerized, be cross-linked and connect a chemical reaction, ultraviolet cured adhesive is made to be solid-state by liquid conversion within the several seconds, thus the body surface bonding that will be in contact with it; Another kind is UV glue is very high without viscosity during Ultraviolet radiation, and the crosslinking chemical bond after UV-irradiation in material is interrupted and causes viscosity to decline to a great extent or disappear.Here namely the UV glue that cementing layer adopts be the latter.
The method that support plate is formed cementing layer can be such as be coated on support plate by cementing layer by the method such as spin coating or printing.Such method is well known to those skilled in the art in the art of semiconductor manufacturing, does not repeat them here.
The material of described first plastic packaging layer 205 is resin, and described resin can be epoxy resin, polyimide resin, benzocyclobutane olefine resin or polybenzoxazoles resin; Described resin also can be polybutylene terephthalate, Merlon, PETG, polyethylene, polypropylene, polyolefin, polyurethane, polyolefin, polyether sulfone, polyamide, polyurethane, ethylene-vinyl acetate copolymer or polyvinyl alcohol; Described first plastic packaging layer 205 can also be other suitable capsulation materials.
The formation process of described first plastic packaging layer 205 is Shooting Technique (injectionmolding), turns and mould technique (transfermolding) or typography.Described first plastic packaging layer 205 can also adopt other technique.
Described second metal coupling 203 can be metal column, and the material of described metal column is aluminium, nickel, tungsten, platinum, copper, titanium, chromium, tantalum, ashbury metal, gold or silver-colored.Described solder layer 105 can be soldered ball, the material of described solder layer 105 is tin or ashbury metal, and ashbury metal can be one or more in tin silver, tin plumbous, SAC, tin silver zinc, tin zinc, tin bismuth indium, tin indium, Sillim, tin copper, tin zinc indium or tin silver antimony.Described second metal coupling 203 and solder layer 105 are formed by electroplating technology.
By multiple semiconductor chip 200 is packaged together, form preformed cover plate, follow-up can by the upside-down mounting of preformed cover plate on the lead frames, the second metal coupling 203 on the pad 201 of the semiconductor chip 200 in integrated unit is welded together with the first metal coupling on pin, compare the method for packing that the pad on existing single semiconductor chip is connected by metal wire with pin, method for packing of the present invention realizes the integral packaging of multiple semiconductor chip 200 and pin, improve the efficiency of encapsulation, and the connected mode of metal coupling is compared to the connected mode of metal wire, the area of the transverse direction occupied reduces, be conducive to the integrated level improving whole encapsulating structure.
In other embodiments of the invention, after formation preformed cover plate, some discrete the first slotted eyes running through the first plastic packaging layer thickness can also be formed in part first plastic packaging layer between the adjacent integrated unit of preformed cover plate, in the present embodiment, described first slotted eye also runs through the insulating barrier between corresponding adjacent integrated unit.The existence of the first slotted eye, on the one hand, the stress gathered in described first slotted eye release preformed cover plate, reduces the war ping effect of preformed cover plate, on the other hand, follow-up by the upside-down mounting of preformed cover plate on the lead frames, the first upper metal coupling of the pin in the load bearing unit of the second metal coupling on the semiconductor chip in integrated unit and lead frame is welded together, formed and fill opening between full pin and between described preformed cover plate and the first surface of lead frame during the second plastic packaging layer in space, because the first slotted eye in preformed cover plate communicates with space between preformed cover plate and the first surface of lead frame, be conducive to exhaust when capsulation material is filled, enhance the mobility of capsulation material, thus prevent from producing void defects in the second plastic packaging layer, again on the one hand, additional space can not be occupied in the first plastic packaging layer of described first slotted eye between adjacent integrated unit, again on the one hand, during follow-up formation second plastic packaging layer, second plastic packaging layer can fill full first slotted eye, packed layer and the opening between the first slotted eye and pin form the structure of similar " latch ", thus preformed cover plate and lead frame two parts are locked, when preventing preformed cover plate and lead frame from deformation occurring in the opposite direction, cause the problem that weld is bad.Described first slotted eye can pass through punching or bore process or Sheet Metal Forming Technology and be formed.In other embodiments of the invention, when aforementioned employing screen printing or Shooting Technique form the first plastic packaging layer, the part-structure of Printing screen or injection molding mould plate is covered the place needing formation first slotted eye, after first plastic packaging layer is formed, removing Printing screen or injection molding mould plate, some discrete the first slotted eyes running through the first plastic packaging layer thickness can be formed, subsequently through the insulating barrier that etching or exposure removal first slotted eye cover in part first plastic packaging layer directly between the adjacent integrated unit of preformed cover plate.Then, please refer to Fig. 7, by the upside-down mounting of described preformed cover plate on the first surface 11 of lead frame, make the integrated unit in preformed cover plate corresponding with the load bearing unit in lead frame, the second metal coupling 203 on semiconductor chip 200 in integrated unit is welded together by solder layer 105 with the first metal coupling 105 on the pin 103 in load bearing unit, form the encapsulation unit of some matrixes arrangement, each encapsulation unit comprises an integrated unit and the load bearing unit corresponding with this integrated unit.
Concrete, first by preformed cover plate upside-down mounting side on the lead frames, make the integrated unit in preformed cover plate corresponding with the load bearing unit in lead frame, the solder layer 105 on the second metal coupling 203 surface on semiconductor chip 200 is contacted with the first metal coupling 104 on pin 103; Reflux technique is carried out to described solder layer 105, solder layer 105 is melted the second metal coupling 203 and the first metal coupling 104 are welded together; Whole encapsulating structure is cooled.
In the present embodiment, described solder layer 105 also covers sidewall and the lower surface of the groove 107 (with reference to figure 5) of the first metal coupling 104 both sides, because groove 107 has bottom and sidewall, when solder layer covers sidewall and the lower surface of the groove 107 (with reference to figure 5) of the first metal coupling 104 both sides, the contact area of solder layer 105 and the first metal coupling 104 and pin 103 is increased, follow-uply between semiconductor chip and pin 103, be formed with the first metal coupling, during the syndeton that solder layer and the second metal coupling are formed, improve adhesion and the mechanical stability between syndeton and pin 103 that are formed between semiconductor chip and pin.
In other embodiments of the present invention, described solder layer is except covering sidewall and the lower surface of the groove of the first metal coupling both sides, described solder layer also covers the part surface of the pin of the first metal coupling both sides, when forming syndeton, adhesion and mechanical stability between syndeton and pin 103 are improved further.
Because the bottom of solder layer 105 and the groove of the first metal coupling 104 both sides and sidewall contact, the material of pin 103 is metal, when refluxing, the sidewall of groove can have draw to solder layer, makes the solder layer after refluxing still can cover sidewall and the bottom of the groove of the first metal coupling 104 both sides of groove.
By semiconductor chip 200 upside-down mounting side on the lead frames, by the first metal coupling 104, pad 201 on semiconductor chip 200 is electrically connected with pin 103 by the syndeton that solder layer 105 and the second metal coupling 203 are formed, pin to be arranged on around single semiconductor chip then by method for packing that the pad on semiconductor chip is connected with pin by plain conductor relative to existing, the encapsulating structure of the method for packing formation of the embodiment of the present invention realizes the integral packaging of multiple semiconductor chip 200 and pin, improve the efficiency of encapsulation, the area of transverse direction that encapsulating structure of the present invention occupies in addition reduces, the small volume of whole encapsulating structure, and this method for packing can realize the encapsulation of the wafer scale of lead frame structure, improve the integrated level of encapsulating structure.
Then, please refer to Fig. 8, fill the opening between full pin 103 and second plastic packaging layer 208, the second plastic packaging layer 208 of filling space between described preformed cover plate and the first surface 11 of lead frame exposes the second surface of pin.。
Region between opening (comprising the first opening and the second opening) between the full pin 103 of described second plastic packaging layer 208 filling, the full adjacent semiconductor chips 200 of filling and between the first surface 11 of semiconductor chip 200 and pin 103, second plastic packaging layer 208 also fills the opening (the first opening and the second opening) between full pin 103, the bottom-exposed of the second plastic packaging layer 208 go out pin away from the first metal coupling 104 1 side surface (second surface 12).When filling the second plastic packaging layer 208, because the opening between pin 103 communicates with the space between semiconductor chip 200 and the first surface 11 of pin 103, improve the mobility of capsulation material, thus prevent from producing the defects such as space in the second plastic packaging layer 208.In addition, carry out after the second metal coupling 203 on semiconductor chip 200 and the first metal coupling 104 on pin 103 are welded to the filling of the plastic packaging material of the opening between adjacent leads 103, prevent from filling after plastic packaging material before welding in the opening in advance, when carrying out reflux technique to opening in the damage of capsulation material.
Described second plastic packaging layer 208 for the protection of with insulation package structure, the material of described second plastic packaging layer 208 is resin, and described resin can be epoxy resin, polyimide resin, benzocyclobutane olefine resin or polybenzoxazoles resin; Described resin also can be polybutylene terephthalate, Merlon, PETG, polyethylene, polypropylene, polyolefin, polyurethane, polyolefin, polyether sulfone, polyamide, polyurethane, ethylene-vinyl acetate copolymer or polyvinyl alcohol; Described second plastic packaging layer 208 can also be other suitable capsulation materials.
The formation process of described second plastic packaging layer 208 is Shooting Technique or turns and mould technique (transfermolding).The formation process of described second plastic packaging layer 208 can also be other suitable techniques.
In another embodiment of the invention, please refer to Fig. 9, some discrete the first slotted eyes 211 running through the first plastic packaging layer thickness are formed in part first plastic packaging layer 205 between the adjacent integrated unit of described preformed cover plate and insulating barrier 206, when forming the second plastic packaging layer 208 of filling completely space between described preformed cover plate and the first surface 11 of lead frame, because the first slotted eye 211 in preformed cover plate communicates with space between preformed cover plate and the first surface 11 of lead frame, be conducive to exhaust when the second capsulation material is filled, enhance the mobility of capsulation material, thus prevent from producing void defects in the second plastic packaging layer.In the present embodiment, when filling the second plastic packaging layer 208, described second plastic packaging layer 208 can fill full first slotted eye 211 simultaneously.In other embodiments of the invention, described first slotted eye can not be filled or be partially filled to the second plastic packaging layer.
In another embodiment of the invention, be formed some discrete when running through the second slotted eye of middle muscle thickness in part between the load bearing unit of described lead frame in muscle, when formation second plastic packaging layer, the mobility of capsulation material improves further, prevents from forming the defects such as space in the two the second plastic packaging layers.
Finally, please refer to Fig. 8 and Figure 10, cut along encapsulation unit, form some discrete encapsulating structures 13.
Carry out cutting along encapsulation unit to comprise: the middle muscle of the first plastic packaging layer, the second plastic packaging layer and lead frame between cutting adjacent semiconductor chips 200, concrete cutting technique please refer to existing cutting technique, does not repeat them here.
Described discrete encapsulating structure 13, comprising: some discrete pins 103, have opening between adjacent leads 103; Be positioned at first metal coupling 104 on the surface of pin 103; Be positioned at the top of the first metal coupling 104 and the solder layer 105 of sidewall surfaces; Semiconductor chip 200, semiconductor chip 200 has some pad 201, first plastic packaging layers 205 and seals described semiconductor chip 200, first plastic packaging layer 205 and expose pad 201 on semiconductor chip 200, pad 201 is formed with the second metal coupling 203; On the lead frames, the second metal coupling 203 on semiconductor chip 200 welds together with the first metal coupling 104 on pin 103 in semiconductor chip 200 upside-down mounting; The second plastic packaging layer in space between the first surface 11 of filling opening between full pin 103 and semiconductor chip 200 and pin, the second plastic packaging layer 208 exposes the second surface 12 (surface away from the first metal coupling 104) of pin 103.
Present invention also offers a kind of encapsulating structure, please refer to Fig. 8, comprising:
Lead frame, described lead frame comprises first surface 11 and the second surface 12 relative with first surface 11, described lead frame has some in matrix arrangement load bearing unit and between load bearing unit for muscle in fixing load bearing unit, each load bearing unit has some discrete pins 103, has opening between adjacent leads 103;
Be positioned at the first metal coupling 104 of the first surface of pin 103;
Be positioned at the top of the first metal coupling 104 and the solder layer 105 of sidewall surfaces;
Preformed cover plate, described preformed cover plate comprises the first plastic packaging layer 205, there is in first plastic packaging layer 205 integrated unit of some arrangements in matrix, there is in each integrated unit at least one semiconductor chip 200, described semiconductor chip 200 has some pads 201 on the surface, first plastic packaging layer 205 exposes the pad 201 on semiconductor chip 200, described pad 201 has on the second metal coupling 203, second metal coupling 203 and is formed with solder layer 105;
The upside-down mounting of preformed cover plate is on the first surface 11 of lead frame, make the integrated unit in preformed cover plate corresponding with the load bearing unit in lead frame, the second metal coupling 203 on semiconductor chip 200 in integrated unit is welded together by solder layer 105 with the first metal coupling 104 on pin 103 in load bearing unit, form the encapsulation unit of some matrixes arrangement, each encapsulation unit comprises a load bearing unit and the integrated unit corresponding with this load bearing unit;
Fill the opening between full pin 103 and second plastic packaging layer 208, the second plastic packaging layer 208 of filling space between described preformed cover plate and the first surface 11 of lead frame 103 exposes the second surface 12 of pin 103.
Concrete, described pin 103 has first surface 11 and the second surface 12 relative with first surface 11, described opening comprises the first opening and the second opening that mutually run through, the width of described first opening is less than the width of the second opening, and described first metal coupling is positioned on the surface away from the second opening of pin.
Be formed with groove in described pin 103 first surface 11, the first metal coupling 104 is positioned at groove.
The width of described first metal coupling 104 is less than the width of groove, and described solder layer 105 also covers sidewall and the lower surface of the groove of the first metal coupling 104 both sides.
In other embodiments of the present invention, described solder layer also covers the sidewall of the groove of the first metal coupling both sides and the part surface of lower surface and pin.
Described second metal coupling 203 is soldered ball or metal column, or comprises the soldered ball at metal column and metal column top.
Region between opening between the full adjacent leads 103 of described solder layer 105 filling, the full adjacent semiconductor chips 200 of filling and the region between the pad 201 of semiconductor chip 200 and the first surface 11 of pin 103.
The second surface of described pin 103 also has weld layer (not shown).The material of described weld layer is one or more in nickel, platinum, gold, palladium, silver or tin.
The surface of described semiconductor chip 200 also has separator 206, there is in separator 206 opening on expose portion pad 201 surface, have convex lower metal layer 202 in opening and on part separator 206, metal coupling 203 is connected with pad 201 by convex lower metal layer 202.
Also comprise: some discrete the first slotted eye running through the first plastic packaging layer thickness formed in the part first plastic packaging layer between the adjacent integrated unit of described preformed cover plate.
Also comprise: formed in muscle in the part between the load bearing unit of described lead frame some discrete run through in the second slotted eye of muscle thickness.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (10)
1. a formation method for encapsulating structure, is characterized in that, comprising:
Lead frame is provided, described lead frame comprises first surface and the second surface relative with first surface, described lead frame has some in matrix arrangement load bearing unit and between load bearing unit for muscle in fixing load bearing unit, each load bearing unit has some discrete pins, has opening between adjacent leads;
The first metal coupling is formed at the first surface of pin;
Preformed cover plate is provided, described preformed cover plate comprises the first plastic packaging layer, there is in first plastic packaging layer the integrated unit of some arrangements in matrix, there is in each integrated unit at least one semiconductor chip, described semiconductor chip surface have some pads, first plastic packaging layer exposes the pad on semiconductor chip, described pad has the second metal coupling, and the second metal coupling is formed with solder layer;
By the upside-down mounting of preformed cover plate on the first surface of lead frame, make the integrated unit in preformed cover plate corresponding with the load bearing unit in lead frame, the first metal coupling on pin in the second metal coupling on semiconductor chip in integrated unit and load bearing unit is welded together by solder layer, forms the encapsulation unit of some matrixes arrangement;
Filling is expired the opening between pin and is filled the second plastic packaging layer in space between described preformed cover plate and the first surface of lead frame, and the second plastic packaging layer exposes the second surface of pin;
Cut along encapsulation unit, form some discrete encapsulating structures.
2. the formation method of encapsulating structure as claimed in claim 1, it is characterized in that, the forming process of described lead frame is: provide leadframe metal layer, described leadframe metal layer comprise some in matrix arrangement bearing area and between adjacent bearing area in muscle region; Etch the bearing area of described leadframe metal layer, form some discrete pins, between adjacent leads, there is opening, a side of pin is connected with middle muscle region, other three sides are unsettled, the some pins formed in each bearing area form the load bearing unit of lead frame, and the middle muscle region of fixing pin forms the middle muscle of lead frame.
3. the formation method of encapsulating structure as claimed in claim 2, it is characterized in that, described opening comprises the first opening and the second opening that mutually run through, and the width of described first opening is less than the width of the second opening, and described first metal coupling is positioned on the surface of pin away from the second opening.
4. the formation method of encapsulating structure as claimed in claim 3, it is characterized in that, described first opening with the forming process of the second opening is: described leadframe metal layer comprises first surface and the second surface relative with first surface, the first surface of the bearing area of etch lead frame metal level, forms some first openings in the bearing area of leadframe metal layer; The second surface of the bearing area of etch lead frame metal level, forms some second openings in the bearing area of leadframe metal layer, and the first opening and the second opening run through mutually, and the first opening and the second opening form opening.
5. the formation method of encapsulating structure as claimed in claim 1, is characterized in that, the surface of etching pin, forms groove, form the first metal coupling in groove in pin, and the top surface of described first metal coupling is higher than the surface of slot opening.
6. the formation method of encapsulating structure as claimed in claim 5, it is characterized in that, the width of described first metal coupling is less than the width of groove.
7. the formation method of encapsulating structure as claimed in claim 5, it is characterized in that, described solder layer also covers sidewall and the lower surface of the groove of the first metal coupling both sides.
8. the formation method of encapsulating structure as claimed in claim 5, it is characterized in that, described solder layer also covers the sidewall of the groove of the first metal coupling both sides and the part surface of lower surface and pin.
9. the formation method of encapsulating structure as claimed in claim 1, is characterized in that, also comprise: form some discrete the first slotted eyes running through the first plastic packaging layer thickness in the part first plastic packaging layer between the adjacent integrated unit of described preformed cover plate.
10. the formation method of encapsulating structure as claimed in claim 1, is characterized in that, also comprise: formed in muscle in the part between described load bearing unit some discrete run through in the second slotted eye of muscle thickness.
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| TWI665774B (en) | 2018-08-15 | 2019-07-11 | 矽品精密工業股份有限公司 | Electronic package and manufacturing method thereof |
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| CN109037183A (en) * | 2018-06-13 | 2018-12-18 | 南通通富微电子有限公司 | A kind of semiconductor chip packaging array and semiconductor chip packaging device |
| CN113504703A (en) * | 2021-07-23 | 2021-10-15 | 赛莱克斯微系统科技（北京）有限公司 | Manufacturing method of micro coaxial structure |
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Address after: Jiangsu province Nantong City Chongchuan road 226006 No. 288 Patentee after: Tongfu Microelectronics Co., Ltd. Address before: 226006 Jiangsu Province, Nantong City Chongchuan District Chongchuan Road No. 288 Patentee before: Fujitsu Microelectronics Co., Ltd., Nantong |