CN103794546A - Method for manufacturing semiconductor device - Google Patents

Abstract

The invention provides a method for manufacturing a semiconductor device, comprising: providing a semiconductor substrate, on which a gate structure is formed, and forming Σ-shaped grooves in the semiconductor substrate on both sides of the gate structure; A seed layer is formed at the bottom of the Σ-shaped groove; an embedded silicon germanium layer is formed on the seed layer to completely fill the Σ-shaped groove; a SiCB cap layer is formed on the embedded silicon germanium layer . According to the present invention, a SiCB layer is formed on the embedded silicon germanium layer as a cap layer, the carbon atoms therein can weaken the diffusion of boron atoms into the semiconductor substrate, and at the same time, the cap layer composed of the SiCB layer can The stability of the salicide composed of nickel silicon formed subsequently is improved, thereby improving the electrical performance of the device.

Description

A method of manufacturing a semiconductor device

technical field

The invention relates to a semiconductor manufacturing process, in particular to a method for improving the quality of a cap layer formed on an embedded silicon germanium layer.

Background technique

In the advanced CMOS device manufacturing process, the embedded silicon germanium process is often used to improve the performance of the PMOS part of the CMOS device.

The process sequence of forming an embedded silicon germanium layer in the source/drain region of PMOS is: provide a semiconductor substrate, form a gate structure and sidewall structures on both sides of the gate structure on the semiconductor → on the sidewall structure Forming grooves in the semiconductor substrates on both sides → using a selective epitaxial growth process to form an embedded silicon germanium layer in the groove → forming a cap layer on the embedded silicon germanium layer, the The cap layer is used to form salicide before the subsequent metal interconnection, and at the same time, it can also avoid stress release of the silicon germanium layer caused by the subsequent process. If the cap layer is a monocrystalline silicon layer, the yield per unit time will decrease due to its low growth rate, and the quality of the device will be affected due to its poor surface flatness; if the cap layer is borosilicate ( SiB) layer, compared with the single crystal silicon layer, has faster growth rate, better surface flatness, and lower self-resistance, but the boron atoms in it can easily diffuse into the substrate (especially the channel region), causing the device performance degradation.

Therefore, it is necessary to propose a method to improve the quality of the cap layer formed on the embedded silicon germanium layer, so as to further improve the performance of the CMOS device.

Contents of the invention

Aiming at the deficiencies of the prior art, the present invention provides a method for manufacturing a semiconductor device, comprising: providing a semiconductor substrate, on which a gate structure is formed, and in the semiconductor substrate on both sides of the gate structure forming a Σ-shaped groove; forming a seed layer at the bottom of the Σ-shaped groove; forming an embedded germanium-silicon layer on the seed layer to completely fill the Σ-shaped groove; A SiCB cap layer is formed on the silicon layer.

Further, the Σ-shaped groove is formed by first dry etching and then wet etching.

Further, the seed layer is a silicon germanium layer with low germanium content.

Further, the embedded silicon germanium layer is formed by using a selective epitaxial growth process.

Further, the SiCB cap layer is formed by an in-situ epitaxial growth process.

Further, the doping dose of boron atoms in the SiCB cap layer is 5.0×e ¹⁴ -5.0×e ²⁰ atom/cm ² .

Further, the doping dose of carbon atoms in the SiCB cap layer is 5.0×e ¹⁴ -5.0×e ²⁰ atom/cm ² .

Further, the gate structure includes a gate dielectric layer, a gate material layer and a gate hard mask layer stacked in sequence.

Further, offset spacer structures close to the gate structure are formed on both sides of the gate structure.

Further, the offset spacer structure includes at least one oxide layer and/or at least one nitride layer.

According to the present invention, a SiCB layer is formed on the embedded silicon germanium layer as a cap layer, the carbon atoms therein can weaken the diffusion of boron atoms into the semiconductor substrate, and at the same time, the cap layer composed of the SiCB layer can The stability of the salicide composed of nickel silicon formed subsequently is improved, thereby improving the electrical performance of the device.

Description of drawings

The following drawings of the invention are hereby included as part of the invention for understanding the invention. The accompanying drawings illustrate embodiments of the invention and description thereof to explain principles of the invention.

In the attached picture:

1A-FIG. 1E are schematic cross-sectional views of each step of the method for improving the quality of the cap layer formed on the embedded silicon germanium layer proposed by the present invention;

FIG. 2 is a flowchart of a method for improving the quality of a cap layer formed on an embedded SiGe layer proposed by the present invention.

Detailed ways

In the following description, numerous specific details are given in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without one or more of these details. In other examples, some technical features known in the art are not described in order to avoid confusion with the present invention.

In order to thoroughly understand the present invention, detailed steps will be presented in the following description to explain the method proposed by the present invention to improve the quality of the cap layer formed on the embedded SiGe layer. Obviously, the practice of the invention is not limited to specific details familiar to those skilled in the semiconductor arts. Preferred embodiments of the present invention are described in detail below, however, the present invention may have other embodiments besides these detailed descriptions.

It should be understood that when the terms "comprising" and/or "comprising" are used in this specification, they indicate the presence of the features, integers, steps, operations, elements and/or components, but do not exclude the presence or addition of one or Multiple other features, integers, steps, operations, elements, components and/or combinations thereof.

Next, the detailed steps of the method for improving the quality of the cap layer formed on the embedded SiGe layer proposed by the present invention will be described with reference to FIG. 1A-FIG. 1E and FIG. 2 .

Referring to FIG. 1A-FIG. 1E , there are shown schematic cross-sectional views of various steps of the method for improving the quality of the cap layer formed on the embedded SiGe layer proposed by the present invention.

First, as shown in FIG. 1A , a semiconductor substrate 100 is provided, and the constituent material of the semiconductor substrate 100 may be undoped single crystal silicon, single crystal silicon doped with impurities, silicon-on-insulator (SOI) or the like. As an example, in this embodiment, the semiconductor substrate 100 is made of single crystal silicon. Isolation structures and various well structures are formed in the semiconductor substrate 100 , which are omitted from illustration for simplicity. For PMOS, an N well (not shown in the figure) can also be formed in the semiconductor substrate 200, and before forming the gate structure, a small dose of boron implantation can be performed on the entire N well to adjust the PMOS The threshold voltage V _th .

A gate structure 101 is formed on the semiconductor substrate 100. As an example, the gate structure 101 may include a gate dielectric layer, a gate material layer and a gate hard mask layer stacked sequentially from bottom to top. . The gate dielectric layer may include an oxide such as a silicon dioxide (SiO ₂ ) layer. The gate material layer may comprise one or more of a polysilicon layer, a metal layer, a conductive metal nitride layer, a conductive metal oxide layer and a metal silicide layer, wherein the constituent material of the metal layer may be tungsten (W ), nickel (Ni) or titanium (Ti); the conductive metal nitride layer may include a titanium nitride (TiN) layer; the conductive metal oxide layer may include an iridium oxide (IrO ₂ ) layer; the metal silicide layer may include Titanium silicide (TiSi) layer. The gate hard mask layer may include one or more of an oxide layer, a nitride layer, an oxynitride layer, and amorphous carbon, where the oxide layer may include borophosphosilicate glass (BPSG), phosphosilicate glass ( PSG), tetraethyl tetrasilicate (TEOS), undoped silica glass (USG), spin-on-glass (SOG), high-density plasma (HDP) or spin-on-dielectric (SOD); the nitride layer can include nitride The silicon (Si ₃ N ₄ ) layer; the oxynitride layer may include a silicon oxynitride (SiON) layer.

In addition, as an example, offset spacer structures 102 located on both sides of the gate structure 101 and close to the gate structure 101 are further formed on the semiconductor substrate 100 . Wherein, the offset spacer structure 102 may include at least one oxide layer and/or at least one nitride layer.

Next, as shown in FIG. 1B , a Σ-shaped groove 103 is formed in the semiconductor substrate 100 through the process window formed by the offset spacer structure 102 . Generally, the Σ-shaped groove 103 is formed by dry etching first and then wet etching, and the specific steps of this process are as follows: first, the semiconductor substrate between the offset spacer structures 102 is longitudinally etched by a dry etching process 100 to form a silicon groove; and then use a wet etching process to etch the silicon groove to form the Σ-shaped groove 103 .

Next, as shown in FIG. 1C , a seed layer 104 is formed at the bottom of the Σ-shaped groove 103 . The seed layer 104 is formed by various suitable process techniques familiar to those skilled in the art, such as selective epitaxial growth process. The seed layer 104 may be a silicon germanium layer with low germanium content. In addition, since enough space needs to be reserved for the embedded silicon germanium layer to be formed later, the seed layer 104 should not be too thick, so as not to fill up the entire Σ-shaped groove 103 .

Next, as shown in FIG. 1D , an embedded SiGe layer 105 is formed on the seed layer 104 by a selective epitaxial growth process to completely fill the Σ-shaped groove 103 . The selective epitaxial growth process can adopt low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), ultra-high vacuum chemical vapor deposition (UHVCVD), rapid thermal chemical vapor deposition (RTCVD) and molecular beam epitaxy ( MBE) in one.

Next, as shown in FIG. 1E , a cap layer 106 is formed on the embedded SiGe layer 105 . The cap layer 106 is formed by an in-situ epitaxial growth process, that is, the epitaxial growth process used to form the cap layer 106 and the epitaxial growth process used to form the embedded SiGe layer 105 are performed in the same reaction chamber. The cap layer 106 is a monocrystalline silicon layer (SiCB layer) doped with boron and carbon, wherein the doping dose of the boron atoms is 5.0×e ¹⁴ -5.0×e ²⁰ atom/cm ² , and the carbon atoms The doping dose is 5.0×e ¹⁴ -5.0×e ²⁰ atom/cm ² .

So far, all the process steps implemented by the method according to the exemplary embodiment of the present invention are completed, and then, the fabrication of the entire semiconductor device can be completed through a subsequent process, which is exactly the same as the traditional semiconductor device processing process. According to the present invention, a SiCB layer is formed on the embedded silicon germanium layer 105 as a cap layer, and the carbon atoms therein can weaken the diffusion of boron atoms into the semiconductor substrate 100, and at the same time, the cap layer formed by the SiCB layer can Improves the stability of a salicide composed of nickel silicon (NiSi) that is subsequently formed thereon, thereby improving the electrical performance of the device.

All the process steps of the method for improving the quality of the cap layer formed on the embedded silicon germanium layer in the above implementation of the present invention are illustrated by taking the PMOS transistor as an example, and those skilled in the art can understand that the PMOS transistor here can be is the PMOS portion of the CMOS transistor.

Referring to FIG. 2 , it shows a flow chart of the method for improving the quality of the cap layer formed on the embedded silicon germanium layer proposed by the present invention, which is used to briefly show the flow of the entire manufacturing process.

In step 201, a semiconductor substrate is provided, a gate structure is formed on the semiconductor substrate, and Σ-shaped grooves are formed in the semiconductor substrate on both sides of the gate structure;

In step 202, a seed layer is formed at the bottom of the Σ-shaped groove;

In step 203, an embedded silicon germanium layer is formed on the seed layer to completely fill the Σ-shaped groove;

In step 204, a SiCB cap layer is formed on the embedded silicon germanium layer.

The present invention has been described through the above-mentioned embodiments, but it should be understood that the above-mentioned embodiments are only for the purpose of illustration and description, and are not intended to limit the present invention to the scope of the described embodiments. In addition, those skilled in the art can understand that the present invention is not limited to the above-mentioned embodiments, and more variations and modifications can be made according to the teachings of the present invention, and these variations and modifications all fall within the claimed scope of the present invention. within the range. The protection scope of the present invention is defined by the appended claims and their equivalent scope.

Claims (10)

1. A method of manufacturing a semiconductor device, comprising: A semiconductor substrate is provided, a gate structure is formed on the semiconductor substrate, and Σ-shaped grooves are formed in the semiconductor substrate on both sides of the gate structure; forming a seed layer at the bottom of the Σ-shaped groove; forming an embedded silicon germanium layer on the seed layer to completely fill the Σ-shaped groove; A SiCB cap layer is formed on the embedded silicon germanium layer. 2 . The method according to claim 1 , wherein the Σ-shaped groove is formed by first dry etching and then wet etching. 3 . 3. The method according to claim 1, wherein the seed layer is a silicon germanium layer with a low germanium content. 4. The method according to claim 1, characterized in that the embedded silicon germanium layer is formed by a selective epitaxial growth process. 5. The method according to claim 1, characterized in that the SiCB cap layer is formed by an in-situ epitaxial growth process. The method according to claim 1 or 5, characterized in that the doping dose of boron atoms in the SiCB cap layer is 5.0×e ¹⁴ -5.0×e ²⁰ atom/cm ² . 7. The method according to claim 1 or 5, characterized in that the doping dose of carbon atoms in the SiCB cap layer is 5.0×e ¹⁴ -5.0×e ²⁰ atom/cm ² . 8. The method according to claim 1, wherein the gate structure comprises a gate dielectric layer, a gate material layer and a gate hard mask layer stacked in sequence. 9 . The method according to claim 1 , wherein offset spacer structures close to the gate structure are formed on both sides of the gate structure. 10. The method according to claim 9, wherein the offset spacer structure comprises at least one oxide layer and/or at least one nitride layer.

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