CN103795521B - Clock recovery method and device for transmitting EI signals based on Ethernet - Google Patents

Abstract

The invention relates to a clock recovery method for transmitting E1 signals based on Ethernet, including storing E1 data packets from Ethernet into a FIFO memory buffer, and reading with a missing-tooth clock CLK _G , and the FIFO memory outputs the E1 data of clock-missing teeth; The E1 data with missing teeth in the clock is stored in the elastic memory, and the PLL outputs a synchronization signal to the elastic memory, and the output of the PLL is used as its feedback input, and the PLL controls the output clock by monitoring the difference between the read and write pointers of the elastic memory Frequency, if the difference between the read and write pointers is greater than the set value, reduce the clock frequency output by the phase-locked loop, otherwise, increase the clock frequency output by the phase-locked loop, and the elastic memory will output clock-smooth E1 data. The invention also discloses a clock recovery device for transmitting E1 signals based on the Ethernet. The clock is recovered by two-level buffer adjustment to reduce phase drift, smooth tooth loss, and recover the clock that meets the relevant requirements of ITU-T G.823, and achieve better roaming performance indicators without changing the frame structure.

Description

A clock recovery method and device for transmitting E1 signals based on Ethernet

technical field

The invention relates to the technical field of communication and information system network transmission, in particular to a clock recovery method and device for transmitting E1 signals based on Ethernet.

Background technique

In the new-generation communication network based on IP, in order to realize multi-service transmission, at the sending end, the real-time service (TDM) is packaged and processed so that it becomes a data packet of an Ethernet packet, and then transmitted; at the receiving end, in order to recover In the original TDM business, statistics and jitter elimination are performed on the data, so as to obtain the timing information of the code stream. In the TDMoIP system, the signal that needs to be sent at the sending end is a standard E1 signal. In order to transmit in the Ethernet, the E1 signal is split and encapsulated to make it into a fixed-sized Ethernet packet. The original E1 signal All the timing information in the receiver is lost, the signal received by the receiving end does not contain any timing information, and the jitter of the data becomes random, which requires special processing at the receiving end to recover the clock of the E1 signal.

Generally, when the multiplexing equipment receives the data bit stream, it uses first-order and second-order low-pass filters on the phase-locked loop to provide smoothing to obtain clock recovery that meets the specifications. However, the disadvantage of the clock phase detector used in the PLL is that the resolution can only reach one bit. When the recovered clock is very close to the actual value, it takes a long time for the phase difference to accumulate to one bit, which will cause drift , it is difficult to meet the requirements of roaming specifications. In addition, due to the characteristics of Ethernet, the time when data packets arrive at the destination will vary randomly, and may even drop packets. In addition, the packet data is a large block burst data. When a packet arrives, it is hundreds or even thousands of bytes. The change of the write pointer of the elastic memory is jumpy. In this case, the phase change detection filter cannot be changed from The detection of pointer difference is accomplished through a general low-pass filtering method.

Contents of the invention

The primary purpose of the present invention is to provide a clock recovery method for transmitting E1 signals based on Ethernet, which can achieve better roaming performance index without changing the frame structure.

In order to achieve the above object, the present invention adopts the following technical scheme: a kind of clock recovery method based on Ethernet transmission E1 signal, this method comprises the steps of following order:

(1) The first level of rough adjustment: the clock CLK _H is pinched to get the tooth-missing clock CLK _G , and the E1 data packet from the Ethernet is stored in the FIFO memory buffer, and read with the tooth-missing clock CLK _G , and the FIFO memory Output the E1 data of the missing tooth of the clock;

(2) Second-level fine-tuning: store the E1 data of the missing tooth in the elastic memory, and use the tooth-missing clock CLK _G as the input of the phase-locked loop. The phase-locked loop outputs the synchronization signal to the elastic memory, and the output of the phase-locked loop serves Its feedback input, the phase-locked loop controls its output clock frequency by monitoring the difference between the read and write pointers of the elastic memory. If the difference between the read and write pointers is greater than the set value, the clock frequency output by the phase-locked loop is reduced, otherwise, the phase-locked loop is increased. The clock frequency of the ring output, and finally, the elastic memory output clock-smoothed E1 data.

The frequency of the clock CLK _H is 2.048MHz+100ppm.

The clock CLK _H is pinched so that the adjusted tooth-missing clock CLK _G can track the input E1 clock. The specific method is:

(1) If the receiving end does not receive a data packet for more than 3ms, a pulse of the clock CLK _H is forcibly cut off;

(2) The time interval of trapping is greater than or equal to 2.5ms. The timing of trapping is at the moment when a packet is received, and it is judged whether the data in the FIFO memory is "empty". If it is "empty", a pulse of CLK _H is pinched. The fact that the data in the FIFO memory is "empty" means that the storage space of the FIFO memory reaches the set lower limit threshold.

The calculation formula of the lower limit of the storage space of the FIFO memory is as follows:

If the transmission speed of the Ethernet line is V _E , and the unit is Mbps, when the longest data packet is 1518 bytes to transmit E1 data, the FIFO memory should not overflow, and the lower limit storage capacity C _F of the FIFO memory is calculated accordingly:

C _F =1518*2.048/ V _E bytes.

Another object of the present invention is to provide a clock recovery device for transmitting E1 signals based on Ethernet, including a FIFO memory, whose input terminal at one end receives the E1 data packet from Ethernet, and the input terminal at the other end receives the tooth-missing clock CLK _G , which The output end is connected to the input end of the elastic memory, and the elastic memory outputs the read-write pointer difference signal to the phase-locked loop, and the input end of the phase-locked loop receives the tooth-missing clock CLK _G , and the output of the phase-locked loop is used as its feedback input, and the phase-locked loop The output terminal is connected to the input terminal of the elastic memory, and the output terminal of the elastic memory serves as the device output.

The missing-tooth clock CLK _G is obtained from the clock CLK _H through a pinch processing circuit.

As can be seen from the above technical solution, the present invention restores the clock with two-stage buffer adjustment, the first stage is coarse adjustment, that is, the original data packet is buffered by the FIFO memory, read by the read signal clock CLK _H of 2.048MHz+100ppm, and detected by the FIFO The data "empty" of the memory indicates that the CLK _H pulse is pinched to generate a tooth-missing clock CLK _G ; the second stage is fine adjustment, that is, the E1 data of the tooth-missing clock CLK _G is stored in the elastic memory, and the continuous clock generated by the phase-locked loop Read out, control the phase-locked loop by monitoring the difference between the read and write pointers, reduce the frequency when it is greater than the set value, and accelerate the frequency when it is less than the set value, so as to reduce the phase drift, smooth missing teeth, and restore the ITU-T G The clock required by .823 can achieve better roaming performance index without changing the frame structure.

Description of drawings

Fig. 1 is method flowchart of the present invention;

Figure 2 is a schematic diagram of the effect of transmitting E1 signals and Ethernet data through 2.304Mbps SDSL.

detailed description

A clock recovery method for transmitting E1 signals based on Ethernet, which includes the following sequential steps: (1) First-level rough adjustment: the clock CLK _H undergoes pinching processing to obtain the missing tooth clock CLK _G , and the clock from the Ethernet E1 data packets are stored in FIFO memory 1 for buffering, and are read by clock CLK _G , and FIFO memory 1 outputs the E1 data of clock missing teeth; (2) Second-level fine-tuning: store the E1 data of clock missing teeth in elastic Memory 2, tooth-missing clock CLK _G is used as the input of phase-locked loop 3, and phase-locked loop 3 outputs a synchronous signal to elastic memory 2, and the output of phase-locked loop 3 is used as its feedback input, and phase-locked loop 3 reads 1. The mode of writing pointer difference controls its output clock frequency, if read, write pointer difference is greater than setting value, reduce the clock frequency of phase-locked loop 3 output, conversely, increase the clock frequency of phase-locked loop 3 output, finally, elastic memory 2 Output clock-smoothed E1 data. As shown in Figure 1. The setting value is one of the parameters of the phase-locked loop 3, and the parameter register of the phase-locked loop 3 is set by an external processor.

The frequency of the clock CLK _H is 2.048MHz+100ppm, as shown in Figure 1, the selection method of the frequency of the clock CLK _H : 1) Not less than the upper limit of the E1 signal rate, that is, 2.048MHz+50ppm; 2) Considering the possibility of the clock CLK _H itself There is a 50ppm deviation, so 2.048MHz+100ppm.

The continuous E1 data with a maximum rate of 2.048MHz+50ppm is packaged into random Ethernet data packets at the sending end and transmitted to the receiving end. These data packets are first stored in a sufficiently large FIFO memory 1, and read out with a 2.048MHz+100ppm clock CLK _H. In order to ensure that the first-level adjusted clock can track the input E1 signal clock, the pulse of the clock CLK _H is required Perform pinching treatment. The clock CLK _H is pinched so that the adjusted tooth-missing clock CLK _G can track the input E1 clock. The specific method is: (1) If the receiving end does not receive a data packet for more than 3ms, a pulse of the clock CLK _H is forcibly pinched ; (2) The time interval of trapping is greater than or equal to 2.5ms. The timing of trapping is at the moment of receiving a packet, and judge whether the data in FIFO memory 1 is "empty". If it is "empty", then pinch off CLK _H one Pulse, the data in the FIFO memory 1 is "empty" means that the storage space of the FIFO memory 1 reaches the set lower limit threshold.

The calculation formula of the lower limit of the storage space of the FIFO memory 1 is as follows: if the transmission speed of the Ethernet line is _VE , and the unit is Mbps, when the longest data packet 1518 bytes transmits E1 data, the FIFO memory 1 should not overflow, accordingly Calculate the lower limit storage capacity C _F of FIFO memory 1:

C _F =1518*2.048/ V _E bytes.

As shown in Figure 1, the device includes a FIFO memory 1, the input end of one end receives the E1 data packet from Ethernet, the input end of the other end receives the missing tooth clock CLK _G , the output end is connected with the input end of the elastic memory 2, and the elastic The memory 2 outputs the read-write pointer difference signal to the phase-locked loop 3, the input end of the phase-locked loop 3 receives the missing tooth clock CLK _G , the output of the phase-locked loop 3 is used as its feedback input, and the output end of the phase-locked loop 3 is connected with the elastic memory 2 The input end of the elastic memory 2 is connected, and the output end of the elastic memory 2 is used as the device output. The missing-tooth clock CLK _G is obtained from the clock CLK _H through a pinch processing circuit.

Due to the characteristics of Ethernet, the time when E1 data packets arrive at the destination will vary randomly, and may even drop packets. In addition, the data of the data packet belongs to the large block burst data. When a data packet arrives, it is hundreds or even thousands of bytes, and the change of the write pointer of the elastic memory 2 belongs to the jump type. In such a case, it is impossible to complete the detection of the pointer difference by means of a general low-pass filter. Even if the case of packet loss is ignored, the Ethernet transmission has QoS guaranteed bandwidth, and the variation factor of the time behavior of the data packet passing through the Ethernet to the receiving end still exists.

The upper part of Figure 2, that is, from the part above the FIFO "full" baseline, it can be seen that an E1 packet, that is, an Ethernet data packet that transmits an E1 signal, is 256 bytes. Generally, the arrival interval of an E1 packet should be 1.0 Within ms +/- several μs, the sender inserts multiplexed Ethernet data packets (1518 bytes) after sending several E1 packets, and must wait for this packet to be transmitted (about 6ms) before sending the E1 packet. When the cached E1 data gets a transmission opportunity, it will digest the accumulated cache at full speed of 2.304Mbps (the packet interval is about 0.89ms), and then return to the normal transmission interval of about 1.0ms.

The FIFO memory buffer for receiving E1 packets must have sufficient capacity, and the specific calculation is as follows:

C _F =1518*2.048/ V _E =1518*2.048/2.304=1350 bytes

Therefore, the FIFO memory 1 has to wait for more than 1350 bytes to start reading after starting up.

The lower part of Figure 2 shows the relationship between the FIFO pointer tip envelope curve and the FIFO "full" and "empty" baselines. The difference between the dotted line envelope formed by the pointer tops and the FIFO "full" baseline is proportional to the difference between the actual signal rate and the rate of the read clock CLK _H , and the resulting missing tooth clock has a large drift. Therefore, it is necessary to go through the secondary buffering and clock smoothing composed of the elastic memory 2 and the phase-locked loop 3 to reduce the phase drift and smooth the missing teeth, so as to finally obtain the recovered clock that meets the specifications.

In summary, the present invention restores the clock with two-stage buffer adjustment, the first stage is coarse adjustment, that is, the original data packet is buffered by FIFO memory 1, read by the read signal clock CLK _H of 2.048MHz+100ppm, and detected by FIFO The data "empty" of the memory 1 indicates that the CLK _H pulse is pinched to generate the tooth-missing clock CLK _G ; the second stage is fine adjustment, that is, the E1 data of the tooth-missing clock CLK _G is stored in the elastic memory 2, which is generated by the phase-locked loop 3 Continuous clock readout, control the phase-locked loop 3 by monitoring the difference between the read and write pointers, reduce the frequency when it is greater than the set value, and accelerate the frequency when it is less than the set value, so as to reduce the phase drift, smooth missing teeth, and restore the compliance The clock required by ITU-T G.823 can achieve better roaming performance without changing the frame structure.

Claims (6)

1. A clock recovery method based on Ethernet transmission E1 signal, the method comprises the steps of the following sequence: (1) The first level of rough adjustment: the clock CLK _H is pinched to get the tooth-missing clock CLK _G , and the E1 data packet from the Ethernet is stored in the FIFO memory buffer, and read with the tooth-missing clock CLK _G , and the FIFO memory Output the E1 data of the missing tooth of the clock; (2) Second-level fine-tuning: store the E1 data of the missing tooth in the elastic memory, and use the tooth-missing clock CLK _G as the input of the phase-locked loop. The phase-locked loop outputs the synchronization signal to the elastic memory, and the output of the phase-locked loop serves Its feedback input, the phase-locked loop controls its output clock frequency by monitoring the difference between the read and write pointers of the elastic memory. If the difference between the read and write pointers is greater than the set value, the clock frequency output by the phase-locked loop is reduced, otherwise, the phase-locked loop is increased. The clock frequency of the ring output, and finally, the elastic memory output clock-smoothed E1 data. 2. The clock recovery method for transmitting E1 signals based on Ethernet according to claim 1, characterized in that: the frequency of the clock CLK _H is 2.048MHz+100ppm. 3. The clock recovery method for transmitting E1 signals based on Ethernet according to claim 1, characterized in that: the clock CLK _H is pinched and processed so that the adjusted missing tooth clock CLK _G can track the input E1 clock, the specific method for: (1) If the receiving end does not receive a data packet for more than 3ms, a pulse of the clock CLK _H is forcibly cut off; (2) The time interval of trapping is greater than or equal to 2.5ms. The timing of trapping is at the moment when a packet is received, and it is judged whether the data in the FIFO memory is "empty". If it is "empty", a pulse of CLK _H is pinched. The fact that the data in the FIFO memory is "empty" means that the storage space of the FIFO memory reaches the set lower limit threshold. 4. the clock recovery method based on Ethernet transmission E1 signal according to claim 3, is characterized in that: the computing formula of described FIFO memory storage space lower limit is as follows: If the transmission speed of the Ethernet line is V _E , and the unit is Mbps, when the longest data packet is 1518 bytes to transmit E1 data, the FIFO memory should not overflow, and the lower limit storage capacity C _F of the FIFO memory is calculated accordingly: C _F =1518*2.048/ V _E bytes. 5. The device for implementing the clock recovery method according to any one of claims 1 to 4, characterized in that: it comprises a FIFO memory, and its input terminal at one end receives the E1 data packet from Ethernet, and the input terminal at the other end receives the tooth-missing clock CLK _G , its output end is connected with the input end of the elastic memory, the elastic memory outputs the reading and writing pointer difference signal to the phase-locked loop, the input end of the phase-locked loop receives the tooth-missing clock CLK _G , the output of the phase-locked loop is used as its feedback input, and the lock The output end of the phase loop is connected with the input end of the elastic memory, and the output end of the elastic memory is used as the device output. 6. The device according to claim 5, characterized in that the missing tooth clock CLK _G is obtained from the clock CLK _H through a pinch processing circuit.