CN103795947B - Method for configuring memory space in video signal processing apparatus - Google Patents

Abstract

The present invention provides a memory space allocation method, which is applied to a video signal processing device. The method includes: planning a first memory space and a second memory space in a memory, and the first and second memory spaces are at least partially overlapping; judging the type of a signal source; when the signal source is a first video signal source, enabling a first processing circuit, and temporarily storing relevant data of the first video signal source through the first memory space; and When the signal source is a second video signal source, enable a second processing circuit, and temporarily store relevant data of the second video signal source through the second memory space, wherein when the first processing circuit is enabled, turn off the the second processing circuit, and when the second processing circuit is enabled, the first processing circuit is turned off.

Description

Memory space allocation method used in video signal processing device

【Technical field】

The present invention relates to a video signal processing mechanism, in particular to a memory space allocation method used in a video signal processing device.

【Background technique】

For a general traditional TV signal processing device, regardless of the source of the image type received, the corresponding memory space used by multiple hardware processing circuits must be pre-configured in the internal memory element. For example, image sources may include different types of signal sources such as analog TV signal sources, digital TV signal sources, and multimedia signal sources. Prior art personnel have designed corresponding analog TV processing circuits, digital TV signal sources, etc. in traditional TV signal processing devices. The TV processing circuit and the multimedia processing circuit are used to process different signal sources respectively. However, under the traditional structure, all signal processing circuits (including analog TV processing circuits, digital TV processing circuits and multimedia processing circuits) will start to operate after the TV signal processing device is turned on, and the hardware circuits such as the signal processing circuits The components will correspondingly access the pre-configured memory space, even if the signal source is switched from one signal source to another (this may be caused by the user deciding to watch other types of video frames), all signal processing circuits will continue to operate . In other words, even if a certain signal source will not be processed at present (for example, an analog TV signal source is currently processed, and a digital TV signal source is not processed first), under the traditional architecture, the digital TV processing corresponding to the digital TV signal source The circuit will still be activated, and correspondingly allocated a memory space. For the analog TV processing circuit processing the analog TV signal source, the memory space allocated to the digital TV processing circuit has not been released at this time. Therefore, the analog The TV processing circuit also cannot access this memory space. Therefore, the actual memory space allocation method of the traditional TV signal processing device is inefficient, and must use larger-sized memory components to implement, which increases the manufacturing cost. In addition, all hardware circuit components for processing different signal sources must be turned on, which also causes The problem of power consumption cannot meet the requirements of energy saving.

【Content of invention】

Therefore, one of the objectives of the present invention is to provide a video signal processing device, especially a memory space allocation method used in the video signal processing device, so as to solve the above-mentioned problems in the prior art.

According to an embodiment of the present invention, it discloses a memory space configuration method applied to a video signal processing device, the method includes: planning a first memory space and a second memory space in a memory, the first memory space 1. The second memory space overlaps at least partially; judging the type of a signal source; when the signal source is a first video signal source, enabling a first processing circuit, and temporarily storing the first video through the first memory space Relevant data of the signal source; and when the signal source is a second video signal source, enable a second processing circuit, and temporarily store the relevant data of the second video signal source through the second memory space; wherein the first The second processing circuit is turned off when the processing circuit is enabled, and the first processing circuit is turned off when the second processing circuit is enabled.

According to an embodiment of the present invention, it further discloses a video signal processing device, including: a memory, planning a first memory space and a second memory space, the first and second memory spaces overlap at least partially; A detection unit for judging the type of a video signal source; a first processing circuit for processing a first video signal source; a second processing circuit for processing a second video signal source; and a processor, It is used to control the first processing circuit and the second processing circuit according to the type of the video signal source, and when the video signal source is the first video signal source, enable the first processing circuit to use the first memory spatially process the first video signal; when the video signal source is the second video signal source, enable the second processing circuit to use the second memory space to process the second video signal source.

The memory space configuration and operation adopted by the embodiments of the present invention for different types of signal sources can enable different signal sources executed at different time points to use the same memory space respectively, thus saving the usage of the overall memory space, More memory space can be effectively used, and it is also beneficial to reduce the manufacturing cost. Furthermore, the embodiments of the present invention aim at only turning on corresponding hardware circuit elements when receiving different signal sources, instead of turning on all hardware circuit elements, so that the effect of power saving can also be achieved at the same time.

【Description of drawings】

FIG. 1 is a schematic diagram of a video signal processing device according to a first embodiment of the present invention.

FIG. 2A and FIG. 2B are schematic diagrams of memory space configurations of memory circuits set by the memory space configuration table shown in FIG. 1 for the first signal source S1 and the second signal source S2 respectively.

3A and FIG. 3B are schematic diagrams of another memory space configuration of the memory circuit set by the memory space configuration table shown in FIG. 1 for the first signal source S1 and the second signal source S2 respectively.

FIG. 4 is a schematic diagram of the operation flow of the video signal processing device shown in FIG. 1 .

FIG. 5 is a schematic diagram of a video signal processing device according to a second embodiment of the present invention.

FIG. 6 is a schematic diagram of the memory space configuration of the memory circuit set by the memory space configuration table shown in FIG. 5 for the multimedia signal source.

[Description of main component symbols]

100, 500 video signal processing device

105 detection unit

110 memory space configuration table

115 processors

120 memory circuits

125A, 125B, 525A, 525B, 525C hardware processing circuit

130 Signal source selection unit

205, 210, 215, 305, 310, 315A, memory space 315B

【detailed description】

Please refer to FIG. 1 , which is a schematic diagram of a video signal processing device 100 according to an embodiment of the present invention. The video signal processing device 100 includes a detection unit 105, a memory space configuration table 110, a processor 115, a memory circuit 120, a plurality of hardware processing circuit elements 125A, 125B and a signal source selection unit 130, wherein the first hardware processing The circuit 125A is used for processing the first signal source S1, and the second hardware processing circuit 125B is used for processing the second signal source S2, and the types of the first and second signal sources S1 and S2 are different. The memory space allocation table 110 is used to record the allocation result of the memory space in the memory circuit 120 . The video signal processing device 100 can receive and process a variety of different signal sources according to user commands, that is, the first and second signal sources S1 and S2, wherein the first signal source S1 is an analog TV signal source, a digital TV signal source and multimedia signal source, and the second signal source S2 is the other one of analog TV signal source, digital TV signal source and multimedia signal source; the video signal processing device 100 can process the picture data of the signal source Output and play on the display screen. For the reception and processing of a signal source, the detection unit 105 is used to detect the command input by the user, and transmit the obtained detection result to the processor 115, and the processor 115 will start and execute the corresponding program code to perform operations that process the corresponding signal sources. For example, if the detection result generated by the detection unit 105 indicates that the user intends to watch the picture of the first signal source S1 (such as an analog TV signal source), the processor 115 will start and execute the processing of the analog TV according to the detection result. The relevant program code of the signal source, and when executing the corresponding program code, the processor 115 will also configure the memory space of the memory circuit 120 according to the configuration mode indicated by the memory space configuration table 110, so that the first hardware processing circuit When processing the first signal source S1 (such as an analog TV signal source), 125A may temporarily store relevant data in the configured memory space through the memory space configured in the memory circuit 120 (including at least the first memory space) or store relevant data from The memory space of the memory circuit 120 reads out the related data. When the first signal source S1 is an analog TV signal source, the first hardware processing circuit 125A includes a comb filter (Comb Filter) in practice, such as a 3D comb filter. The comb filter is used for analog TV signal The source separates the black-and-white and color signals (Y/C separation), so that the separated black-and-white and color signals are sent to the corresponding demodulators without interfering with each other; however, it should be noted that the present invention does not It is not limited that the first hardware processing circuit 125A must be a comb filter, but the circuit design of the first hardware processing circuit 125A during implementation is determined according to the type of the first signal source S1, so the above description is not a limitation of the present invention .

Similarly, if the detection result generated by the detection unit 105 indicates that the user intends to watch the picture of the second signal source S2 (for example, one of the digital TV signal source or the multimedia signal source), the processor 115 will As a result, the related program code for processing the second signal source S2 is started and executed, and when the corresponding program code is executed, the processor 115 also configures the memory of the memory circuit 120 according to the configuration mode indicated by the memory space configuration table 110 space, so that when the second hardware processing circuit 125B processes the second signal source S2 (for example, one of the digital TV signal source or the multimedia signal source), the memory space configured in the memory circuit 120 (including at least the second (2) memory space), temporarily storing relevant data in the configured memory space or reading relevant data from the memory space of the memory circuit 120 . When the second signal source S2 is a digital TV signal source, the second hardware processing circuit 125B actually includes an electronic program guide (Electronic Program Guide, EPG) hardware processing circuit for capturing and processing the digital TV signal source In addition, if the second signal source S2 is a multimedia signal source, the second hardware processing circuit 125B is actually a hardware processing circuit for multimedia signals, used to capture and process multimedia Relevant data and pictures in the signal source; It should be noted that the present invention does not limit the second hardware processing circuit 125B to necessarily be a hardware processing circuit for processing digital TV signal sources or multimedia signal sources, but according to the second signal source S2 The circuit design of the second hardware processing circuit 125B during implementation is determined by the type, so the above description is not a limitation of the present invention.

As mentioned above, the embodiments of the present invention are aimed at different types of signal sources S1 and S2. When processing the corresponding signal sources, the hardware processing circuit 125A or 125B respectively temporarily stores the relevant data in the configured memory space or reads from the memory circuit The memory space of 120 reads out relevant data. In an embodiment of the present invention, in order to save the memory space of the memory circuit 120, the content of the memory space configuration table 110 indicates that the first memory space accessed by the first hardware processing circuit 125A and the second hardware processing circuit at least partially overlap The second memory space accessed by 125B; and in a preferred embodiment, the first and second memory spaces are overlapped, that is, the hardware processing circuits 125A and 125B actually access the same memory space. Please refer to FIG. 2A and FIG. 2B together. FIG. 2A is a schematic diagram of the memory space configuration of the memory circuit 120 set by the memory space configuration table 110 shown in FIG. 1 for the first signal source S1. FIG. 2B is a schematic diagram of the memory space configuration shown in FIG. A schematic diagram of the memory space configuration of the memory circuit 120 set by the space configuration table 110 for the second signal source S2. As shown in the figure, the address settings of the memory spaces 205 and 210 are used to store the processor program code CODE and the data of On Screen Display used in processing the first signal source S1 and the second signal source S2. OSD, and when the video signal processing device 100 is used to process the first signal source S1 (as shown in FIG. 2A ), the address of the memory space 215 is used to store and process the relevant data of the first signal source S1, in other words, the memory space 215 It is the first memory space mentioned above, and when the first signal source S1 is, for example, an analog TV signal source, the address of the memory space 215 can be used to store the comb filter for separating black and white and color signals from the analog TV signal source Signal data COMB. Conversely, when the video signal processing device 100 is used to process the second signal source S2 (as shown in FIG. 2B ), the address of the memory space 215 is used to store and process the relevant data of the second signal source S2, in other words, the memory space 215 is also The second memory space mentioned above, and when the second signal source S2 is, for example, a digital TV signal source, the address of the memory space 215 can be used to store the data and picture EPG of the electronic program list of the digital TV signal source. In addition, if the second When the signal source S2 is a multimedia signal source, the address of the memory space 215 can be used to store multimedia data and images of the multimedia signal source. Therefore, the start addresses of the first and second memory spaces respectively accessible by the first and second body processing circuits 125A and 125B are set to the same start address, and the respective end addresses are set to the same End address, by using the address of the same memory space 215 to store and process different data (such as data COMB and EPG) of different signal sources S1 and S2 at different time points, so that the circuit design of the memory circuit 120 does not need to be overdone during implementation. More memory space, in other words, the size of the memory circuit 120 can be relatively smaller, so the manufacturing cost is relatively low/cheap.

It should be noted that the above-mentioned embodiment of address overlap between the first and second memory spaces is not a limitation of the present invention. In another embodiment, it can be designed that part of the address of the first memory space overlaps with that of the second memory space. The partial addresses, that is, the addresses of the first and second memory spaces only partially overlap. Please refer to FIG. 3A and FIG. 3B together. FIG. 3A is the memory space configuration method of the memory circuit 120 set by the memory space configuration table 110 shown in FIG. 1 for the first signal source S1. FIG. 3B is the memory space configuration method shown in FIG. 1 The space configuration table 110 sets another memory space configuration mode of the memory circuit 120 for the second signal source S2. As shown in the figure, the addresses of the memory spaces 305 and 310 are set to store the processor program code CODE and the display control data OSD used when processing the first signal source S1 and the second signal source S2. When the signal processing device 100 processes the first signal source S1 (as shown in FIG. 3A ), it uses the address of the memory space 315A to store and process the relevant data of the first signal source S1, such as the data COMB of the comb filter. On the contrary, When the video signal processing device 100 processes the second signal source S2 (as shown in FIG. 3B ), it uses the address of the memory space 315B to store and process the relevant data of the second signal source S2, such as electronic program guide data EPG, wherein the memory The address of space 315A only partially overlaps with the address of memory space 315B (as indicated by the hatched area in FIG. 3B ). In addition, it should be noted that the above-mentioned memory spaces 315A and 315B are only one embodiment of the present invention in which partial address overlap is not a limitation of the present invention, and the embodiment of partial address overlap can have many different design variations , in the design variation, the start address of a certain memory space is set to be located between a start address and an end address of another memory space, for example, in FIGS. 3A and 3B , the second memory space The start address of 315B is set to be located between the start address and the end address of the first memory space 315A; the design variations all conform to the spirit of the present invention.

Moreover, in order to use the address of the same memory space or at least partially the same memory space address when processing the first and second signal sources S1 and S2 respectively, in an embodiment of the present invention, when processing a signal source, Only one corresponding hardware processing circuit is turned on, that is, when the first signal source S1 is processed, only the first hardware processing circuit 125A is turned on, and other hardware processing circuits (that is, the second hardware processing circuit 125B) are turned off, And when processing the second signal source S2, only the second hardware processing circuit 125B is turned on, and other hardware processing circuits (that is, the first hardware processing circuit 125A are turned off. When the first hardware processing circuit 125A is turned on and the second hardware processing circuit When 125B is turned off, it means that the memory space occupied by the second hardware processing circuit 125B is released, and the released memory space can be allocated to the first hardware processing circuit 125A to process the operation of the first signal source S1; otherwise, When the second hardware processing circuit 125B is turned on and the first hardware processing circuit 125A is turned off, it means that the memory space occupied by the first hardware processing circuit 125A is released, and the released memory space can be allocated to the second hardware processing circuit 125B to process the operation of the second signal source S2.Therefore, using the address of the same block of memory space or at least part of the same memory space address at different time points to process the operation of different signal sources S1, S2 will not cause errors Please refer to Fig. 4, Fig. 4 is the operation flow schematic diagram of the video signal processing device 100 shown in Fig. 1.If generally can reach the same result, do not need to carry out according to the order of steps in the flow process shown in Fig. 4 , and the steps shown in FIG. 4 do not have to be performed continuously, that is, other steps can also be inserted therein.

When the video signal processing device 100 is turned on, the detection unit 105 detects whether the user inputs a command, and if it detects that the user inputs a command, the obtained detection result is output and sent to the processor 115 at step 405 . The processor 115 will receive the detection result, start and execute the corresponding program code according to the detection result (step 410, the corresponding program code will first close all hardware processing circuits used to process different signal sources when executing, and Release the memory space of the memory circuit 120 (step 415, for example, close the first and second hardware processing circuits 125A, 125B shown in Figure 1. Then, the processor 115 executes the corresponding program code, according to the detection result of the detection unit 105 , get the address configuration of the corresponding memory space from the memory space configuration table 110 (step 420. The processor 115 sets/assigns the address configuration of the corresponding memory space to a corresponding hardware circuit element (step 425, if the detection unit The detection result of 105 indicates the first signal source S1, then the processor 115 will set/assign the address configuration of the memory space to the first hardware circuit 125A, otherwise, if the detection result of the detection unit 105 indicates the second signal source S2, Then the processor 115 will set/assign the corresponding memory space address configuration to the second hardware circuit 125B. The processor 115 then activates/enables the corresponding hardware circuit elements described in step 425 (step 430. Then, the processor 115 Control the signal source selection unit 130 to select and receive a signal source corresponding to the hardware circuit element described in step 430 (step 435), and the hardware circuit element activated in step 430 starts to receive the signal source selection unit 130 Incoming signals are processed.

For example, if the detection result detected by the detection unit 105 indicates the first signal source S1, indicating that the user wants to watch the picture of the first signal source S1, the processor 115 will select and execute the corresponding program code, and in order to avoid starting two hardware processing circuit elements at the same time subsequently, so the corresponding program code first closes all hardware processing circuits 125A, 125B and releases the memory space of the memory circuit 120 in step 415, and in step In step 420 and step 425, the program code configures the physical address according to the content of the memory space configuration table, and then restarts the first hardware processing circuit 125A corresponding to the first signal source S1 in step 430. In this way, the present invention The flow of the embodiment can ensure that only one hardware processing circuit element (that is, the first hardware processing circuit 125A) is activated at the same time point and only the set memory space is assigned to the activated hardware processing circuit element 125A, so the video The operation of the signal processing device 100 to save memory space by sharing all or part of the physical addresses of the same memory space will not cause access errors. Conversely, if the detection result indicates the second signal source S2, only the second hardware processing circuit 125B corresponding to the second signal source S2 is started in step 430, ensuring that only the second hardware processing circuit 125B will is activated.

Once the user subsequently decides to watch the screen of the second signal source S2 and inputs a command, instructing to switch from the first signal source S1 to the second signal source S2, the detection unit 105 will detect the command in step 405 and report the detection result output to the processor 115, the processor 115 will select and execute the program code corresponding to the second signal source S2 in step 410, and close all hardware processing circuits 125A, 125B and release the memory space of the memory circuit 120 in step 415, In other words, the memory space configured and used by the first hardware processing circuit 125A is released, and the subsequent program code corresponding to the second signal source S2 in step 420 and step 425 will configure the physical address according to the content of the memory space configuration table , and restart the second hardware processing circuit 125B corresponding to the second signal source S2 in step 430 . In other words, when the video signal processing device 100 is turned on or the user decides to switch to a different signal source, the process steps shown in FIG. 4 will be executed sequentially to configure the physical address of the corresponding memory space to the activated hardware processing circuit.

Furthermore, the present invention does not limit the number of hardware circuit elements included in the video signal processing device, because the signal sources that the current video signal processing device can receive have a variety of signal types, the video signal of the embodiment of the present invention The processing device can also be used to receive and process multiple (including two or more) different types of signal sources, so it contains multiple different hardware circuit processing elements inside. Please refer to FIG. 5 , which is a schematic diagram of a video signal processing device 500 according to a second embodiment of the present invention. The video signal processing device 500 includes a detection unit 105, a memory space configuration table 110, a processor 115, a memory circuit 120, a plurality of hardware processing circuit elements 525A, 525B, 525C and a signal source selection unit 130, wherein the hardware processing circuit elements 525A, 525B and 525C are respectively used to process the first, second and third signal sources S1, S2 and S3, and the signal types of the first, second and third signal sources S1, S2 and S3 are all different. For example, The first signal source S1 is an analog TV signal source, the first hardware processing circuit 525A is a comb filter, the second signal source S2 is a digital TV signal source, and the second hardware processing circuit 525B is a hardware processing circuit for processing an electronic program list. The circuit element, the third signal source S3 is a multimedia signal source, and the third hardware processing circuit 525C is a hardware processing circuit element for processing multimedia data. The operations and functions of other circuit elements are the same as those described in the preceding paragraphs, and will not be repeated here.

For the memory space configuration of the memory circuit 120, please refer to FIG. 2A, FIG. 2B and FIG. 6. FIG. 2A, FIG. 2B and FIG. 6 are the memory space configuration table 110 shown in FIG. The memory space configuration mode of the memory circuit 120 set by the multimedia signal source. As shown in the figure, the addresses of the memory spaces 205 and 210 are set to store the processor program code CODE and the display control data OSD used when processing different signal sources S1, S2 and S3. When the video signal processing device For example, when 500 is used to process an analog TV signal source (as shown in FIG. 2A ), the address of the memory space 215 is used to store the signal data COMB for separating black and white and color signals of the analog TV signal source by the comb filter. Conversely, when the video signal processing device 500 is used to process digital TV signal sources (as shown in FIG. 2B ), the address of the memory space 215 is used to store the data and picture EPG of the electronic program list of the digital TV signal source. In addition, when For example, when the video signal processing device 500 is used to process a multimedia signal source (as shown in FIG. 6 ), the address of the memory space 215 is used to store the multimedia data and the frame MM of the multimedia signal source. By using the address of the same memory space 215 to store and process different data (data COMB, EPG, MM) of different signal sources S1, S2, S3 at different time points, the circuit design of the memory circuit 120 does not need to be overdone during implementation. More memory space, in other words, the size of the memory circuit 120 can be relatively smaller, so the manufacturing cost is relatively low/cheap.

The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the scope of the patent application of the present invention shall fall within the scope of the present invention.

Claims (8)

1. A memory space configuration method applied to a video signal processing device, the method comprising: Planning a first memory space and a second memory space in a memory, the first memory space and the second memory space at least partially overlap; determine the type of a signal source; When the signal source is a first video signal source, enable a first processing circuit, and temporarily store relevant data of the first video signal source through the first memory space; and When the signal source is a second video signal source, enable a second processing circuit, and temporarily store relevant data of the second video signal source through the second memory space; wherein when the first processing circuit is enabled, the second processing circuit is turned off, and when the second processing circuit is turned on, the first processing circuit is turned off; The step of planning a first memory space and a second memory space in a memory includes: recording the planning result in a memory space configuration table; The step of temporarily storing the relevant data of the first video signal source through the first memory space includes: obtaining the address of the first memory space from the memory space configuration table, and temporarily storing the relevant data of the first video signal source to the first memory space. 2. The memory space allocation method according to claim 1, wherein the first video signal source is one of a digital TV signal source, an analog TV signal source and a multimedia signal source, and the second video signal source is The video signal source is the other one of the digital TV signal source, the analog TV signal source and the multimedia signal source. 3. The memory space allocation method according to claim 1, wherein the step of temporarily storing the relevant data of the second video signal source through the second memory space comprises: obtaining the first memory space allocation table from the memory space allocation table The address of the second memory space, and temporarily store the relevant data of the second video signal source in the second memory space. 4. The memory space configuration method according to claim 1, further comprising: releasing the first memory space when the first processing circuit is turned off; and When the second processing circuit is turned off, the second memory space is released. 5. A video signal processing device, comprising: A memory, planning a first memory space and a second memory space, the first memory space and the second memory space at least partially overlap; A detection unit for judging the type of a video signal source; a first processing circuit for processing a first video signal source; a second processing circuit for processing a second video signal source; and a processor, used to control the first processing circuit and the second processing circuit according to the type of the video signal source; when the video signal source is the first video signal source, enable the first processing circuit to use The first memory space processes the first video signal; when the video signal source is the second video signal source, enabling the second processing circuit to use the second memory space to process the second video signal source; and A memory space configuration table, used to record the configuration of the first and second memory spaces; Wherein the processor obtains the address of the first memory space from the memory space configuration table, and temporarily stores the related data of the first video signal source in the first memory space; and obtains the second memory space from the memory space configuration table address of the memory space, and temporarily store relevant data of the second video signal source in the second memory space. 6. The video signal processing device according to claim 5, wherein the processor turns off the second processing circuit when the first processing circuit is enabled; and turns off the second processing circuit when the second processing circuit is enabled. A processing circuit. 7. The video signal processing device according to claim 6, wherein the first video signal source is one of a digital TV signal source, an analog TV signal source and a multimedia signal source, and the second The video signal source is the other one of the digital TV signal source, the analog TV signal source and the multimedia signal source. 8. The video signal processing device according to claim 7, wherein when the processor closes the first processing circuit, the first memory space is released; and when the processor closes the second processing circuit, The second memory space is released.