CN103825557B - Transconductance amplifier with low power consumption and high linearity - Google Patents

Abstract

The invention relates to the technical field of analog integrated operational amplifiers, in particular to a Push-Pull transconductance amplifier with low power consumption and high linearity. The transconductance amplifier of the present invention comprises a bias circuit, a Rail-to-Rail input stage and a Push-Pull output stage connected in sequence; the bias circuit is made up of a mirror current mirror tube, which is a Rail-to-Rail input stage and a Push Pull output stage; The ‑Pull output stage provides the bias voltage; the Rail‑to‑Rail input stage uses folded NMOS differential pairs and PMOS differential pairs for common-mode input range rail-to-rail and uses source degeneration for linearized transconductance; The Push-Pull output stage described above uses low-power bias to realize low-power push-pull output, and uses mirror current amplification to improve output drive capability. The invention has the advantages of simple structure, high linearity, low power consumption, high power supply rejection ratio, small chip area and the like. The invention is particularly applicable to transconductance amplifiers.

Description

A Low Power Consumption and High Linearity Transconductance Amplifier

technical field

The invention relates to the technical field of analog integrated operational amplifiers, in particular to a Push-Pull transconductance amplifier with low power consumption and high linearity.

Background technique

Operational transconductance amplifier (OTA), as one of the important foundations and key modules in the analog circuit system, is widely used in power supply, power amplification, signal processing and other systems. The performance level of the operational amplifier directly determines the performance of the entire system. Since different application occasions have different requirements on the parameters of operational transconductance amplifiers, the design of operational transconductance amplifiers is mostly based on the requirements of the application system for its performance indicators.

In the field of switching power supplies, the error amplifier, which is the core of the voltage control loop, has different index requirements under different system topologies and different feedback signal types. In some system topologies and feedback signal types, an error amplifier with low power consumption and high linearity is used to form a voltage control loop. For example, when the feedback signal type is an AC signal in practical applications, the error amplifier needs to accept a wide Range input, and the nonlinear problem introduced by the wide input range also needs to be considered by the designer; when the output of the error amplifier drives the PWM (Pulse Width Modulation) controller and requires a large adjustment range, the error amplifier requires a large output swing; when When the chip has strict requirements on power consumption, the design of the error amplifier should reduce power consumption as much as possible. It is based on this application requirement that it is of great practical significance to design a low-power and high-linearity transconductance amplifier that can be used as an error amplifier.

The OTA linearity achieved by the traditional source-coupled differential amplifier structure is limited by the tail current I _SS and β If you want to increase the linear input range, you must increase the tail current I _SS or reduce β; the paradox is that increasing I _SS will increase power consumption, and reducing β will reduce the common-mode input range, so traditional amplifiers do not have It also has high linearity, low power consumption and wide input range.

Contents of the invention

What the present invention aims to solve is to aim at the problems existing in the above-mentioned traditional amplifiers, and at the same time, in order to realize the requirements of the switching power supply voltage control loop on the error amplifier with low power consumption and high linearity, a low power consumption and high linearity amplifier that can be used as an error amplifier is proposed Linearity Push-Pull Transconductance Amplifier.

The technical solution adopted by the present invention to solve the above-mentioned technical problems is: a low-power consumption high-linearity transconductance amplifier, characterized in that it includes a bias circuit connected in sequence, a Rail-to-Rail input stage and a Push-Pull output stage ; The bias circuit is composed of a mirror current mirror tube, which provides a bias voltage for the Rail-to-Rail input stage and the Push-Pull output stage; the Rail-to-Rail input stage adopts a folded NMOS differential pair and a PMOS differential pair To achieve common mode input range rail to rail, and use source negative feedback to achieve linearized transconductance; the Push-Pull output stage uses low power bias to achieve low power push-pull output, and uses mirror current amplification to improve output Drive capability.

Specifically, the bias circuit includes a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a fourth PMOS transistor MP4, a first NMOS transistor MN1, a second NMOS transistor MN2, and a third NMOS transistor MN3 and current source;

The Rail-to-Rail input stage includes fifth PMOS transistor MP5, sixth PMOS transistor MP6, seventh PMOS transistor MP7, eighth PMOS transistor MP8, ninth PMOS transistor MP9, tenth PMOS transistor MP10, eleventh PMOS transistor Tube MP11, twelfth PMOS tube MP12, fourth NMOS tube MN4, fifth NMOS tube MN5, sixth NMOS tube MN6, seventh NMOS tube MN7, eighth NMOS tube MN8, ninth NMOS tube MN9, tenth NMOS tube MN10, an eleventh NMOS transistor MN11, a first resistor RSN and a second resistor RSP;

The Push-Pull output stage includes a thirteenth PMOS transistor MP13, a fourteenth PMOS transistor MP14, a fifteenth PMOS transistor MP15, a sixteenth PMOS transistor MP16, a seventeenth PMOS transistor MP17, an eighteenth PMOS transistor MP18, The twelfth NMOS transistor MN12, the thirteenth NMOS transistor MN13, the fourteenth NMOS transistor MN14, the fifteenth NMOS transistor MN15, the sixteenth NMOS transistor MN16, the seventeenth NMOS transistor MN17, the third resistor RBP and the fourth resistor RBN; where,

The first PMOS transistor MP1, the second PMOS transistor MP2, the third PMOS transistor MP3, the fourth PMOS transistor MP4, the fifth PMOS transistor MP5, the sixth PMOS transistor MP6, the ninth PMOS transistor MP9, the tenth PMOS transistor MP10, the tenth PMOS transistor The source lining terminals of the fifth PMOS transistor MP15, the sixteenth PMOS transistor MP16, the lining terminals of the eleventh PMOS transistor MP11, the twelfth PMOS transistor MP12, the seventeenth PMOS transistor MP17, and the eighteenth PMOS transistor MP18 are connected to the power supply voltage;

The gate-drain terminal of the first PMOS transistor MP1, the gate terminal of the second PMOS transistor MP2, the gate terminal of the third PMOS transistor MP3, the gate terminal of the fifth PMOS transistor MP5, and the gate terminal of the sixth PMOS transistor MP6 are all connected to the positive current source. To the terminal, the negative terminal of the current source is grounded;

The gate-drain terminal of the first NMOS transistor MN1, the gate terminal of the tenth NMOS transistor MN10, the gate terminal of the eleventh NMOS transistor MN11, the gate terminal of the sixteenth NMOS transistor MN16, and the gate terminal of the seventeenth NMOS transistor MN17 are all connected to The drain end of the second PMOS transistor MP2 is connected;

The gate-drain end of the second NMOS transistor MN2, the gate end of the third NMOS transistor MN3, the gate end of the fourth NMOS transistor MN4, the gate end of the fifth NMOS transistor MN5, the gate end of the eighth NMOS transistor MN8, the gate end of the ninth NMOS transistor The gate terminals of MN9 are all connected to the drain terminal of the third PMOS transistor MP3;

The gate-drain terminal of the fourth PMOS transistor MP4, the gate terminal of the eleventh PMOS transistor MP11, the gate terminal of the twelfth PMOS transistor MP12, the gate terminal of the seventeenth PMOS transistor MP17, and the gate terminal of the eighteenth PMOS transistor MP18 are all connected to the drain end of the third NMOS transistor MN3;

The gate terminal of the sixth NMOS transistor MN6 is connected to the gate terminal of the seventh PMOS transistor MP7 as an input terminal, and the gate terminal of the seventh NMOS transistor MN7 is connected to the gate terminal of the eighth PMOS transistor MP8 as another input terminal. The source liner end of the sixth NMOS transistor MN6 and the source liner end of the seventh NMOS transistor MN7 are respectively connected to the drain end of the fourth NMOS transistor MN4 and the drain end of the fifth NMOS transistor MN5 and bridged through the first resistor RSN;

The source liner end of the seventh PMOS transistor MP7 and the source liner end of the eighth PMOS transistor MP8 are respectively connected to the drain end of the fifth PMOS transistor MP5 and the drain end of the sixth PMOS transistor MP6 and bridged through the second resistor RSP;

The drain end of the ninth PMOS transistor MP9, the source end of the eleventh PMOS transistor MP11 are connected to the drain end of the seventh NMOS transistor MN7; the drain end of the tenth PMOS transistor MP10, the source end of the twelfth PMOS transistor MP12 and the The drain terminals of the six NMOS transistors MN6 are connected;

The drain end of the eighth NMOS transistor MN8, the source end of the tenth NMOS transistor MN10 are connected to the drain end of the eighth PMOS transistor MP8; the drain end of the ninth NMOS transistor MN9, the source end of the eleventh NMOS transistor MN11 and the seventh The drain end of the PMOS transistor MP7 is connected;

The gate end of the ninth PMOS transistor MP9, the gate end of the tenth PMOS transistor MP10, and the drain end of the eleventh PMOS transistor MP11 are all connected to the drain end of the tenth NMOS transistor MN10; the drain end of the twelfth PMOS transistor MP12, The source end of the fourteenth PMOS transistor MP14 and the source end of the thirteenth NMOS transistor MN13 are connected to the drain end of the eleventh NMOS transistor MN11;

The drain gate terminal of the twelfth NMOS transistor MN12 and the gate terminal of the thirteenth NMOS transistor MN13 are connected to the third resistor RBP to the power supply; the drain gate terminal of the thirteenth PMOS transistor MP13 and the gate terminal of the fourteenth PMOS transistor MP14 are connected to the fourth resistor RBN to ground potential, the source end of the twelfth NMOS transistor MN12 is connected to the source end of the thirteenth PMOS transistor MP13;

The gate end of the fifteenth PMOS transistor MP15, the gate end of the sixteenth PMOS transistor MP16, and the drain end of the seventeenth PMOS transistor MP17 are all connected to the drain end of the thirteenth NMOS transistor MN13; the drain end of the fourteenth NMOS transistor MN14 The gate terminal, the gate terminal of the fifteenth NMOS transistor MN15, and the drain terminal of the sixteenth NMOS transistor MN16 are all connected to the drain terminal of the fourteenth PMOS transistor MP14;

The drain end of the fifteenth PMOS transistor MP15 and the drain end of the sixteenth PMOS transistor MP16 are respectively connected to the source end of the seventeenth PMOS transistor MP17 and the source end of the eighteenth PMOS transistor MP18;

The drain end of the fourteenth NMOS transistor MN14 and the drain end of the fifteenth NMOS transistor MN15 are respectively connected to the source end of the sixteenth NMOS transistor MN16 and the source end of the seventeenth NMOS transistor MN17; The drain end is connected to the drain end of the eighteenth PMOS transistor MP18 as an output end;

The first NMOS transistor MN1, the second NMOS transistor MN2, the third NMOS transistor MN3, the fourth NMOS transistor MN4, the fifth NMOS transistor MN5, the eighth NMOS transistor MN8, the ninth NMOS transistor MN9, the fourteenth NMOS transistor MN14, the The source lining end of the fifteenth NMOS transistor MN15, the tenth NMOS transistor MN10, the eleventh NMOS transistor MN11, the twelfth NMOS transistor MN12, the thirteenth NMOS transistor MN13, the sixteenth NMOS transistor MN16, and the seventeenth NMOS transistor MN17 The pad ends are at ground potential.

The invention has the advantages of simple structure, high linearity, low power consumption, high power supply rejection ratio, small chip area and the like. Compared with the prior art, the push-pull transconductance amplifier with low power consumption and high linearity overcomes the problems of complex structure, large power consumption, and large layout area caused by adding additional circuits to improve linearity. Under the application conditions that the voltage control loop requires the error amplifier, a compact circuit design with high linearity and low power consumption is realized.

Description of drawings

Figure 1 is a schematic diagram of the source resistor cross-connected negative feedback structure of the linearized transconductance;

Fig. 2 is a schematic diagram of a source resistor separated negative feedback structure for linearized transconductance;

Fig. 3 is a schematic diagram of the overall circuit structure of the low power consumption and high linearity transconductance amplifier of the present invention.

detailed description

Below in conjunction with accompanying drawing, describe technical scheme of the present invention in detail:

The low power consumption and high linearity transconductance amplifier of the present invention comprises a Rail-to-Rail input stage, a Push-Pull push-pull output stage and a bias circuit, wherein the low power consumption and high linearity Push-Pull transconductance amplifier adopts a source Resistor-connected negative feedback structure (Figure 1) achieves high linear transconductance, compared with the source resistor separated negative feedback structure (Figure 2), the voltage drop at the source end will not increase, ensuring the joint effect of the double differential pair of tubes The common mode level range is wide; at the same time, low power consumption and high linearity Push-Pull transconductance amplifier uses current transmission to amplify the push-pull output stage to make the output drive capability large, and can drive the PWM controller to achieve a large duty cycle adjustment range; low High power consumption and linearity Push-Pull transconductance amplifier output stage adopts low power consumption bias to reduce circuit power consumption. Simulation shows that the typical power consumption is only 708uw at 25°C; low power consumption and high linearity Push-Pull transconductance amplifier The circuit structure is simple, the layout is compact, and the BCD350 process layout area is only 300×270um ² ; in addition, the cascode (cascode) structure used in the input and output stages can obtain high PSRR, and the simulation shows that the PSRR is within the frequency range of 100kHz. More than 45db, meet the system requirements.

As shown in Figure 3, it is the overall circuit structure of the low power consumption high linearity transconductance amplifier of the present invention, the bias circuit includes a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a fourth PMOS transistor MP4, first NMOS transistor MN1, second NMOS transistor MN2, third NMOS transistor MN3 and a current source;

The Rail-to-Rail input stage includes fifth PMOS transistor MP5, sixth PMOS transistor MP6, seventh PMOS transistor MP7, eighth PMOS transistor MP8, ninth PMOS transistor MP9, tenth PMOS transistor MP10, eleventh PMOS transistor Tube MP11, twelfth PMOS tube MP12, fourth NMOS tube MN4, fifth NMOS tube MN5, sixth NMOS tube MN6, seventh NMOS tube MN7, eighth NMOS tube MN8, ninth NMOS tube MN9, tenth NMOS tube MN10, an eleventh NMOS transistor MN11, a first resistor RSN and a second resistor RSP;

The Push-Pull output stage includes a thirteenth PMOS transistor MP13, a fourteenth PMOS transistor MP14, a fifteenth PMOS transistor MP15, a sixteenth PMOS transistor MP16, a seventeenth PMOS transistor MP17, an eighteenth PMOS transistor MP18, The twelfth NMOS transistor MN12, the thirteenth NMOS transistor MN13, the fourteenth NMOS transistor MN14, the fifteenth NMOS transistor MN15, the sixteenth NMOS transistor MN16, the seventeenth NMOS transistor MN17, the third resistor RBP and the fourth resistor RBN; where,

The first PMOS transistor MP1, the second PMOS transistor MP2, the third PMOS transistor MP3, the fourth PMOS transistor MP4, the fifth PMOS transistor MP5, the sixth PMOS transistor MP6, the ninth PMOS transistor MP9, the tenth PMOS transistor MP10, the tenth PMOS transistor The source lining terminals of the fifth PMOS transistor MP15, the sixteenth PMOS transistor MP16, the lining terminals of the eleventh PMOS transistor MP11, the twelfth PMOS transistor MP12, the seventeenth PMOS transistor MP17, and the eighteenth PMOS transistor MP18 are connected to the power supply voltage;

The gate-drain terminal of the first PMOS transistor MP1, the gate terminal of the second PMOS transistor MP2, the gate terminal of the third PMOS transistor MP3, the gate terminal of the fifth PMOS transistor MP5, and the gate terminal of the sixth PMOS transistor MP6 are all connected to the positive current source. To the terminal, the negative terminal of the current source is grounded;

The gate-drain terminal of the first NMOS transistor MN1, the gate terminal of the tenth NMOS transistor MN10, the gate terminal of the eleventh NMOS transistor MN11, the gate terminal of the sixteenth NMOS transistor MN16, and the gate terminal of the seventeenth NMOS transistor MN17 are all connected to The drain end of the second PMOS transistor MP2 is connected;

The gate-drain end of the second NMOS transistor MN2, the gate end of the third NMOS transistor MN3, the gate end of the fourth NMOS transistor MN4, the gate end of the fifth NMOS transistor MN5, the gate end of the eighth NMOS transistor MN8, the gate end of the ninth NMOS transistor The gate terminals of MN9 are all connected to the drain terminal of the third PMOS transistor MP3;

The gate-drain terminal of the fourth PMOS transistor MP4, the gate terminal of the eleventh PMOS transistor MP11, the gate terminal of the twelfth PMOS transistor MP12, the gate terminal of the seventeenth PMOS transistor MP17, and the gate terminal of the eighteenth PMOS transistor MP18 are all connected to the drain end of the third NMOS transistor MN3;

The gate terminal of the sixth NMOS transistor MN6 is connected to the gate terminal of the seventh PMOS transistor MP7 as an input terminal, and the gate terminal of the seventh NMOS transistor MN7 is connected to the gate terminal of the eighth PMOS transistor MP8 as another input terminal. The source liner end of the sixth NMOS transistor MN6 and the source liner end of the seventh NMOS transistor MN7 are respectively connected to the drain end of the fourth NMOS transistor MN4 and the drain end of the fifth NMOS transistor MN5 and bridged through the first resistor RSN;

The source liner end of the seventh PMOS transistor MP7 and the source liner end of the eighth PMOS transistor MP8 are respectively connected to the drain end of the fifth PMOS transistor MP5 and the drain end of the sixth PMOS transistor MP6 and bridged through the second resistor RSP;

The drain end of the ninth PMOS transistor MP9, the source end of the eleventh PMOS transistor MP11 are connected to the drain end of the seventh NMOS transistor MN7; the drain end of the tenth PMOS transistor MP10, the source end of the twelfth PMOS transistor MP12 and the The drain terminals of the six NMOS transistors MN6 are connected;

The drain end of the eighth NMOS transistor MN8, the source end of the tenth NMOS transistor MN10 are connected to the drain end of the eighth PMOS transistor MP8; the drain end of the ninth NMOS transistor MN9, the source end of the eleventh NMOS transistor MN11 and the seventh The drain end of the PMOS transistor MP7 is connected;

The gate end of the ninth PMOS transistor MP9, the gate end of the tenth PMOS transistor MP10, and the drain end of the eleventh PMOS transistor MP11 are all connected to the drain end of the tenth NMOS transistor MN10; the drain end of the twelfth PMOS transistor MP12, The source end of the fourteenth PMOS transistor MP14 and the source end of the thirteenth NMOS transistor MN13 are connected to the drain end of the eleventh NMOS transistor MN11;

The drain gate terminal of the twelfth NMOS transistor MN12 and the gate terminal of the thirteenth NMOS transistor MN13 are connected to the third resistor RBP to the power supply; the drain gate terminal of the thirteenth PMOS transistor MP13 and the gate terminal of the fourteenth PMOS transistor MP14 are connected to the fourth resistor RBN to ground potential, the source end of the twelfth NMOS transistor MN12 is connected to the source end of the thirteenth PMOS transistor MP13;

The gate end of the fifteenth PMOS transistor MP15, the gate end of the sixteenth PMOS transistor MP16, and the drain end of the seventeenth PMOS transistor MP17 are all connected to the drain end of the thirteenth NMOS transistor MN13; the drain end of the fourteenth NMOS transistor MN14 The gate terminal, the gate terminal of the fifteenth NMOS transistor MN15, and the drain terminal of the sixteenth NMOS transistor MN16 are all connected to the drain terminal of the fourteenth PMOS transistor MP14;

The drain end of the fifteenth PMOS transistor MP15 and the drain end of the sixteenth PMOS transistor MP16 are respectively connected to the source end of the seventeenth PMOS transistor MP17 and the source end of the eighteenth PMOS transistor MP18;

The drain end of the fourteenth NMOS transistor MN14 and the drain end of the fifteenth NMOS transistor MN15 are respectively connected to the source end of the sixteenth NMOS transistor MN16 and the source end of the seventeenth NMOS transistor MN17; The drain end is connected to the drain end of the eighteenth PMOS transistor MP18 as an output end;

The first NMOS transistor MN1, the second NMOS transistor MN2, the third NMOS transistor MN3, the fourth NMOS transistor MN4, the fifth NMOS transistor MN5, the eighth NMOS transistor MN8, the ninth NMOS transistor MN9, the fourteenth NMOS transistor MN14, the The source lining end of the fifteenth NMOS transistor MN15, the tenth NMOS transistor MN10, the eleventh NMOS transistor MN11, the twelfth NMOS transistor MN12, the thirteenth NMOS transistor MN13, the sixteenth NMOS transistor MN16, and the seventeenth NMOS transistor MN17 The pad ends are at ground potential

Wherein, the current source IB, NMOS transistors MN1 , MN2 , MN3 and PMOS transistors MP1 , MP2 , MP3 , MP4 form a bias circuit. The power supply VDD can generate bias voltages VB1, VB2, VB3, and VB4 to provide bias voltages for the Rail-to-Rail input stage and the Push-Pull output stage.

The NMOS transistors MN4-MN11, PMOS transistors MP5-MP12, resistors RSN and RSP form a Rail-to-Rail input stage. ICMR rail-to-rail can be achieved by using a double-folded differential pair input, linearized transconductance can be achieved by using a source-end resistor cross-connect negative feedback, and a cascode cascode structure can not only improve current transmission accuracy but also improve PSRR.

The NMOS transistors MN12-MN17, PMOS transistors MP13-MP18, resistors RBN and RBP form a Push-Pull output stage. Among them, MN12, MP13, RBP, and RBN can provide low-power bias for MN13 and MP14. By adjusting the size of RBP and RBN, a compromise between layout area and power consumption can be achieved. NMOS transistors MN14~MN17 and PMOS transistors MP15~MP18 have a current mirror structure It can achieve current amplification and improve the ability to drive the load.

Working principle of the present invention:

For the bias circuit, set all the tubes to work in the saturation region. In order to ensure that the NMOS differential pairs MN6, MN7 and the PMOS differential pairs MP7, MP8 have the same tail current source and thus have the same transconductance, it is necessary to set (W/L) _N2 ＝(W/L) _N4 ＝(W/L) _N5 ; in order to ensure that the cascode transistor is properly biased so as to maximize the swing range, (W/L) _N1 must be set approximately ( W/L) _N2 In order to ensure the accuracy of the mirror current, the channel length of the mirror tube must be set larger to reduce the influence of the channel length modulation effect.

For Rail-to-Rail input stage circuits, set all tubes to work in the saturation region. NMOS differential pair can realize common mode input range (V _GSN6,7 +V _DSATN4,5 )～VDD, PMOS differential pair can realize common mode input range VSS～(VDD-V _DSATP5,6 -V _GS7,8 ), double differential The pair structure can easily realize the common-mode input range rail-to-rail. In order to make the double differential pair have a larger mutual action range, a resistance jumper structure (shown in Figure 1) is used to achieve linearized transconductance. At this time, the common action range is (V _GSN6,7 +V _DSATN4,5 )～(VDD-V _DSATP5,6 -V _GS7,8 ), and the common action range of the resistance separation structure (shown in Figure 2) is (V _GSN6,7 + V _DSATN4,5 +V _RSN )～(VDD-V _DSATP5,6 -V _GS7,8 -V _RSP ), it is obvious that the structure shown in Figure 1 can obtain a larger joint action interval; set RSN=RSP=RS, then Have:

${\mathrm{<span\; class="notranslate">\; G</span>}}_{\mathrm{<span\; class="notranslate">\; n</span>}\mathrm{<span\; class="notranslate">\; 6,7</span>}}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; G</span>}}_{\mathrm{<span\; class="notranslate">\; mP</span>}\mathrm{<span\; class="notranslate">\; 7,8</span>}}<span\; class="notranslate">\; \&ap;</span>\frac{\mathrm{<span\; class="notranslate">\; 2</span>}}{\mathrm{<span\; class="notranslate">\; RS</span>}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 3</span>}<span\; class="notranslate">\; )</span>$

Among them, G _mN6,7 and G _mP7,8 represent the equivalent transconductance of the NMOS differential pair MN6, MN7 plus source negative feedback and the equivalent transconductance of the PMOS differential pair MP7, MP8 plus source negative feedback, respectively, g _mNi , _rdsNi represent the transconductance and drain-source resistance of the i-th NMOS transistor respectively, and g _mPi and _rdsPi represent the transconductance and drain-source resistance of the i-th PMOS transistor respectively.

It can be seen from the expression (3) that the transconductance of the input differential pair is only determined by the source-side jumper resistance, which realizes linearization. The use of isolated resistors and matching technology on the layout can make the transconductance of the NMOS differential pair and the PMOS differential pair more accurate. Exact, better linearization.

For the Push-Pull output stage circuit, it mainly realizes current transmission amplification, and adopts current buffer and current mirror amplification structure. MN12 diode connection, MP13 diode connection, RBN, RBP provide low power consumption bias for current buffer MOS transistors MN13, MP14, increasing the resistance of RBN, RBP can reduce power consumption; the output of the input stage is from the source of MN13, MP14 After the terminal input and the drain terminal output, the current mirror amplification structure MN14~MN17 and MP15~MP18 is used to amplify the current proportionally; when the signal is large, the output of the input stage changes greatly, which will cause a tube of MN13 and MP14 to enter the cut-off area, thereby realizing push-pull output;

It can be seen that a low power consumption and high linearity Push-Pull transconductance amplifier proposed by the present invention has a simple structure, only 17 NMOS, 18 PMOS transistors and 4 resistors are used, and it is very suitable for use in the field of switching power supplies as a voltage Error amplifier at the heart of the control loop.

Claims (1)

1. a kind of low power consumption high linearity transconductance amplifier is characterized in that, comprises the bias circuit, Rail-to-Rail input stage and Push-Pull output stage that are connected successively; Described bias circuit is formed by mirror current mirror tube Composed to provide a bias voltage for the Rail-to-Rail input stage and the Push-Pull output stage; the Rail-to-Rail input stage uses a folded NMOS differential pair and a PMOS differential pair to achieve a common-mode input range rail-to-rail, and Linearized transconductance is realized by using source negative feedback; the Push-Pull output stage uses low power consumption bias to realize low power consumption push-pull output, and uses mirror current amplification to improve output drive capability; The bias circuit includes a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a fourth PMOS transistor MP4, a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3 and a current source ; The Rail-to-Rail input stage includes fifth PMOS transistor MP5, sixth PMOS transistor MP6, seventh PMOS transistor MP7, eighth PMOS transistor MP8, ninth PMOS transistor MP9, tenth PMOS transistor MP10, eleventh PMOS transistor Tube MP11, twelfth PMOS tube MP12, fourth NMOS tube MN4, fifth NMOS tube MN5, sixth NMOS tube MN6, seventh NMOS tube MN7, eighth NMOS tube MN8, ninth NMOS tube MN9, tenth NMOS tube MN10, an eleventh NMOS transistor MN11, a first resistor RSN and a second resistor RSP; The Push-Pull output stage includes a thirteenth PMOS transistor MP13, a fourteenth PMOS transistor MP14, a fifteenth PMOS transistor MP15, a sixteenth PMOS transistor MP16, a seventeenth PMOS transistor MP17, an eighteenth PMOS transistor MP18, The twelfth NMOS transistor MN12, the thirteenth NMOS transistor MN13, the fourteenth NMOS transistor MN14, the fifteenth NMOS transistor MN15, the sixteenth NMOS transistor MN16, the seventeenth NMOS transistor MN17, the third resistor RBP and the fourth resistor RBN; where, The first PMOS transistor MP1, the second PMOS transistor MP2, the third PMOS transistor MP3, the fourth PMOS transistor MP4, the fifth PMOS transistor MP5, the sixth PMOS transistor MP6, the ninth PMOS transistor MP9, the tenth PMOS transistor MP10, the tenth PMOS transistor The source lining terminals of the fifth PMOS transistor MP15, the sixteenth PMOS transistor MP16, the lining terminals of the eleventh PMOS transistor MP11, the twelfth PMOS transistor MP12, the seventeenth PMOS transistor MP17, and the eighteenth PMOS transistor MP18 are connected to the power supply voltage; The gate-drain terminal of the first PMOS transistor MP1, the gate terminal of the second PMOS transistor MP2, the gate terminal of the third PMOS transistor MP3, the gate terminal of the fifth PMOS transistor MP5, and the gate terminal of the sixth PMOS transistor MP6 are all connected to the positive current source. To the terminal, the negative terminal of the current source is grounded; The gate-drain terminal of the first NMOS transistor MN1, the gate terminal of the tenth NMOS transistor MN10, the gate terminal of the eleventh NMOS transistor MN11, the gate terminal of the sixteenth NMOS transistor MN16, and the gate terminal of the seventeenth NMOS transistor MN17 are all connected to The drain end of the second PMOS transistor MP2 is connected; The gate-drain end of the second NMOS transistor MN2, the gate end of the third NMOS transistor MN3, the gate end of the fourth NMOS transistor MN4, the gate end of the fifth NMOS transistor MN5, the gate end of the eighth NMOS transistor MN8, the gate end of the ninth NMOS transistor The gate terminals of MN9 are all connected to the drain terminal of the third PMOS transistor MP3; The gate-drain terminal of the fourth PMOS transistor MP4, the gate terminal of the eleventh PMOS transistor MP11, the gate terminal of the twelfth PMOS transistor MP12, the gate terminal of the seventeenth PMOS transistor MP17, and the gate terminal of the eighteenth PMOS transistor MP18 are all connected to the drain end of the third NMOS transistor MN3; The gate terminal of the sixth NMOS transistor MN6 is connected to the gate terminal of the seventh PMOS transistor MP7 as an input terminal, and the gate terminal of the seventh NMOS transistor MN7 is connected to the gate terminal of the eighth PMOS transistor MP8 as another input terminal. The source liner end of the sixth NMOS transistor MN6 and the source liner end of the seventh NMOS transistor MN7 are respectively connected to the drain end of the fourth NMOS transistor MN4 and the drain end of the fifth NMOS transistor MN5 and bridged through the first resistor RSN; The source liner end of the seventh PMOS transistor MP7 and the source liner end of the eighth PMOS transistor MP8 are respectively connected to the drain end of the fifth PMOS transistor MP5 and the drain end of the sixth PMOS transistor MP6 and bridged through the second resistor RSP; The drain end of the ninth PMOS transistor MP9, the source end of the eleventh PMOS transistor MP11 are connected to the drain end of the seventh NMOS transistor MN7; the drain end of the tenth PMOS transistor MP10, the source end of the twelfth PMOS transistor MP12 and the The drain terminals of the six NMOS transistors MN6 are connected; The drain end of the eighth NMOS transistor MN8, the source end of the tenth NMOS transistor MN10 are connected to the drain end of the eighth PMOS transistor MP8; the drain end of the ninth NMOS transistor MN9, the source end of the eleventh NMOS transistor MN11 and the seventh The drain end of the PMOS transistor MP7 is connected; The gate end of the ninth PMOS transistor MP9, the gate end of the tenth PMOS transistor MP10, and the drain end of the eleventh PMOS transistor MP11 are all connected to the drain end of the tenth NMOS transistor MN10; the drain end of the twelfth PMOS transistor MP12, The source end of the fourteenth PMOS transistor MP14 and the source end of the thirteenth NMOS transistor MN13 are connected to the drain end of the eleventh NMOS transistor MN11; The drain gate terminal of the twelfth NMOS transistor MN12 and the gate terminal of the thirteenth NMOS transistor MN13 are connected to the third resistor RBP to the power supply; the drain gate terminal of the thirteenth PMOS transistor MP13 and the gate terminal of the fourteenth PMOS transistor MP14 are connected to the fourth resistor RBN to ground potential, the source end of the twelfth NMOS transistor MN12 is connected to the source end of the thirteenth PMOS transistor MP13; The gate end of the fifteenth PMOS transistor MP15, the gate end of the sixteenth PMOS transistor MP16, and the drain end of the seventeenth PMOS transistor MP17 are all connected to the drain end of the thirteenth NMOS transistor MN13; the drain end of the fourteenth NMOS transistor MN14 The gate terminal, the gate terminal of the fifteenth NMOS transistor MN15, and the drain terminal of the sixteenth NMOS transistor MN16 are all connected to the drain terminal of the fourteenth PMOS transistor MP14; The drain end of the fifteenth PMOS transistor MP15 and the drain end of the sixteenth PMOS transistor MP16 are respectively connected to the source end of the seventeenth PMOS transistor MP17 and the source end of the eighteenth PMOS transistor MP18; The drain end of the fourteenth NMOS transistor MN14 and the drain end of the fifteenth NMOS transistor MN15 are respectively connected to the source end of the sixteenth NMOS transistor MN16 and the source end of the seventeenth NMOS transistor MN17; The drain end is connected to the drain end of the eighteenth PMOS transistor MP18 as an output end; The first NMOS transistor MN1, the second NMOS transistor MN2, the third NMOS transistor MN3, the fourth NMOS transistor MN4, the fifth NMOS transistor MN5, the eighth NMOS transistor MN8, the ninth NMOS transistor MN9, the fourteenth NMOS transistor MN14, the The source lining end of the fifteenth NMOS transistor MN15, the tenth NMOS transistor MN10, the eleventh NMOS transistor MN11, the twelfth NMOS transistor MN12, the thirteenth NMOS transistor MN13, the sixteenth NMOS transistor MN16, and the seventeenth NMOS transistor MN17 The pad ends are at ground potential.