CN103839814A - Method for forming fin field effect transistor - Google Patents

Abstract

A method for forming a fin field effect transistor, comprising: providing a semiconductor substrate; forming a hard mask layer on the surface of the semiconductor substrate; using the hard mask layer as a mask, etching the semiconductor substrate to form fins; Form a dummy gate on the surface of the semiconductor substrate, the dummy gate spans and covers the first channel region of the fin and the hard mask layer on the top; forms a dielectric covering the source and drain of the fin on both sides of the dummy gate layer; remove the dummy gate to expose the first channel region of the fin and the hard mask layer on the top; etch the first channel region to reduce its width to form a second channel region; form a lateral across and overly the gate of the second channel region. The forming method of the fin field effect transistor can reduce the resistance of the source and drain and increase the driving current of the transistor.

Description

Method for forming fin field effect transistor

technical field

The invention relates to the technical field of semiconductors, in particular to a method for forming a fin field effect transistor.

Background technique

With the continuous development of semiconductor process technology, the process node is gradually reduced, and the gate-last (gate-last) process has been widely used to obtain an ideal threshold voltage and improve device performance. However, when the feature size (CD, Critical Dimension) of the device is further reduced, even the field effect transistor fabricated by the gate-last process can no longer meet the demand for device performance, and multi-gate devices have received widespread attention.

A Fin Field Effect Transistor (Fin FET) is a common multi-gate device. FIG. 1 shows a three-dimensional schematic diagram of a fin and gate structure of a fin field effect transistor in the prior art. As shown in FIG. 1 , it includes: a semiconductor substrate 10 on which a protruding fin 14 is formed; a dielectric layer 11 covering the surface of the semiconductor substrate 10 and the sidewall of the fin 14 A part; a gate structure 12, spanning the fin portion 14 and covering the top and sidewalls of the fin portion 14, the gate structure 12 includes a gate dielectric layer (not shown in the figure) and a gate dielectric layer located on the gate dielectric layer gate electrode (not shown in the figure). The top of the fin 14 in contact with the gate structure 12 and the sidewalls on both sides form a channel region. Therefore, the Fin FET has multiple gates, which is beneficial to increase the driving current and improve device performance.

However, as the size of the fin decreases, the areas of the source and drain regions at both ends of the fin also decrease accordingly, resulting in an increase in the contact resistance of the source and drain, resulting in a decrease in the driving current, thereby affecting the performance of the device. In the formation technique, after the fin transistor is formed, sidewalls are formed on the sidewalls of the gate and the sidewalls of the source and drain of the transistor. An existing method for reducing the source and drain resistance is to remove the sidewalls on both sides of the source and drain, and then form an epitaxial silicon layer on the surface of the source and drain to increase the area of the source and drain regions, thereby reducing the source-drain resistance. However, this method, on the one hand, will hinder the formation of the epitaxial layer on the surface of the source and drain due to incomplete removal of the bottom sidewall, and on the other hand, will also remove the sidewall of the source and drain sidewalls at the same time. Removing part of the side wall of the gate side wall will result in the formation of epitaxial layers on the surface of the source, drain and gate at the same time. When the epitaxial layer on the source, drain and gate reaches a certain thickness, it will cause the source, drain and gate. Bridging of the epitaxial layer between the drain and gate, resulting in a short circuit between the source, drain and gate.

For more information about the structure and formation method of the FinFET, please refer to the US Patent No. "US7868380B2".

Contents of the invention

The problem to be solved by the present invention is to provide a method for forming a fin field effect transistor, which can reduce the resistance of the source and drain and increase the driving current of the transistor.

In order to solve the above problems, the present invention provides a method for forming a fin field effect transistor, comprising: providing a semiconductor substrate; forming a hard mask layer on the surface of the semiconductor substrate; using the hard mask layer as a mask, engraving Etching the semiconductor substrate to form a fin; forming a dummy gate on the surface of the semiconductor substrate, the dummy gate spans and covers the first channel region of the fin and the hard mask layer on the top thereof, the first channel region Located in the middle of the fin, both sides of the first channel region are the source and drain of the fin; a dielectric layer covering the source and drain of the fin is formed on both sides of the dummy gate, and the surface of the dielectric layer is connected to the The surface of the dummy gate is flush; the dummy gate is removed to expose the first channel region of the fin and the hard mask layer on the top; both sides of the first channel region are etched to reduce its width to form a second A second channel region; forming a gate across and covering the second channel region.

Preferably, the method for forming fins includes: after forming a hard mask layer, forming first sidewalls on both sides of the hard mask layer, using the hard mask layer and the sidewalls on both sides As a mask, the semiconductor substrate is etched to form fins.

Preferably, the material of the first sidewall is silicon nitride, amorphous carbon, boron nitride, silicon oxynitride, silicon carbide nitride or silicon oxycarbide.

Preferably, the width of the bottom surface of the first sidewall is greater than 2 nm.

Preferably, the method for forming the second channel region is as follows: removing the first sidewall, and then etching both sides of the first channel region by wet process or dry etching process to make the width The dry etching process uses the hard mask layer as a mask to perform vertical etching.

Preferably, the method for forming fins includes: using the hard mask layer as a mask, etching the semiconductor substrate to form pre-processing fins, and then growing epitaxial layers on both sides of the pre-processing fins , forming fins.

Preferably, the epitaxial layer is a single-layer or multi-layer structure.

Preferably, the material of the epitaxial layer is silicon, silicon germanium or silicon carbide.

Preferably, the method for forming the second channel region is: using wet etching or dry etching process to etch both sides of the first channel region to reduce its width, and the dry etching The plasma direction of etching is in the horizontal plane, perpendicular to the sidewall of the first channel region.

Preferably, the thickness of the hard mask layer is greater than 10 nm.

Preferably, the width of the fin is larger than 30nm.

Preferably, the width of the second channel region is greater than 10 nm.

Preferably, the material of the hard mask layer is silicon nitride, amorphous carbon, boron nitride, silicon oxynitride, silicon carbide nitride or silicon oxycarbide.

Preferably, the material of the dummy gate is polysilicon.

Preferably, the material of the dielectric layer includes silicon oxide, silicon nitride or silicon oxynitride.

Preferably, the method further includes: after forming the second channel region, forming a second sidewall on the sidewall surface of the dielectric layer facing the second channel region.

Preferably, the material of the second side wall is silicon nitride, amorphous carbon, boron nitride, silicon oxynitride, silicon carbide nitride or silicon oxycarbide.

Preferably, the gate is a high-K metal gate or a polysilicon gate.

Compared with the prior art, the present invention has the following advantages:

In the technical solution of the present invention, after the fin is formed on the surface of the semiconductor substrate, a dummy gate is formed in the first channel region of the fin, and after a medium covering the source and drain of the fin is formed on both sides of the dummy gate, the The dummy gate exposes the first channel region of the fin, and the width of the first channel region is reduced by etching to form a second channel region. Finally, a fin with a large source-drain width and a small channel region width is formed. In the technical solution of the present invention, after forming a fin with a large width first, the channel region of the fin is thinned, and at the same time, the source and drain are protected by a dielectric layer covering the source and drain, so that the size of the source and drain is maintained. Therefore, while obtaining the required width of the channel region, the dimensions of the source and the drain are increased, the resistance of the source and the drain of the transistor is effectively reduced, and the driving current of the transistor is increased.

Further, by growing epitaxial layers on both sides of the pre-treated fin, a fin with a larger width is obtained. The epitaxial layer may be a single layer of silicon, silicon germanium or silicon carbide, or may have a multilayer structure, and the materials of adjacent single layers of each layer are different from each other. The epitaxial layer can exert stress on the channel region and improve the mobility of carriers in the channel. If the formed epitaxial layer is a silicon germanium layer, it helps to increase the tensile stress in the channel region, improves the mobility of electrons in the channel, and helps to improve the performance of NMOS; the epitaxial layer is a silicon carbide layer. The compressive stress in the channel region increases the mobility of holes in the channel, which helps to improve the performance of PMOS. For different types of MOS transistors, the structure and material of the epitaxial layer can be adjusted to obtain suitable stress. The technical solution can improve the carrier mobility of the transistor while reducing the source-drain resistance.

Description of drawings

FIG. 1 is a schematic diagram of an existing fin transistor;

2 to 16 are schematic diagrams of forming fin field effect transistors in the first embodiment of the present invention;

17 to 26 are schematic diagrams of forming FinFETs in the second embodiment of the present invention.

Detailed ways

As mentioned in the background technology, in the existing fin field effect transistor, as the size of the fin decreases, the areas of the source and drain regions at both ends of the fin also decrease accordingly, resulting in an increase in the contact resistance of the source and drain, and a decrease in the driving current. , thereby affecting the performance of the device. In the prior art, the source and drain are generally grown epitaxially to increase the size of the source and drain regions after the fin field effect transistor is formed, but this method has the problems of low deposition quality and easy short circuit between the source, drain and gate.

In order to solve the above problems, the present invention proposes a method for forming a Fin Field Effect Transistor. Firstly, a larger-sized fin is formed, and then the width of the channel region of the fin is thinned. After obtaining a smaller-sized trench Larger source and drain regions are obtained while the channel region is obtained, thereby reducing the resistance of the source and drain.

In order to make the above objects, features and advantages of the present invention more comprehensible, specific implementations of the present invention will be described in detail below in conjunction with the accompanying drawings. The described embodiments are some, but not all, of the possible implementations of the invention. When describing the embodiments of the present invention in detail, for convenience of explanation, the schematic diagrams will not be partially enlarged according to the general scale, and the schematic diagrams are only examples, which shall not limit the protection scope of the present invention. In addition, the three-dimensional space dimensions of length, width and depth should be included in actual production. According to the embodiments, all other implementation manners that can be obtained by those skilled in the art without creative effort belong to the protection scope of the present invention. Accordingly, the invention is not limited to the specific implementations disclosed below.

first embodiment

Referring to FIG. 2 , a semiconductor substrate 110 is provided.

The material of the semiconductor substrate 110 includes semiconductor materials such as silicon, germanium, silicon germanium, gallium arsenide, etc., and may be a bulk material or a composite structure such as silicon-on-insulator or germanium-on-insulator. Those skilled in the art can select the type of the semiconductor substrate 110 according to the semiconductor devices formed on the semiconductor substrate 110 , so the type of the semiconductor substrate should not limit the protection scope of the present invention.

In this embodiment, the material of the semiconductor substrate 110 used is silicon-on-insulator, including a silicon substrate layer 100 , a middle silicon oxide layer 101 and a single crystal silicon top layer 102 .

Referring to FIG. 3 , a hard mask material layer 200 is formed on the surface of the semiconductor substrate 110 .

Specifically, a hard mask material layer is deposited on the surface of the semiconductor substrate 110 through a chemical vapor deposition process. The material of the hard mask material layer is other suitable materials such as silicon nitride, amorphous carbon, boron nitride, silicon oxynitride, silicon carbide nitride, or silicon carbide oxide.

Referring to FIG. 4 , a hard mask layer 201 is formed on the surface of the semiconductor substrate.

Specifically, the hard mask material layer 200 (please refer to FIG. 3 ) is etched to form a hard mask layer 201, and the thickness of the hard mask layer 201 is greater than 10 nm.

Referring to FIG. 5 , first spacers 202 are formed on both sides of the hard mask layer 201 .

Specifically, the material of the first side wall 202 is silicon nitride, amorphous carbon, boron nitride, silicon oxynitride, silicon nitride carbide or silicon oxycarbide and other suitable materials. The forming method of the first sidewall 202 is: using a chemical vapor deposition process to form a first sidewall material layer covering the surface of the semiconductor substrate and the hard mask layer; using a plasma etching process to vertically etch the The first spacer material layer is until the top surface of the hard mask layer 201 and the surface of the semiconductor substrate are exposed, and the first sidewalls 202 are formed on both sides of the hard mask layer 201 . The bottom width of the first sidewall is greater than 2nm. The total width of the bottom of the first spacer and the hard mask layer is larger than 30nm. In other embodiments of the present invention, the first sidewall may not be formed, only a hard mask layer is formed, and the width of the hard mask layer is made greater than 30 nm.

Referring to FIG. 6 , using the hard mask layer 201 and the first sidewalls 202 on both sides thereof as a mask, the semiconductor substrate is etched to form fins 300 .

Specifically, in this embodiment, the single crystal silicon top layer 102 of the semiconductor substrate (please refer to FIG. 5 ) is etched by a dry etching process to form fins 300 , and the width of the formed fins 300 is greater than 30 nm. In other embodiments of the present invention, if the first sidewall 202 is not formed, the semiconductor substrate is directly etched using the hard mask layer 201 as a mask to form a fin with a width greater than 30 nm.

Referring to FIG. 7 , a dummy gate 400 is formed spanning and covering the first channel region of the fin, and the hard mask layer 201 and the first spacer 202 on top of it.

Specifically, the material of the dummy gate 400 is polysilicon. The first channel region of the fin is located in the middle of the fin. The process of forming the dummy gate is: forming a layer of polysilicon layer covering the fin and its top hard mask layer and sidewall on the surface of the substrate, and planarizing it; The mask layer of the channel region. After etching the polysilicon layer with the mask layer as a mask, the source and drain regions at both ends of the fin, as well as the hard mask layer and the top of the source and drain regions are exposed. side wall. In other embodiments of the present invention, if bulk silicon or other materials are used as the semiconductor substrate, after forming the fins and before forming dummy gates, an insulating layer is formed on the surface of the substrate as the subsequently formed gate and substrate. insulating layer between the bottom.

Referring to FIG. 8 , a dielectric layer 401 covering the source and drain of the fin is formed on both sides of the dummy gate 400 .

Specifically, the material of the dielectric layer is silicon nitride or silicon oxynitride. The method for forming the dielectric layer 401 is: using a chemical vapor deposition process, depositing a dielectric material on both sides of the dummy gate, covering the source and drain of the fin, and then planarizing it to form the dielectric layer 401. The height of the dielectric layer 401 is equal to that of the dummy gate 400 . The dielectric layer 401 covers the source and drain of the fin, so that the source and drain are protected in the subsequent process and the size will not change.

Referring to FIG. 9 , the dummy gate 400 (please refer to FIG. 8 ) is removed to expose the first channel region of the fin and the hard mask layer and the first spacer on the top thereof.

Specifically, the process of removing the dummy gate is wet etching or dry etching.

Please refer to FIG. 10 , which is a top view of FIG. 9 after removing the dummy gate.

The channel region (not shown) is located in the middle region not covered by the dielectric layer 401 and is covered by the first spacer 202 and the hard mask layer 201 .

Please refer to FIG. 11 , which is a schematic cross-sectional view along the direction AA' after removing the dummy gate.

The first channel region 301 of the fin is located on the silicon oxide layer 101 and covered by the hard mask layer 201 and the first spacer 202 .

Referring to FIG. 12 , the first channel region 301 (please refer to FIG. 11 ) is etched to reduce its width to form a second channel region 302 .

Specifically, in this embodiment, the method of etching the first channel region 301 to form the second channel region 302 is a wet etching process. In other embodiments of the present invention, a dry etching process may also be used, and the plasma direction of the dry etching is in the horizontal plane and perpendicular to the sidewall of the channel region. The width of the formed second channel region 302 is greater than 10 nm.

In other embodiments of the present invention, the first sidewall 202 may also be removed first to expose the part of the first channel region not covered by the hard mask layer 201, and then use the hard mask layer 201 as a mask, The first channel region is vertically etched by a dry etching process to form a second channel region 302 . In other embodiments of the present invention, the first sidewall may not be formed after the formation of the hard mask layer 201. In such a case, the first trench may be etched using a wet process or a dry etching process. region, the plasma direction of the dry etching is in the horizontal plane and perpendicular to the sidewall of the channel region.

Referring to FIG. 13 , remove the first side wall 202 (please refer to FIG. 12 ).

Please refer to FIG. 14 , which is a top view after removing the first side wall 202 (please refer to FIG. 12 ).

The top of the second channel region 302 (please refer to FIG. 13 ) only has the hard mask layer 201 .

Referring to FIG. 15 , a second sidewall 402 is formed on the sidewall surface of the dielectric layer 401 facing the second channel region of the fin.

Specifically, the material of the second sidewall is silicon nitride, amorphous carbon, boron nitride, silicon oxynitride, silicon nitride carbide, silicon oxycarbide and other suitable materials.

The second sidewall can make up for the damage caused to the dielectric layer 401 on both sides during the etching process of the first channel region, keep the surface flat, and improve the deposition quality of the subsequently formed gate.

Referring to FIG. 16 , a gate 500 is formed across and covering the second channel region.

Specifically, in this embodiment, the gate 500 is a high-k metal gate, and the formation method is as follows: first deposit a high-k dielectric layer, and the high-k dielectric can be HfO ₂ , La ₂ O ₃ , HfSiON or High-k materials such as HfAlO ₂ . A metal layer is then formed on the surface of the high-K dielectric layer, followed by planarization. In other embodiments of the present invention, the gate 500 may also be a polysilicon gate. In other embodiments of the present invention, the gate 500 may also be formed after removing the hard mask layer 201 (please refer to FIG. 15 ).

In this embodiment, plasma implantation is performed on the source and drain regions before forming the gate.

In this embodiment, after forming a fin with a relatively large width, the source and drain regions are covered and protected with a dielectric layer, and then the first channel region of the fin is etched to reduce its width to form a large source and drain region. , fins with small channel region dimensions. Under the condition that the size of the channel region is satisfied, the size of the source and drain is increased, thereby reducing the source and drain resistance and increasing the driving current of the transistor. Moreover, the source and drain of the transistor are protected by the dielectric layer, and will not form a short circuit with the gate formed later.

second embodiment

This embodiment also provides another method for forming a FinFET.

Referring to FIG. 17 , using the same method as the first embodiment, after forming the hard mask layer 201 on the surface of the substrate, the semiconductor substrate is etched to form the pre-processing fins 500 .

Referring to FIG. 18 , an epitaxial layer 501 is grown on the sidewall of the pre-processing fin, and the pre-processing fin 500 and the epitaxial layer 501 on both sides thereof form a fin 510 .

Specifically, in this embodiment, the material of the epitaxial layer 501 is silicon. In other embodiments of the present invention, the material of the epitaxial layer 501 may also be silicon germanium or silicon carbide. The epitaxial layer 501 can be a single-layer silicon, silicon germanium or silicon carbide structure, or a multi-layer structure formed of multiple layers of different materials. For example, a layer of germanium is first grown on the sidewall of the pre-treated fin. silicon, and then grow a silicon carbide layer on the surface of the silicon germanium. The formation of silicon germanium layer helps to increase the tensile stress of the channel region and the mobility of electrons in the channel, which is suitable for NMOS; while the silicon carbide layer helps to increase the compressive stress of the channel region and improve the migration of holes in the channel rate, applicable to PMOS. In a specific embodiment, the structure and material of the epitaxial layer can be adjusted for different types of MOS to obtain proper stress. The width of the fin portion 510 is greater than 30 nm.

Referring to FIG. 19 , a dummy gate 600 is formed across and covering the first channel region of the fin 510 and the hard mask layer 201 on top thereof.

Specifically, the material of the dummy gate 600 is polysilicon. The first channel region of the fin is located in the middle of the fin. The process of forming the dummy gate is: forming a layer of polysilicon layer covering the fin and its top hard mask layer and sidewall on the surface of the substrate, and planarizing it; The mask layer of the channel region, after etching the polysilicon layer using the mask layer as a mask, exposes the source and drain regions at both ends of the fin, and the hard mask layer and sidewalls on the top. In other embodiments of the present invention, if bulk silicon or other materials are used as the semiconductor substrate, after forming the fins and before forming dummy gates, an insulating layer is formed on the surface of the substrate as the subsequently formed gate and substrate. insulating layer between the bottom.

Referring to FIG. 20 , a dielectric layer 601 covering the source and drain of the fin is formed on both sides of the dummy gate 600 .

Specifically, the material of the dielectric layer includes silicon oxide, silicon nitride or silicon oxynitride. The method for forming the dielectric layer 601 is: using a chemical vapor deposition process, depositing a dielectric material on both sides of the dummy gate, covering the source and drain of the fin, and then planarizing it to form a dielectric layer. The height of the layer is flush with the height of the dummy gate. The dielectric layer covers the source and drain of the fin, so that the source and drain are protected in the subsequent process and the size will not change.

Referring to FIG. 21 , the dummy gate 600 (please refer to FIG. 20 ) is removed to expose the first channel region of the fin and the hard mask layer on top.

Please refer to FIG. 22 , which is a top view after removing the dummy gate 600 .

Please refer to FIG. 23 , which is a cross-sectional view along the BB' direction of FIG. 22 , the width of the first channel region 502 is greater than the width of the hard mask layer 201 . The first channel region is located in the middle of the fin, the region not covered by the dielectric layer 601 (please refer to FIG. 22 ), including part of the epitaxial layer and part of the pre-processed fin.

Referring to FIG. 24 , the first channel region 502 (please refer to FIG. 23 ) is etched to reduce its width to form a second channel region 503 .

Specifically, in this embodiment, the method of etching the first channel region 502 to form the second channel region 503 is a wet etching process. In other embodiments of the present invention, a dry etching process may also be used, and the plasma direction of the dry etching is in the horizontal plane and perpendicular to the sidewall of the channel region. The width of the formed second channel region 503 is greater than 10 nm. In other embodiments of the present invention, the first channel region may be vertically etched by using the hard mask layer 201 as a mask by a dry etching process to form the second channel region 503 . The width of the second channel region 503 is greater than 10 nm.

Referring to FIG. 25 , a second sidewall 602 is formed on the sidewall surface of the dielectric layer 601 facing the second channel region of the fin.

Specifically, the material of the second sidewall is silicon nitride, amorphous carbon, boron nitride, silicon oxynitride, silicon nitride carbide, silicon oxycarbide and other suitable materials.

The second sidewall can compensate for the damage caused to the dielectric layer 601 on both sides during the etching process of the first channel region, keep the surface flat, and improve the deposition quality of the subsequently formed gate.

Referring to FIG. 26 , a gate 700 is formed across and covering the second channel region.

Specifically, in this embodiment, the gate 700 is a high-k metal gate, and the formation method is as follows: first deposit a high-k dielectric layer, and the high-k dielectric can be HfO ₂ , La ₂ O ₃ , HfSiON or High-k materials such as HfAlO ₂ . A metal layer is then formed on the surface of the high-K dielectric layer, followed by planarization. In other embodiments of the present invention, the gate 700 may also be a polysilicon gate. In other embodiments of the present invention, the gate 700 may also be formed after the hard mask layer 201 (please refer to FIG. 25 ).

In this embodiment, plasma implantation is performed on the source and drain regions before forming the gate.

In this embodiment, the pre-treatment fins are formed first, and then epitaxial layers are grown on both sides of the pre-treatment fins to form fins with larger widths. The source and drain regions are covered and protected by a dielectric layer, and then the first channel region of the fin is etched to reduce its width to form a fin with a large source and drain size and a small channel region. Under the condition that the size of the channel region is satisfied, the size of the source and drain is increased, thereby reducing the source and drain resistance and increasing the driving current of the transistor. Moreover, the source and drain of the transistor are protected by the dielectric layer, and will not form a short circuit with the gate formed later. In addition, the epitaxial layer can be a single layer or multi-layer silicon germanium, silicon carbide and other materials, which can exert stress on the channel region and increase the mobility of carriers in the channel. For example, forming the epitaxial layer is a silicon germanium layer, which helps to increase the tensile stress in the channel region, improves the mobility of electrons in the channel, and helps to improve the performance of NMOS; the epitaxial layer is a silicon carbide layer. Increasing the compressive stress in the channel region and increasing the mobility of holes in the channel will help improve the performance of the PMOS. For different types of MOS transistors, the structure and material of the epitaxial layer can be adjusted to obtain suitable stress.

The above descriptions through the embodiments should enable those skilled in the art to better understand the present invention, and to be able to reproduce and use the present invention. It is obvious to those skilled in the art that various changes and modifications can be made to the above-mentioned embodiments based on the principles described herein without departing from the spirit and scope of the present invention. Accordingly, the present invention should not be construed as limited to the above-described embodiments shown herein, but its protection scope should be defined by the appended claims.

Claims (18)

1. a formation method for fin formula field effect transistor, is characterized in that, comprising:

Semiconductor substrate is provided;

Form hard mask layer at semiconductor substrate surface;

Taking described hard mask layer as mask, etching semiconductor substrate, forms fin;

Form pseudo-grid at semiconductor substrate surface, described pseudo-grid across and cover the first channel region of fin and the hard mask layer at top thereof, described the first channel region is positioned at the middle part of fin, source electrode and drain electrode that described the first channel region both sides are fin;

Form in pseudo-grid both sides and cover the source electrode of fin and the dielectric layer of drain electrode, described dielectric layer surface and pseudo-grid flush;

Remove pseudo-grid, expose the first channel region of fin and the hard mask layer at top thereof;

The both sides of the first channel region described in etching, reduce its width, form the second channel region;

Form across and cover the grid of the second channel region.

2. the formation method of fin formula field effect transistor according to claim 1, it is characterized in that, the method of described formation fin comprises: after forming hard mask layer, form the first side wall in the both sides of described hard mask layer, using the side wall of described hard mask layer and both sides thereof as mask, etching semiconductor substrate, forms fin.

3. the formation method of fin formula field effect transistor according to claim 2, is characterized in that, the material of described the first side wall is silicon nitride, amorphous carbon, boron nitride, silicon oxynitride, fire sand or siloxicon.

4. the formation method of fin formula field effect transistor according to claim 2, is characterized in that, the bottom width of described the first side wall is greater than 2nm.

5. the formation method of fin formula field effect transistor according to claim 2, it is characterized in that, the method that forms the second channel region described quarter is: remove described the first side wall, then adopt the both sides of the first channel region described in wet processing or dry etch process etching, its width is reduced, described dry etch process, taking hard mask layer as mask, is carried out vertical etching.

6. the formation method of fin formula field effect transistor according to claim 1, it is characterized in that, the method of described formation fin comprises: taking described hard mask layer as mask, after described in etching, Semiconductor substrate forms preliminary treatment fin, at described preliminary treatment fin both sides grown epitaxial layer, form fin again.

7. the formation method of fin formula field effect transistor according to claim 6, is characterized in that, described epitaxial loayer is single or multiple lift structure.

8. the formation method of fin formula field effect transistor according to claim 6, is characterized in that, the material of described epitaxial loayer is silicon, SiGe or carborundum.

9. according to the formation method of the fin formula field effect transistor described in claim 1,2 or 6, it is characterized in that, the method that forms the second channel region is: the both sides of the first channel region described in employing wet etching or dry etch process etching, its width is reduced, the sidewall of vertical described first channel region of plasma direction of described dry etching.

10. the formation method of fin formula field effect transistor according to claim 1, is characterized in that, the thickness of described hard mask layer is greater than 10nm.

11. according to the formation method of the fin formula field effect transistor described in claim 1,2 or 6, it is characterized in that, the width of described fin is greater than 30nm.

12. according to the formation method of the fin formula field effect transistor described in claim 1,2 or 6, it is characterized in that, the width of described the second channel region is greater than 10nm.

The formation method of 13. fin formula field effect transistors according to claim 1, is characterized in that, the material of described hard mask layer is silicon nitride, amorphous carbon, boron nitride, silicon oxynitride, fire sand or siloxicon.

The formation method of 14. fin formula field effect transistors according to claim 1, is characterized in that, the material of described pseudo-grid is polysilicon.

The formation method of 15. fin formula field effect transistors according to claim 1, is characterized in that, the material of described dielectric layer comprises silica, silicon nitride or silicon oxynitride.

16. according to the formation method of the fin formula field effect transistor described in claim 1,2 or 6, it is characterized in that, also comprises: after forming the second channel region, form the second side wall in the sidewall surfaces towards the second channel region of described dielectric layer.

The formation method of 17. fin formula field effect transistors according to claim 16, is characterized in that, the material of described the second side wall is silicon nitride, amorphous carbon, boron nitride, silicon oxynitride, fire sand or siloxicon.

The formation method of 18. fin formula field effect transistors according to claim 1, is characterized in that, described grid is high-K metal grid or polysilicon gate.

Images