CN103928327B - Fin formula field effect transistor and forming method thereof - Google Patents

Abstract

A Fin Field Effect Transistor and its forming method, wherein the forming method of the Fin Field Effect Transistor comprises: providing a semiconductor substrate, the surface of the semiconductor substrate has raised fins, and the fins located on the fins a gate structure, the gate structure covers part of the top and sidewalls of the fin; forming a first dielectric layer covering the gate structure; forming a second dielectric layer covering the first dielectric layer, the The dielectric constant of the second dielectric layer is smaller than the dielectric constant of the first dielectric layer; etching back the second dielectric layer to form a second spacer; using the second sidewall as a mask to etch the The first dielectric layer forms a first side wall, the first side wall has a horizontal part and a vertical part, and the part of the fin covered by the first side wall forms a negative cover area. The parasitic capacitance between the gate structure of the fin field effect transistor of the present invention and the conductive plugs in the source region and the drain region is small.

Description

Fin field effect transistor and method of forming the same

technical field

The invention relates to the technical field of semiconductors, in particular to a fin field effect transistor and a forming method thereof.

Background technique

MOS transistors generate switching signals by regulating the current through the channel region by applying a voltage to the gate. With the development of semiconductor technology, the control ability of the traditional planar MOS transistor on the channel current becomes weaker, resulting in serious leakage current. Fin Field Effect Transistor (Fin FET) is an emerging multi-gate device, which generally includes a semiconductor fin protruding from the surface of the semiconductor substrate, and a gate structure covering part of the top and side walls of the fin, A source region and a drain region are located in the fins on both sides of the gate structure.

But below the 20nm node, the thickness of the fin field effect transistor fin is extremely small, and the short channel effect is obvious, such as the threshold voltage is sensitive to the channel length change, the carrier velocity saturation effect, the hot carrier effect and the subthreshold characteristic degradation, etc. In order to solve the above problems, the prior art proposes FinFETs with underlaps. Please refer to FIG. 1, which is a schematic cross-sectional structure diagram of a fin field effect transistor with a negative cover region, including: a semiconductor substrate 100; a protruding fin 101 located on the semiconductor substrate 100, and the fin 101 passes through The semiconductor substrate 100 is etched to form; the gate dielectric layer 103 covering part of the surface of the fin portion 101; the gate electrode layer 104 located on the gate dielectric layer 103; the gate dielectric layer 103 and the gate electrode layer 104 sidewalls 105 on both sides of the electrode layer 104; source and drain regions 102 in the fins 101 on both sides of the gate electrode layer 104; negative cover regions 106 in the fins 101 below the sidewalls 105, The doping concentration of the negative cover region 106 is the same as the doping concentration of the FinFET channel region (not shown).

In the above-mentioned fin field effect transistor with the negative cover region 106, because the negative cover region 106 is not subjected to lightly doped drain implantation (LDD) and halo implantation (Halo Implantation), the negative cover region 106 The doping concentration of the doping concentration is the same as that of the channel region of the fin field effect transistor, which increases the length of the effective channel region and alleviates the short channel effect. However, due to the existence of the negative cover region 106, the channel resistance increases, resulting in a decrease in the driving current of the FinFET. Therefore, in the FinFET with the negative cover region 106, the sidewall 105 is usually It is formed by using a dielectric material with a relatively high dielectric constant, and the purpose of increasing the driving current of the FinFET is achieved by increasing the capacitance value of the negative covering region 106 .

However, in the prior art, the sidewalls of fin field effect transistors with negative cover regions are formed with high dielectric constant materials, which increases the parasitic capacitance between the gate electrode and the subsequently formed conductive plugs in the source region and drain region, affecting Transistor performance.

For other methods of forming FinFETs with negative capping regions, reference can also be made to US Patent Application Publication No. US2005/0275045A1.

Contents of the invention

The problem solved by the invention is that the parasitic capacitance between the gate electrode and the conductive plugs in the source region and the drain region of the fin field effect transistor with the negative covering region in the prior art is large.

In order to solve the above problems, the present invention provides a method for forming a fin field effect transistor, comprising: providing a semiconductor substrate, the surface of the semiconductor substrate has raised fins, and a gate structure located on the fins , the gate structure covers part of the top and sidewall of the fin; forming a first dielectric layer covering the gate structure; forming a second dielectric layer covering the first dielectric layer, the second dielectric layer The dielectric constant of the layer is smaller than the dielectric constant of the first dielectric layer; etching back the second dielectric layer to form a second spacer; etching the first dielectric layer using the second side wall as a mask layer, forming a first side wall, the first side wall has a horizontal part and a vertical part, and the part of the fin covered by the first side wall constitutes a negative cover area (Gate under lap).

Optionally, the doping concentration of the negative covering region is the same as that of the channel region of the FinFET.

Optionally, the length of the negative masking region ranges from 300 angstroms to 500 angstroms.

Optionally, the length of the negative masking region ranges from 10 angstroms to 50 angstroms.

Optionally, further comprising: forming an isolation dielectric layer covering the fin, the upper surface of the isolation dielectric layer being flush with the upper surface of the gate structure.

Optionally, the method further includes: performing ion implantation on the vertical portion of the first sidewall to reduce the dielectric constant of the vertical portion of the first sidewall.

Optionally, the implanted ions in the ion implantation process are hydrogen ions.

Optionally, the method further includes: forming a third dielectric layer on the second dielectric layer, and forming a third spacer after etching back the third dielectric layer.

Optionally, the material of the third dielectric layer is silicon nitride.

Optionally, it also includes forming embedded source and drain regions in the fins on both sides of the gate structure.

Optionally, the material of the embedded source region and drain region is silicon, silicon germanium or silicon carbide.

Optionally, the embedded source region and drain region are doped with N-type or P-type impurities.

Optionally, the material of the first dielectric layer is one or more of HfO ₂ , Al ₂ O ₃ , ZrO ₂ , HfSiO, HfSiON, HfTaO and HfZrO.

Optionally, the material of the second dielectric layer is one or more of SiCN, SiCON, SiBCN and SiBOCN.

Optionally, the gate structure is a dummy gate.

Optionally, the method further includes: removing the dummy gate, forming a second opening, and forming a high dielectric constant gate dielectric layer and a metal gate in the second opening.

Correspondingly, the present invention also provides a Fin Field Effect Transistor, comprising: a semiconductor substrate having raised fins on the surface of the semiconductor substrate; a gate structure located on the fins, the gate The structure covers part of the top and sidewalls of the fin; the first sidewalls on both sides of the gate structure, the first sidewalls have horizontal parts and vertical parts; the first sidewalls on both sides of the first sidewall The second side wall, the second side wall is located on the horizontal part of the first side wall, the dielectric constant of the second side wall is smaller than the dielectric constant of the first side wall; Negative shaded area in part of the fin below the side wall.

Optionally, the doping concentration of the negative covering region is the same as that of the channel region of the FinFET.

Optionally, the material of the first sidewall is one or more of HfO ₂ , Al ₂ O ₃ , ZrO ₂ , HfSiO, HfSiON, HfTaO and HfZrO, and the material of the second sidewall is SiCN, One or more of SiCON, SiBCN and SiBOCN.

Optionally, third sidewalls located on both sides of the second sidewalls are further included, and the material of the third sidewalls is silicon nitride.

Compared with the prior art, the present invention has the following advantages:

In the method for forming a fin field effect transistor according to an embodiment of the present invention, a first dielectric layer covering the gate structure and a second dielectric layer on the first dielectric layer are formed, and the second dielectric layer is etched back. layer to form a second sidewall, and using the second sidewall as a mask to etch the first dielectric layer to form a first sidewall, so that the first sidewall has a horizontal portion and a vertical portion. Since the first sidewall has a horizontal portion and the first sidewall has a higher dielectric constant, the capacitance value of the negative cover area can be increased to increase the driving current of the FinFET. In addition, since the dielectric constant of the second spacer is smaller than that of the first spacer, after the subsequent formation of conductive plugs in the source region and the drain region, the gate structure and the source region and the drain region can be reduced. Parasitic capacitance between conductive plugs. That is, the first spacer and the second sidewall structure of the embodiment of the present invention can reduce the parasitic capacitance between the gate structure and the source region and the drain region while increasing the capacitance value of the negative cover region.

Further, in the embodiment of the present invention, after the isolation dielectric layer is formed, ion implantation is performed on the vertical part of the first sidewall, and the implanted ions in the ion implantation process are hydrogen ions, because hydrogen ions can be combined with high dielectric The constant dielectric layer material reacts to form a hydrogen-containing dielectric material layer, which reduces the dielectric constant of the vertical part of the first sidewall, and can further reduce the parasitic capacitance between the gate structure and the conductive plugs in the source region and the drain region. And because the first ion implantation is only for the vertical part of the first sidewall, it will not reduce the dielectric constant of the horizontal part of the first sidewall, so it will not affect the capacitance value of the negative covering area.

Correspondingly, the FinFET according to the embodiment of the present invention also has the advantage of reducing the parasitic capacitance between the gate structure and the conductive plugs in the source region and the drain region.

Description of drawings

1 is a schematic diagram of a three-dimensional structure of a fin field effect transistor in the prior art;

2 to 9 are structural schematic diagrams of the formation process of the fin field effect transistor according to the embodiment of the present invention.

detailed description

It can be seen from the background art that the parasitic capacitance between the gate electrode and the conductive plugs in the source region and the drain region of the fin field effect transistor with the negative cover region formed in the prior art is large.

The inventors of the present invention have studied the formation method of the fin field effect transistor with the negative cover region in the prior art, and found that the high dielectric constant sidewalls lead to large parasitic capacitance between the gate electrode and the conductive plugs in the source region and the drain region. the main reason. It can be seen from the formula C=εS/4πkd that in a flat plate capacitor, the capacitance C is inversely proportional to the distance d between the plates, and is inversely proportional to the dielectric constant ε of the dielectric layer between the plates, so it can be reduced by reducing the dielectric of the sidewall material constant to reduce the parasitic capacitance between the gate electrode and the source and drain regions. However, in the fin field effect transistor with a negative cover area, the purpose of using a high dielectric constant dielectric layer for the sidewall is to increase the capacitance of the negative cover area to increase the driving current of the fin field effect transistor, so , the sidewalls cannot simply be replaced by materials with low dielectric constants, but a reasonable sidewall structure needs to be adopted to reduce the distance between the gate electrode and the source and drain regions without reducing the capacitance of the negative cover region. parasitic capacitance.

Based on the above studies, the inventors of the present invention proposed a method for forming a fin field effect transistor. First, a first dielectric layer and a second dielectric layer on the first dielectric layer are formed on the gate structure, and the The dielectric constant of the second spacer is smaller than that of the first sidewall, etching back the second dielectric layer to form a second spacer, and etching the first sidewall by using the second sidewall as a mask. A dielectric layer forms a first side wall, such that the first side wall has a horizontal portion and a vertical portion. The horizontal portion of the first side wall has a higher dielectric constant, which can increase the dielectric constant of the negative covering area. The vertical part of the second sidewall and the first sidewall is located between the gate structure and the conductive plugs in the source region and the drain region. Since the dielectric constant of the second sidewall is small, The parasitic capacitance between the gate structure and the conductive plugs in the source and drain regions can be reduced.

The specific embodiments will be described in detail below in conjunction with the accompanying drawings, and the above-mentioned purpose and advantages of the present invention will be more clear.

2 to 9 are structural schematic diagrams of the formation process of the fin field effect transistor according to the embodiment of the present invention.

2, a semiconductor substrate 200 is provided, the surface of the semiconductor substrate 200 has a raised fin 202, a gate structure 204 located on the fin 202, the gate structure 204 covers part of the fin The top and side walls of section 202.

The semiconductor substrate 200 may be silicon or silicon-on-insulator (SOI), and the semiconductor substrate 200 may also be germanium, silicon germanium, gallium arsenide, or germanium-on-insulator. The surface of the semiconductor substrate 200 has a raised fin 202, and the connection between the fin 202 and the semiconductor substrate 200 can be integrated, for example, the fin 202 is connected to the semiconductor substrate 200 The raised structure formed after etching.

The gate structure 204 is located on the fin 202 , and the gate structure 204 covers part of the top and sidewall of the fin 202 . In this embodiment, the gate structure 204 is a dummy gate, and the material of the dummy gate 204 is polysilicon. The dummy gate 204 is used to reduce the thermal budget of the subsequently formed high dielectric constant gate dielectric layer and metal gate during the gate-last formation process of the high dielectric constant gate dielectric layer and metal gate (HKMG), It is beneficial to adjust the threshold voltage of the MOS transistor. After the dummy gate 204 is removed in a subsequent process, a gate dielectric layer with a high dielectric constant and a metal gate are sequentially formed at the position of the dummy gate 204 .

In another embodiment, the gate structure includes a gate dielectric layer and a gate electrode layer, the gate dielectric layer is made of silicon oxide, and the gate electrode layer is made of polysilicon.

In this embodiment, a shallow trench isolation structure 201 (STI) located on the surface of the semiconductor substrate 200 and covering part of the sidewalls of the fins 202 is also included, which is used to separate different fins in the semiconductor substrate 200 part isolation, the material of the shallow trench isolation structure 201 is silicon oxide, the formation method of the shallow trench isolation structure 201 can refer to the existing process, and will not be repeated here.

Please refer to FIG. 3 . FIG. 3 is a schematic cross-sectional structure view along the AA1 direction during the process of forming the FinFET based on FIG. 2 , and the first dielectric layer 205 covering the gate structure 204 is formed.

Specifically, the first dielectric layer 205 is formed on the gate structure 204 by physical vapor deposition, chemical vapor deposition or atomic layer deposition. The first dielectric layer 205 is used to form first sidewalls in subsequent processes. The material of the first dielectric layer 205 has a relatively high dielectric constant, for example, the material of the first dielectric layer is one of HfO ₂ , Al ₂ O ₃ , ZrO ₂ , HfSiO, HfSiON, HfTaO and HfZrO or Several kinds. Since the first dielectric layer 205 has a relatively high dielectric constant, after the subsequent formation of the first spacer, the capacitance value of the negative cover region (Gate under lap) can be increased to increase the driving current of the FinFET.

Referring to FIG. 4 , a second dielectric layer 206 covering the first dielectric layer 205 is formed, and the dielectric constant of the second dielectric layer 206 is smaller than that of the first dielectric layer 205 .

Specifically, the second dielectric layer 206 is formed on the first dielectric layer 205 by physical vapor deposition, chemical vapor deposition or atomic layer deposition. The second dielectric layer 206 is used to form second sidewalls in subsequent processes. The material of the second dielectric layer 206 has a relatively low dielectric constant, for example, the material of the second dielectric layer is one or more of SiCN, SiCON, SiBCN and SiBOCN. Since the second dielectric layer 206 has a lower dielectric constant, the parasitic capacitance between the gate structure 204 and the conductive plugs in the source and drain regions can be reduced after the subsequent formation of the second spacer.

In another embodiment of the present invention, after forming the second dielectric layer covering the first dielectric layer, a third dielectric layer is further formed on the second dielectric layer, and the material of the third dielectric layer is silicon nitride, and subsequently etch back the third dielectric layer to form a third sidewall. The third sidewall can be used as an etch barrier layer for via hole etching in the subsequent process of forming the plugs of the source region and the drain region, so as to reduce damage to the gate structure caused by the etching process.

Referring to FIG. 5 , the second dielectric layer 206 (refer to FIG. 4 ) is etched back to form a second spacer 207 .

Specifically, the second dielectric layer 206 is etched back using a dry etching process, and in this embodiment, the second dielectric layer 206 is etched back using a reactive ion etching process. Since reactive ion etching has good directionality, no mask is required, and after etching back the second dielectric layer 206, only the second dielectric layer 206 located on both sides of the gate structure 204 remains to form the second side The wall 207, the second dielectric layer 206 on the top of the gate structure 204 and the rest of the area are removed. On the one hand, the dielectric constant of the second spacer 207 is low, which can reduce the parasitic capacitance between the gate structure 204 and the conductive plugs in the source and drain regions; on the other hand, the spacer 207 is located at the Above the first dielectric layer 205, when the first dielectric layer 205 is subsequently etched to form the first sidewall, it can be used as an etching mask so that the formed second sidewall has a horizontal portion and a vertical portion.

Referring to FIG. 6, the first dielectric layer 205 is etched using the second sidewall 207 as a mask (refer to FIG. 5) to form a first sidewall 208. The first sidewall 208 has a horizontal portion 208a and Vertical section 208b.

Specifically, the first dielectric layer 205 is etched back using a dry etching process, and in this embodiment, the first dielectric layer 205 is etched using a reactive ion etching process. Since part of the surface of the first dielectric layer 205 is covered by the second sidewall 207, after the second sidewall 208 is formed by etching the first dielectric layer 205 using the second sidewall 207 as a mask , the first dielectric layer 205 located on both sides of the gate structure 204 forms the vertical portion 208b of the second sidewall 208, and the first dielectric layer 205 located below the second sidewall 207 forms the horizontal portion of the second sidewall 208 Section 208a.

It should be noted that the process of etching the second dielectric layer to form the second spacer and etching the first dielectric layer to form the first spacer can be completed in the same etching process, or can be divided into two steps. The etching process is completed.

After the first sidewall 208 is formed, the part of the fin 202 covered by the first sidewall 208 forms a negative cover region 209 (Gate under lap), and the doping concentration of the negative cover region 209 is the same as that of the subsequently formed fin. The channel regions (not shown) of the field effect transistors have the same doping concentration. Since lightly doped drain region implantation and halo implantation will not be performed in the subsequent process of the negative cover region 209, the doping concentration of the negative cover region 209 is relatively low, which can increase the effective channel region length of the FinFET , to alleviate the short channel effect.

In order to solve the low doping concentration of the negative cover region 209, which leads to the reduction of the driving current of the fin field effect transistor, in the prior art, it is usually necessary to use sidewalls with a high dielectric constant to increase the capacitance value of the negative cover region, but the high dielectric constant The sidewalls have the adverse effect of increasing the parasitic capacitance between the gate structure and the conductive plugs in the source and drain regions. In this embodiment, a double sidewall structure of the first sidewall 208 and the second sidewall 207 is adopted, the dielectric constant of the second sidewall 207 is smaller than the dielectric constant of the first sidewall 208, and The first side wall 208 has a horizontal portion 208a and a vertical portion 208b. The first sidewall 208 and the second sidewall 207 of this embodiment can be realized by one etching process, and the process is simple; The parasitic capacitance between the conductive plugs of the source region and the drain region; the horizontal portion 208a of the first spacer 208 has a higher dielectric constant, which can increase the capacitance value of the negative cover region 209 and enhance the fin field effect The driving current of the transistor;

In this embodiment, the length of the negative masking region 209 ranges from 10 angstroms to 50 angstroms. Since the width of the negative cover region 209 is related to the threshold voltage of the fin field effect transistor formed subsequently, when the length of the negative cover region 209 is small, the threshold voltage of the fin field effect transistor formed subsequently is small, Often used as transistors in logic areas to reduce power consumption. The length of the negative masking area 209 is close to the sum of the thicknesses of the first dielectric layer and the second dielectric layer, so the length range of the negative masking area 209 can be controlled by depositing the first dielectric layer and the second dielectric layer The thickness is adjusted to obtain a negative mask region 209 with a smaller length.

In another embodiment, the thickness of the first dielectric layer and the second dielectric layer is relatively thick, and the length of the formed negative masking region 209 ranges from 300 angstroms to 500 angstroms. The subsequently formed fin field effect transistor has a higher threshold voltage, and is often used as a transistor in the input/input area, so that it has a higher threshold voltage and breakdown voltage.

Referring to FIG. 7 , embedded source and drain regions 210 are formed in the fins 202 on both sides of the gate structure 204 .

Specifically, the fins 202 on both sides of the gate structure 204 are etched to form a first opening (not shown), and embedded source and drain regions 210 are formed in the first opening using a selective epitaxy process. , the selective epitaxy process may be chemical vapor deposition or molecular beam epitaxy.

In this embodiment, the material of the embedded source region and drain region 210 is silicon or silicon carbide, which is used for NMOS fin field effect transistors, and the silicon or silicon carbide is doped with N-type impurities. When the material of the embedded source region and drain region 210 is silicon, the volume of the formed embedded source region and drain region is larger than the volume of the etched fin portion 202, which is conducive to the subsequent conductive insertion of the source region and drain region. The formation of the plug prevents poor contact between the metal plug and the source region and the drain region due to the too small volume of the fin portion 202 . When the material of the embedded source region and drain region 210 is silicon carbide, the formed embedded source region and drain region 210 are not only conducive to the formation of conductive plugs on the subsequent source region and drain region, but also due to the silicon carbide material The lattice constant is smaller than that of the silicon material, and tensile stress can be introduced in the channel region of the NMOS fin field effect transistor to improve electron mobility.

In another embodiment, the material of the embedded source region and drain region 210 is silicon or silicon germanium, which is used for a PMOS fin field effect transistor, and the silicon or silicon germanium is doped with P-type impurities. When the material of the embedded source region and drain region 210 is silicon, the volume of the formed embedded source region and drain region 210 is larger than the volume of the etched fin portion 202, which is conducive to conduction on the subsequent source region and drain region. The formation of the plug prevents poor contact between the conductive plug and the source region and the drain region due to the too small volume of the fin portion 202 . When the material of the embedded source region and drain region 210 is silicon germanium, the formed embedded source region and drain region 210 can also introduce compressive stress in the channel region of the PMOS transistor to improve hole mobility.

Referring to FIG. 8 , an isolation dielectric layer 211 covering the embedded source region and drain region 210 is formed, and the upper surface of the isolation dielectric layer 211 is flush with the upper surface of the gate structure 204 .

In this embodiment, a physical vapor deposition or chemical vapor deposition process is used to form an isolation dielectric material layer covering the embedded source region and drain region 210 . Using a chemical mechanical polishing process to polish the isolation dielectric material layer, using the upper surface of the gate structure 204 as a polishing stop layer, so that the surface of the isolation dielectric material layer is flush with the upper surface of the gate structure 204, The isolation dielectric material layer constitutes the isolation dielectric layer 211 . The isolation dielectric layer 211 is used to isolate the FinFET from external devices.

In another embodiment, after forming the isolation dielectric layer, performing ion implantation on the vertical part of the first sidewall to reduce the dielectric constant of the vertical part of the first sidewall. The implanted ions in the ion implantation process are hydrogen ions, because the hydrogen ions can react with the dielectric material layer with high dielectric constant to form a dielectric material layer containing hydrogen with a lower dielectric constant. For example, when the material of the first side wall is HfO ₂ , hydrogen ions react with HfO x H y to generate Hf or HfO _x H _y , and the dielectric constant of Hf and HfO _x H _y is smaller than that of HfO ₂ . Since the dielectric constant of the vertical portion of the first spacer is reduced, the parasitic capacitance between the gate structure and the conductive plugs formed subsequently on the source region and the drain region can be further reduced.

Referring to FIG. 9 , the gate structure 204 (refer to FIG. 8 ) is removed to form a second opening (not shown), and a high dielectric constant gate dielectric layer 212 and a metal gate 213 are formed in the second opening.

In this embodiment, the gate structure 204 is a dummy gate, and after removing the dummy gate, a second opening is formed. A high dielectric constant gate dielectric material layer is formed in the second opening by chemical vapor deposition process or atomic layer deposition process, and the material of the high dielectric constant gate dielectric material layer is HfO ₂ , Al ₂ O ₃ , ZrO _2. One or more of HfSiO, HfSiON, HfTaO and HfZrO. A metal gate material layer is formed on the high dielectric constant gate dielectric material layer, and the material of the metal gate material layer is W, Al, Cu, Ti, Ta, TaN, NiSi, CoSi, TiN, TiAl and One or several kinds of TaSiN. The metal gate material layer and the high dielectric constant gate dielectric material layer are polished by a chemical mechanical polishing process, and the isolation dielectric layer 211 is used as a polishing stop layer to form a high dielectric constant gate dielectric layer 212 and a metal gate 213 .

In another embodiment, the gate structure includes a gate dielectric layer and a gate electrode layer, which are formed using a gate-first process (Gatefirst), without removing the gate structure.

Subsequently, a via hole exposing the surface of the embedded source region and the drain region is formed in the isolation dielectric layer, and a conductive plug of the source region and the drain region is formed in the through hole. Due to the low dielectric constant of the second spacer, the parasitic capacitance between the gate structure and the conductive plugs of the source region and the drain region is reduced.

Correspondingly, please refer to FIG. 9 , this embodiment also provides a fin field effect transistor, including: a semiconductor substrate 200, the surface of the semiconductor substrate has a raised fin 202; The gate structure, the gate structure covers part of the top and sidewall of the fin portion 202, the gate structure includes a gate dielectric layer 212 and a gate electrode layer 213 on the gate dielectric layer 212; The first sidewall 208 on both sides of the gate structure, the first sidewall has a horizontal portion 208a and a vertical portion 208b; the second sidewall 207 on both sides of the first sidewall 208, the second sidewall The wall position 207 is on the horizontal portion 208a of the first side wall, the dielectric constant of the second side wall 207 is smaller than the dielectric constant of the first side wall 208; Negative shadow area 209 within part of fin 202 .

In this embodiment, the doping concentration of the negative covering region 209 is the same as that of the channel region (not shown) of the FinFET.

In this embodiment, the material of the first side wall 208 is one or more of HfO ₂ , Al ₂ O ₃ , ZrO ₂ , HfSiO, HfSiON, HfTaO and HfZrO, and the material of the second side wall 207 One or more of SiCN, SiCON, SiBCN and SiBOCN.

In another embodiment, the FinFET further includes third sidewalls located on both sides of the second sidewalls, and the material of the third sidewalls is silicon nitride.

Correspondingly, the fin field effect transistor of this embodiment is formed by using the method for forming the fin field effect transistor described above, so the fin field effect transistor of this embodiment also has the ability to reduce the gap between the gate structure and the source region and the drain region. Advantages of parasitic capacitance between conductive plugs.

Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention, and any person skilled in the art can utilize the methods and techniques disclosed above to analyze the technical aspects of the present invention without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments according to the technical essence of the present invention, which do not depart from the content of the technical solution of the present invention, all belong to the protection of the technical solution of the present invention. scope.

Claims (18)

1. A method for forming a Fin Field Effect Transistor, comprising: providing a semiconductor substrate, the surface of the semiconductor substrate has a raised fin, a gate structure on the fin, the gate structure covers part of the top and sidewall of the fin; forming a first dielectric layer covering the gate structure; forming a second dielectric layer covering the first dielectric layer, the dielectric constant of the second dielectric layer is lower than the dielectric constant of the first dielectric layer; Etching back the second dielectric layer to form a second spacer; Etching the first dielectric layer by using the second sidewall as a mask to form a first sidewall, the first sidewall has a horizontal part and a vertical part, and the part of the fin covered by the first sidewall constitutes The negative cover region, the doping concentration of the negative cover region is the same as the doping concentration of the channel region of the fin field effect transistor. 2 . The method for forming a fin field effect transistor according to claim 1 , wherein the length of the negative covering region ranges from 300 angstroms to 500 angstroms. 3 . The method for forming a fin field effect transistor according to claim 1 , wherein the length of the negative masking region ranges from 10 angstroms to 50 angstroms. 4 . 4. The method for forming a fin field effect transistor according to claim 1, further comprising: forming an isolation dielectric layer covering the fin, the upper surface of the isolation dielectric layer is connected to the gate structure flush with the top surface. 5. The method for forming a fin field effect transistor according to claim 4, further comprising: performing ion implantation on the vertical portion of the first sidewall to reduce the vertical portion of the first sidewall the dielectric constant. 6 . The method for forming a fin field effect transistor according to claim 5 , wherein the implanted ions in the ion implantation process are hydrogen ions. 7. The method for forming a fin field effect transistor according to claim 1, further comprising: forming a third dielectric layer on the second dielectric layer, and after etching back the third dielectric layer, Form the third side wall. 8. The method for forming a fin field effect transistor according to claim 7, wherein the material of the third dielectric layer is silicon nitride. 9 . The method for forming a fin field effect transistor according to claim 1 , further comprising forming embedded source and drain regions in the fins on both sides of the gate structure. 10 . The method for forming a fin field effect transistor according to claim 9 , wherein the embedded source region and drain region are made of silicon, silicon germanium or silicon carbide. 11 . 11. The method for forming a fin field effect transistor according to claim 9, wherein the embedded source region and drain region are doped with N-type or P-type impurities. 12. The method for forming a fin field effect transistor according to claim 1, wherein the material of the first dielectric layer is HfO ₂ , Al ₂ O ₃ , ZrO ₂ , HfSiO, HfSiON, HfTaO and HfZrO. one or more of. 13. The method for forming a fin field effect transistor according to claim 1, wherein the material of the second dielectric layer is one or more of SiCN, SiCON, SiBCN and SiBOCN. 14. The method for forming a FinFET according to claim 1, wherein the gate structure is a dummy gate. 15. The method for forming a fin field effect transistor according to claim 14, further comprising: removing the dummy gate, forming a second opening, and forming a high dielectric constant electrode in the second opening. gate dielectric layer and metal gate. 16. A fin field effect transistor, characterized in that it comprises: a semiconductor substrate having raised fins on its surface; a gate structure on the fin, the gate structure covering part of the top and sidewalls of the fin; a first sidewall located on both sides of the gate structure, the first sidewall has a horizontal portion and a vertical portion; a second side wall located on both sides of the first side wall, the second side wall is located on a horizontal portion of the first side wall, and the dielectric constant of the second side wall is smaller than that of the first side wall The dielectric constant; The negative cover region located in the part of the fin under the first sidewall, the doping concentration of the negative cover region is the same as the doping concentration of the channel region of the fin field effect transistor. 17. The fin field effect transistor according to claim 16, wherein the material of the first sidewall is one of HfO ₂ , Al ₂ O ₃ , ZrO ₂ , HfSiO, HfSiON, HfTaO and HfZrO or more than one, the material of the second side wall is one or more of SiCN, SiCON, SiBCN and SiBOCN. 18 . The FinFET according to claim 16 , further comprising third sidewalls located on both sides of the second sidewalls, the material of the third sidewalls is silicon nitride.