CN103928487B - Back-illuminated image sensor and method for forming the same - Google Patents

Abstract

A kind of back side illumination image sensor and forming method thereof.Wherein, described back side illumination image sensor includes: Semiconductor substrate, and described Semiconductor substrate includes first area and at least one second area；Photo-electric conversion element, is positioned in described first area；Floating diffusion region, part is positioned in a described second area, and part is positioned in described first area, and the upper surface of described second area is higher than the upper surface of described first area；Transfering transistor, electrically connects with described photo-electric conversion element and described floating diffusion region respectively including the source electrode being positioned in described Semiconductor substrate and drain electrode, described source electrode and described drain electrode；Transistor is followed in source, and including the grid being positioned in described Semiconductor substrate, described grid electrically connects with described floating diffusion region；Reset transistor, including the drain electrode being positioned in described Semiconductor substrate, described drain electrode electrically connects with described floating diffusion region.The performance of described back side illumination image sensor improves, and cost reduces.

Description

Back-illuminated image sensor and method for forming the same

technical field

The invention relates to the field of image sensors, in particular to a back-illuminated image sensor and a forming method thereof.

Background technique

An image sensor is a semiconductor device that converts light signals into electrical signals. The image sensor has a photoelectric conversion element. Usually, the photoelectric conversion element is formed under the substrate surface, and the logic circuit is formed on the photoelectric conversion element. After passing through the logic circuit, the light Before reaching the photoelectric conversion element, the light passes through the multi-layer structure, resulting in light loss or light crosstalk to adjacent image sensor unit chips, affecting the photoresponse characteristics of the photoelectric conversion elements of each image sensor unit chip.

In order to overcome the above limitations, back side illumination (BSI) image sensors have been proposed. In the back-illuminated image sensor, light is directly irradiated to the photoelectric conversion element from the back surface of the substrate without passing through the logic circuit, so that the photoresponse characteristics of the photoelectric conversion element are improved in the back-illuminated image sensor.

Image sensors can be further divided into complementary metal oxide (CMOS) image sensors and charge-coupled device (CCD) image sensors. The advantage of the CCD image sensor is that it has high image sensitivity and low noise, but it is difficult to integrate the CCD image sensor with other devices, and the power consumption of the CCD image sensor is relatively high. In contrast, CMOS image sensors have the advantages of simple process, easy integration with other devices, small size, light weight, low power consumption, and low cost. Therefore, with the development of technology, CMOS image sensors are increasingly used in various electronic products instead of CCD image sensors. At present, CMOS image sensors have been widely used in still digital cameras, camera phones, digital video cameras, medical imaging devices (such as gastroscopes), and automotive imaging devices.

The core component of an image sensor is the pixel unit (Pixel), which directly affects factors such as the size of the image sensor, dark current level, noise level, imaging transparency, image color saturation, and image defects.

A pair of contradictory factors have been driving image sensors forward all the time:

1. Economic factors: The more image sensor chips that can be produced on a wafer, the lower the cost of the image sensor chip, and the pixel unit occupies most of the area of the entire image sensor chip. Therefore, in order to save costs, the pixel unit is required The size is made smaller, that is, for economical reasons, the characteristic size of the pixel unit in the image sensor is required to be reduced.

2. Image quality factors: In order to ensure image quality, especially in order to ensure light sensitivity, color saturation and imaging transparency and other indicators, it is necessary to have enough light incident on the photoelectric conversion element of the pixel unit (usually photodiode) , and a larger pixel unit can have a larger photosensitive area to receive light. Therefore, a larger pixel unit can provide better image quality in principle; Switching devices, such as reset transistors, transfer transistors, and amplifying devices (such as source follower transistors), these devices also determine dark current, noise, and image defects. From the perspective of image quality, in principle, larger devices have better electrical performance. It is helpful to form an image with better quality; for this reason, it is known that the size of the pixel unit in the image sensor is required to be increased in consideration of the image quality.

It can be clearly seen that how to coordinate the above contradictions to obtain the optimal choice is a problem that the image sensor industry has been facing.

In existing image sensors, there is usually a pixel array (array) composed of one pixel unit. From the perspective of the layout, multiple pixel units can be put together to form a complete pixel array, and the shape of the pixel unit can be changed according to the needs. are rectangles, squares, polygons (triangles, pentagons, hexagons) and so on.

In the existing image sensor, the structure of the pixel unit can be divided into a photoelectric conversion element plus 3 transistor structure, a photoelectric conversion element plus 4 transistor structure or a photoelectric conversion element plus 5 transistor structure. The structure of the photoelectric conversion element plus 3 transistors is specifically that the photoelectric conversion element is directly connected to the floating diffusion area, and the photogenerated electrons generated in the photoelectric conversion element are stored in the floating diffusion area. Under control, the photogenerated electrons are converted and output by a source follower (SF).

Please refer to FIG. 1 , which shows a schematic cross-sectional view of a photoelectric conversion element plus 4 transistors. The photoelectric conversion element 115 is usually a photodiode (PD), the photoelectric conversion element 115 is connected to the floating diffusion region 113 (FD) through the transfer transistor 114, and the lead L3 (the lead generally includes a plug and an interconnection wire, etc.) is connected to the transfer transistor. 114 grid. The source follower transistor 112 is connected to the floating diffusion region 113 , and the source follower transistor 112 is used to amplify the potential signal formed in the floating diffusion region 113 , and the lead L2 is connected to the gate of the source follower (amplification) transistor 112 . One end of the reset transistor 111 is connected to the power supply VDD, and the other end is connected to the floating diffusion region 113 to reset the potential of the floating diffusion region 113 . The lead L1 is connected to the gate of the reset transistor 111 . It can be seen that the photoelectric conversion element plus 4 transistor structure is based on the photoelectric conversion element plus 3 transistor structure, and the transfer transistor 114 is added between the photoelectric conversion element 115 and the floating diffusion region 113 . The transfer transistor 114 can effectively suppress noise, and the photoelectric conversion element plus 4 transistor structure can obtain better image quality, and has gradually become the leading structure in the industry. In addition, multiple photoelectric conversion elements can share a set of 4-transistor devices to save chip area, and this structure is also considered as a 4-transistor structure.

However, in the existing image sensors, the pixel unit has inherent defects that are difficult to overcome:

1. In the existing pixel unit, the four transistor devices are all planar structures. In other words, if the chip area is to be further reduced, the components of these devices (such as transfer transistors, reset transistors, and source follower transistors, etc.) must be reduced. size. However, if the size of these devices is reduced, the performance of these devices will be degraded at the same time, specifically manifested in the decrease of the drive current of the device, the increase of fluctuations in electrical parameters, and the decrease in amplification efficiency. These issues have a significant impact on image quality. Therefore, although the circuits around the pixel array can further reduce the line width and size according to Moore's law, the transistor devices in the pixel unit can only be reduced very slowly. However, the area of the entire image sensor chip is mainly determined by the pixel array. Therefore, the structure of the existing pixel unit limits the further reduction of the chip area, making the cost of the image sensor high.

2. In the existing pixel unit, the four transistor devices are all planar structures. For a pixel unit of a certain size, after containing four transistor devices, the size can be further reduced. The ratio is limited. As for the performance of the pixel unit, the smaller the proportion of the photoelectric conversion element, the less light collected per unit area, the less transparent the image, the poorer the layering of the image, and the drier the color. In short, the planar structure of the transistor device limits Further improvements in image quality.

3. In the existing pixel unit, the image quality under dark field is very critical, and its key indicators are dark current, noise, white point and dark point, etc. These dark currents, noises, white spots and dark spots originate from transistor device frequency noise and thermal noise, as well as surface recombination currents of photoelectric conversion elements. In the traditional existing process, even though great effort is spent on these aspects, the ideal effect cannot be achieved because the process limit has been reached. Therefore, new image sensors and corresponding processes are urgently needed to further reduce dark current and noise. , white point and dark point etc. indicator levels.

4. In the existing pixel unit, since each transistor has a planar structure, the parasitic capacitance between the transfer transistor, the reset transistor and the source follower transistor cannot be further reduced as the feature size is reduced, and the parasitic capacitance basically plays a negative role. , such as reducing signal transmission speed, increasing low-frequency 1/f noise, reducing dynamic range, etc., these are unacceptable for image sensors. Therefore, it is necessary to further reduce parasitic capacitance and reduce low-frequency 1/f noise in order to increase signal transmission speed and increase dynamic range, which is a very difficult and expensive task for traditional image sensors and their formation processes.

5. In the existing pixel unit, since the photoelectric conversion element is made on the surface of the wafer, even if the back-illuminated lighting condition is used, the light is attenuated by the thicker semiconductor layer, which reduces the light entering the photoelectric conversion element. If the luminous flux is reduced, the corresponding photogenerated electrons will be reduced, and the image quality of the image sensor will decrease, the layering will be poor, and the color will not be bright.

For more information about the existing image sensor and its forming method, please refer to the Chinese patent application document with the publication number CN103500750A published on January 8, 2014.

To sum up, there is an urgent need for a back-illuminated image sensor and its forming method to overcome the defects of existing image sensors.

Contents of the invention

The problem to be solved by the present invention is to provide a back-illuminated image sensor and its forming method, so as to improve the performance of the back-illuminated image sensor, improve the image quality of the back-illuminated image sensor, and reduce the cost of the back-illuminated image sensor.

In order to solve the above problems, the present invention provides a back-illuminated image sensor, including a pixel array, the pixel array includes a plurality of pixel units arranged in an array, and the pixel units include:

a semiconductor substrate comprising a first region and at least one second region;

a photoelectric conversion element, located in the first region, for receiving light to generate signal charges;

a floating diffusion region located partly in one of the second regions and partly in the first region, the upper surface of the second region being higher than the upper surface of the first region, the floating diffusion region for collecting the signal charge to generate a signal potential;

a transfer transistor, including a source and a drain located in the semiconductor substrate, the source and the drain are respectively electrically connected to the photoelectric conversion element and the floating diffusion region, and the transfer transistor is used for controlling the transfer of the signal charge to the floating diffusion;

a source follower transistor, including a gate on the semiconductor substrate, the gate is electrically connected to the floating diffusion region, and the source follower transistor is used to amplify the signal potential;

A reset transistor includes a drain located in the semiconductor substrate, the drain is electrically connected to the floating diffusion area, and the reset transistor is used to reset the potential of the floating diffusion area.

Optionally, the upper surface of the floating diffusion region is higher than the upper surface of the semiconductor substrate corresponding to the photoelectric conversion element by more than 30 nm.

Optionally, the upper surface of the channel region of the source follower transistor is higher than the upper surface of the semiconductor substrate corresponding to the photoelectric conversion element by more than 30 nm.

Optionally, the second region is a convex structure, including a first part and a second part located on the first part, the first part has two sides, and the second part has a top surface and two sides .

Optionally, the channel region of the source-following transistor is located in the second part of another second region, and the gate of the source-following transistor covers the top surface and two sides of the second part. At least one side.

Optionally, the channel region of the source follower transistor has a channel doped region and a non-channel doped region, and the non-channel doped region is located between the channel doped region and the source follower transistor. between the gates.

Optionally, the channel region of the reset transistor is located in the second part of another second region, and the gate of the reset transistor covers at least one of the top surface and two sides of the second part. one side.

Optionally, the semiconductor substrate has a plurality of the second regions, the semiconductor substrate also has an isolation structure between adjacent second regions, and the photoelectric conversion element is located in the isolation structure .

Optionally, the gate of the transfer transistor is located on the upper surface of the photoelectric conversion element and the isolation structure at the same time.

Optionally, the pixel unit further includes: a side wall, the side wall covers two sides of the first part.

Optionally, the photoelectric conversion element is a photodiode.

In order to solve the above problems, the present invention also provides a method for forming a back-illuminated image sensor, including:

providing a semiconductor substrate comprising a first region and at least one second region;

forming a photoelectric conversion element in the first region;

forming a source follower transistor, a reset transistor, and a transfer transistor on the semiconductor substrate, and the source of the transfer transistor is electrically connected to the photoelectric conversion element;

A floating diffusion region is formed in the semiconductor substrate, the floating diffusion region is partly located in one of the second regions and partly located in the first region, and the upper surface of the second region is higher than the first region. an upper surface of an area; and the floating diffusion area is electrically connected to the drain of the reset transistor, the drain of the transfer transistor and the gate of the source follower transistor.

Optionally, the upper surface of the floating diffusion region is higher than the upper surface of the semiconductor substrate corresponding to the photoelectric conversion element by more than 30 nm.

Optionally, the upper surface of the channel region of the source follower transistor is higher than the upper surface of the semiconductor substrate corresponding to the photoelectric conversion element by more than 30 nm.

Optionally, the second region is a convex structure, including a first part and a second part located on the first part, the first part has two sides, and the second part has a top surface and two sides .

Optionally, the channel region of the source-follower transistor is formed in the second part of another second region, and the gate of the source-follower transistor covers the top surface and two sides of the second part at least one side of the .

Optionally, the channel region of the reset transistor is formed in the second part of another second region, and the gate of the reset transistor covers at least the top surface and two sides of the second part. one side.

Optionally, the process of forming the second region includes:

A plurality of discrete shallow trenches are formed on the surface of the semiconductor substrate, and the remaining portion of the semiconductor substrate between adjacent shallow trenches is the second region.

Optionally, forming a source follower transistor, a reset transistor and a transfer transistor in the semiconductor substrate includes:

Doping the semiconductor substrate until forming a well region in the semiconductor substrate, the well region including the second region and part of the first region;

forming a gate dielectric layer of a source follower transistor, a reset transistor and a transfer transistor on the well region;

forming the gates of the source follower transistor, the reset transistor and the transfer transistor on the gate dielectric layer;

Part of the well region is doped until the source and drain of the source follower transistor and the reset transistor are formed.

Optionally, after forming the shallow trench and before forming the gate dielectric layer, the forming method further includes:

filling the shallow trench with a first dielectric layer;

Etching back the first dielectric layer until the remaining first dielectric layer forms a side wall covering the side of the first portion.

Optionally, forming the gate includes:

forming a gate layer on the surface of the gate dielectric layer;

Covering the gate layer with photoresist;

patterning the photoresist layer to form an opening, the opening exposing the gate layer located in the non-gate region;

Using the photoresist layer as a mask, etching removes the gate layer exposed by the opening, leaving the gate layer as the gate.

Optionally, before forming the photoelectric conversion element, the method further includes:

forming an isolation structure in the first region;

When forming the photoelectric conversion element, the photoelectric conversion element is formed in the isolation structure.

Optionally, when forming the gate of the transfer transistor, the gate of the transfer transistor covers the photoelectric conversion element and the upper surface of the isolation structure at the same time.

Optionally, forming the channel region of the source follower transistor includes:

Channel doping is performed on the second part to form a channel doping region, and the region of the second part that is not subjected to channel doping is a non-channel doping region, and the non-channel doping region is located at Between the channel doping region and the gate.

Optionally, the second region is an epitaxially grown single crystal semiconductor layer, and the process of forming the second region includes:

forming a second dielectric layer on the surface of the semiconductor substrate;

patterning the second dielectric layer to form a groove exposing the semiconductor substrate;

The single crystal semiconductor layer is epitaxially grown on the surface of the semiconductor substrate exposed by the groove.

Optionally, the forming method also includes:

Etching back the second dielectric layer until the remaining second dielectric layer forms a side wall covering the side of the first portion.

Optionally, the process of forming the gate dielectric layer and the gate includes:

forming a dummy gate dielectric layer on the surface of the well region;

forming a third dielectric layer on the surface of the dummy gate dielectric layer;

patterning the third dielectric layer to form a window, the window exposing the dummy gate dielectric layer located in the gate region;

removing the dummy gate dielectric layer exposed by the window;

After removing the dummy gate dielectric layer exposed by the window, forming the gate dielectric layer at the bottom of the window;

The gate is formed on the gate dielectric layer.

Optionally, the material of the gate dielectric layer is a high dielectric material, and the material of the gate includes polysilicon, metal or a combination of both.

Optionally, the high dielectric material refers to a material with a dielectric constant greater than 4.

Optionally, the photoelectric conversion element is a photodiode.

Compared with the prior art, the technical solution of the present invention has the following advantages:

In the technical solution of the present invention, a semiconductor substrate having a first region and at least one second region is provided, the photoelectric conversion element is located in the first region, the floating diffusion region is partially located in one of the second regions, and the floating diffusion region partly located in the first region, the upper surface of the second region is higher than the upper surface of the first region, therefore, the upper surface of the floating diffusion region is higher than the upper surface of the semiconductor substrate corresponding to the photoelectric conversion element . And the upper surface of the channel region region of the transfer transistor is located in the same surface as the upper surface of the photoelectric conversion element, therefore, the upper surface of the floating diffusion region is higher than the upper surface of the channel region region of the transfer transistor, that is, at this time The upper surface of the floating diffusion region is not in the same plane as the upper surface of the channel region region of the transfer transistor. Once the upper surface of the floating diffusion region and the upper surface of the channel region of the transfer transistor are not on the same plane, the scattered capacitance between the floating diffusion region and the transfer transistor can be reduced, thereby accelerating the transfer and transmission of photocharges. The conversion efficiency is improved.

Further, the upper surface of the floating diffusion region is set to be higher than the upper surface of the semiconductor substrate corresponding to the photoelectric conversion element by more than 30 nm. The upper surface of the channel region region of the transfer transistor is flush with the upper surface of the semiconductor substrate corresponding to the photoelectric conversion element, and when the upper surface of the floating diffusion region is higher than the upper surface of the photoelectric conversion element by more than 30nm, the The height difference between the surface and the upper surface of the channel region of the transfer transistor is also more than 30nm. At this time, the bulk capacitance between the floating diffusion region and the transfer transistor is greatly reduced, and the conversion efficiency of photoelectric charges is significantly improved.

Further, the upper surface of the channel region region of the source follower transistor is not on the same plane as the upper surface of the semiconductor substrate corresponding to the photoelectric conversion element. At this time, there is no horizontal isolation problem between the channel region of the source follower transistor and the photoelectric conversion element. Therefore, no isolation structure needs to be provided between the source follower transistor and the photoelectric conversion element. Compared with the traditional planar structure, the isolation structure between the source follower transistor and the photoelectric conversion element can be reduced, so that under the same pixel unit size condition, the area of the pixel unit occupied by the non-photoelectric conversion element can be reduced, The filling rate of the photoelectric conversion element is increased, and the utilization rate of the area of the pixel unit is improved.

Further, the upper surface of the channel region region of the source follower transistor is set to be higher than the upper surface of the semiconductor substrate corresponding to the photoelectric conversion element by more than 30nm, when the upper surface of the channel region region of the source follower transistor is higher than the corresponding photoelectric conversion element When the upper surface of the semiconductor substrate is more than 30nm, the isolation effect between the source follower transistor and the photoelectric conversion element is more ideal.

Further, the source-following transistor is set as a buried channel device, that is, the channel region of the source-following transistor has a channel doping region and a non-channel doping region, and the non-channel doping region is located at the channel doping region. region and the gate of the source follower transistor. The low-frequency 1/f noise of the source follower transistor is one of the key factors affecting the performance of the pixel unit. The lower the low-frequency 1/f noise, the better the performance of the pixel unit and the higher the image quality. When the source-following transistor is a buried channel device, the current mainly flows in the channel region far away from the surface of the channel region, so that when the electrons flow, they flow concentratedly inside the channel region (that is, the buried channel) to avoid electrons near the channel region. The region flow on the surface of the channel region area, thereby reducing the scattering at the interface when the current flows on the surface of the channel region region, thereby reducing the low-frequency 1/f noise and improving the performance of the back-illuminated image sensor.

Further, the source-follower transistor has a gate that surrounds three surfaces (including the top surface and two side surfaces) of the channel region, so the physical width of the channel region of the source-follower transistor can be greatly increased. Compared with the existing planar source-follower transistor, the physical width of the channel region of the source-follower transistor is significantly increased, so the current passing through the channel region can be significantly increased. On the other hand, when the same passing current is to be achieved, only a small device size is required to adopt the follower transistor provided by the present invention, that is, the source follower transistor can maintain the physical length and physical width of the effective channel region of the transistor. Next, the lateral size of the transistor is reduced, and the filling rate of the photoelectric conversion element in the pixel unit is increased, so as to achieve the purpose of reducing the chip area.

Description of drawings

FIG. 1 is a schematic cross-sectional structure diagram of a pixel unit in an existing image sensor;

2 is a schematic top view of a pixel unit in a back-illuminated image sensor provided by an embodiment of the present invention;

3 is a schematic cross-sectional structure diagram of a pixel unit in a back-illuminated image sensor provided by an embodiment of the present invention;

FIG. 4 is a schematic diagram of a three-dimensional structure of a source follower transistor in the pixel unit shown in FIG. 3;

5 is a schematic cross-sectional structure diagram of a pixel unit in a back-illuminated image sensor provided by another embodiment of the present invention;

6 to 15 are structural schematic diagrams corresponding to each step in the method for forming a back-illuminated image sensor provided by an embodiment of the present invention;

16 to 19 are structural schematic diagrams corresponding to each step in the method for forming a back-illuminated image sensor provided by an embodiment of the present invention.

detailed description

In existing image sensors, transistors (such as source follower transistors, transfer transistors, and reset transistors, etc.) are usually planar structures. Therefore, the corresponding pixel units have many defects. For example, it is difficult to further reduce the chip area of image sensors. The cost remains high, the image quality formed by the image sensor is difficult to further improve, the noise level of the image sensor is difficult to reduce, and the area occupancy rate of the photoelectric conversion element in the pixel unit is difficult to increase.

For this reason, the present invention proposes a new three-dimensional back-illuminated image sensor, which has a new pixel unit structure, and the pixel unit includes: a semiconductor substrate, and the semiconductor substrate includes a first regions and at least one second region; a photoelectric conversion element located in the first region for receiving light to generate signal charges; a floating diffusion region partially located in one of the second regions and partially located in the first region In one region, the upper surface of the second region is higher than the upper surface of the first region, that is, the upper surface of the floating diffusion region is higher than the upper surface of the photoelectric conversion element.

By setting the upper surface of the floating diffusion region higher than the upper surface of the photoelectric conversion element, in the pixel unit of the present invention, the adverse effect between the floating diffusion region and the photoelectric conversion element is reduced, so the performance of the pixel unit is improved , so that the image quality generated by the image sensor can be improved, and the performance of the image sensor chip can be improved at the same time, and the cost of the image sensor chip can be reduced.

In order to make the above objects, features and advantages of the present invention more comprehensible, specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.

An embodiment of the present invention provides a back-illuminated image sensor, the back-illuminated image sensor includes a pixel array, and the pixel array includes a plurality of pixel units arranged in an array.

Please refer to FIG. 2 , which is a schematic top view of a pixel unit in a back-illuminated image sensor provided by an embodiment of the present invention.

Four pixel units are shown in FIG. 2 as a representative, and FIG. 2 shows a schematic layout (top view) of a pixel unit having a photoelectric conversion element plus 4 transistor structure. Wherein, the layout shape of each pixel unit is square, and 4 pixel units are arranged and connected together in a 2×2 array.

Please continue to refer to FIG. 2, reset transistor 230t, source follower transistor 270t, photodiode region 260 (photoelectric conversion element), transfer transistor 250t and floating diffusion region 240 can be seen in the top view plane of each pixel unit. 4 pixel units The floating diffusion region 240 is gathered at the same vertex, the transfer transistor 250t and the photodiode region 260 are sequentially outward from the floating diffusion region 240, and the source follower transistor 270t is formed at a diagonal position far away from the floating diffusion region 240, reset The transistor 230t is formed on a different vertex on the same side as the source follower transistor 270t. Such a layout structure is compact, which can make reasonable use of the area of the pixel unit and reduce the total area of the image sensor chip.

It should be noted that, in other embodiments of the present invention, the layout shape of the pixel unit may also be other shapes, such as triangle, rectangle or regular hexagon, etc., which is not limited in the present invention. Similarly, in other embodiments of the present invention, the number of transistors in each pixel unit may be 3 or 5, etc., which is not limited in the present invention. Likewise, in other embodiments of the present invention, each transistor device may be arranged in various other forms in each pixel unit, which is not limited in the present invention.

Please refer to FIG. 2 and FIG. 3 in conjunction. FIG. 3 shows a schematic cross-sectional view of the pixel unit shown in FIG. Specifically, in FIG. 3 from FIG. 2 , the fold line AA' first cuts along the source follower transistor 270t of one of the pixel units to the photodiode region 260, then cuts along the photodiode region 260 to the transfer transistor 250t, and then cuts along the transfer transistor 250t. cutting to the floating diffusion region 240, then passing through this pixel unit to continue cutting to the floating diffusion region 240 of the second pixel unit, and then cutting along the floating diffusion region 240 of the second pixel unit to the transfer transistor of this pixel unit 250t, then cut along the transfer transistor 250t of the second pixel unit to the photodiode region 260 of the second pixel unit, and finally cut to the reset transistor 230t of the second pixel unit. And in this embodiment, the part of the second pixel unit that is repeatedly cut (ie, the floating diffusion region 240, the transfer transistor 250t and the photodiode region 260) is represented by a dotted line segment, as indicated by the folded line AA' in FIG. 2 , and in the schematic cross-sectional structure diagram corresponding to FIG. 3 , the part cut by the dotted line segment is not shown.

Please refer to FIG. 2 and FIG. 3 in conjunction with the pixel units included in the back-illuminated image sensor provided in this embodiment.

The pixel unit includes:

A semiconductor substrate 200. The semiconductor substrate 200 includes a first region (not marked) and three second regions (not marked), and the second regions are in a raised structure. In FIG. 3 , the first area and the second area are separated by a dotted line to show the difference. The semiconductor substrate 200 has a well region 210 on it. The region where the well region 210 is located includes all three of the second regions in the raised structure, and also includes part of the first region.

a photoelectric conversion element located in the first region. In this embodiment, the photoelectric conversion element is a photodiode, and a photodiode area 260 is shown in FIG. 3 , that is, the photodiode area 260 represents the area where the photodiode is located. Photodiodes are used for photoelectric conversion to generate signal charges.

The floating diffusion region 240 is located on the well region 210 , and the floating diffusion region 240 is partially located in one of the second regions and is partially located in the first region, as shown in FIG. 3 . The floating diffusion region 240 is used to collect the signal charge to generate a signal potential.

The transfer transistor 250t is located between the floating diffusion region 240 and the photodiode region 260 . The transfer transistor 250t includes a source (not shown) and a drain (not shown) in the semiconductor substrate 200 . The source is electrically connected to the photodiode region 260 , and the drain is electrically connected to the floating diffusion region 240 . The transfer transistor 250t is used to control the transfer of the signal charge from the photodiode region 260 to the floating diffusion region 240 . In other words, it can be said that the photodiode region 260 is the source of the transfer transistor 250t, and the floating diffusion region 240 is the drain of the transfer transistor 250t.

reset transistor 230t, the reset transistor 230t is located on the well region 210, and the channel region of the reset transistor 230t is located in another said second region (in FIG. 3, the channel region of the reset transistor 230t is located in the floating diffusion region 240 in the second area on the left). The reset transistor 230t includes a drain located in the semiconductor substrate 200, the drain is electrically connected to the floating diffusion region 240, the source of the reset transistor 230t is generally connected to a reset voltage, and the reset transistor 230t is used to reset the floating diffusion region 240 potential.

The source follower transistor 270t, the source follower transistor 270t is located on the well region 210, and the channel region region of the source follower transistor 270t is located in another said second region (in FIG. 3, the channel region region of the source follower transistor 270t is located in the floating placed in the second region to the right of the diffusion region 240). The source follower transistor 270t includes a gate 271 located on the semiconductor substrate 200, the gate 271 is electrically connected to the floating diffusion region 240, and the source follower transistor 270t is used to amplify the signal potential, that is, the drain of the source follower transistor 270t outputs a An electrical signal related to the potential of the floating diffusion region 240 .

The dielectric layer 220, the dielectric layer 220 fills and surrounds the surface of the gate region of the above-mentioned transistors, the dielectric layer 220 can be a single-layer structure or a multi-layer structure, and the dielectric layer 220 is covered by the plug 233, the plug 242, the plug 252 And plug 273 runs through. The plug 233 is connected to the gate 231 of the reset transistor, the plug 242 is connected to the floating diffusion region 240 , the plug 252 is connected to the gate 251 of the transfer transistor, and the plug 273 is connected to the gate 271 of the source follower transistor.

In this embodiment, the semiconductor substrate 200 may be single crystal silicon or silicon germanium (wafer doped substrate), or silicon on insulator (Silicon on insulator, SOI). In other embodiments of the present invention, a P-type epitaxial layer or an N-type epitaxial layer can also be formed on the semiconductor substrate 200, and the semiconductor substrate 200 and the P-type epitaxial layer or N-type epitaxial layer are used together as the semiconductor for forming the pixel unit. base.

In this embodiment, the well region 210 may be a P-type well, which may be formed by doping with boron or a boron compound. Correspondingly, the channel region of each transistor is a P-type doped region, and the source region and drain region of the transistor correspond to an N-type heavily doped region. It should be noted that, in other embodiments of the present invention, the well region can also be an N-type well, and different positions of the well region can be doped with different types, and the specific doping type can be determined according to the type of transistor to be formed. .

The reset transistor 230t, the floating diffusion region 240, the transfer transistor 250t and the source follower transistor 270t in the pixel unit will be further described below in order from left to right in FIG. 3 .

Please continue to refer to FIG. 3 , the reset transistor 230t is located in the second region to the left of the floating diffusion region 240 . The second area can be specifically divided into a first part 2301 and a second part 2302 . The channel region of the reset transistor 230t is located in the area where the second portion 2302 is located. The second portion 2302 has a top surface and two sides (faces not labeled). The top surface and two sides of the second part 2302 are covered by a gate dielectric layer (not shown), and the gate dielectric layer is covered by the gate 231 of the reset transistor 230t, that is, the gate 231 surrounds the top surface of the channel region and two sides.

Since the gate 231 of the reset transistor 230t covers the top surface and two sides of the second part 2302, that is, the gate 231 of the reset transistor 230t covers the top surface and two sides of the channel region of the reset transistor 230t, therefore, at this time, reset The transistor 230t has a gate-surrounding structure on three sides. This surrounding gate structure can increase the physical width of the channel region of the reset transistor 230t, thus improving the performance of the reset transistor 230t, such as improving the turn-off capability of the gate 231, and reducing the feature size of the reset transistor 230t.

It should be noted that, in other embodiments of the present invention, the gate 231 of the reset transistor 230t may only cover one side of the second part 2302, or only cover two sides of the second part 2302, or only cover the second side. The top surface and one of the side surfaces of the two parts 2302 .

Please continue to refer to FIG. 3 , the reset transistor 230 t also has sidewalls 232 located between the well region 210 and the gate 231 , and the sidewalls 232 cover two sides of the first portion 2301 . Therefore, the side wall 232 can isolate the gate 231 from the well region 210, so that the performance of the reset transistor 230t is improved.

Please continue to refer to FIG. 3 , the gate 231 is also connected to the external circuit L21 through the plug 233 , and the external circuit L21 is connected to a corresponding control circuit to control the gate 231 .

In this embodiment, the upper surface of the semiconductor substrate corresponding to the channel region region of the reset transistor 230t is not on the same plane as the upper surface of the photodiode region 260, that is, as shown in FIG. There is a height difference H1 between the upper surfaces of the regions 260 . At this time, there is no horizontal isolation problem between the channel region of the reset transistor 230t and the photodiode region 260 . Therefore, no isolation structure is required between the reset transistor 230t and the photodiode region 260 . Compared with the traditional planar structure, the back-illuminated image sensor provided by this embodiment can reduce the isolation structure between the reset transistor 230t and the photodiode region in the original traditional image sensor, so that under the same pixel unit size condition, The back-illuminated image sensor provided by this embodiment can reduce the area of the pixel unit occupied by the non-photoelectric conversion element, increase the filling rate of the photoelectric conversion element (photodiode), and improve the utilization rate of the area of the pixel unit.

Further, the upper surface of the semiconductor substrate corresponding to the channel region of the reset transistor 230t is higher than the upper surface of the semiconductor substrate corresponding to the photodiode region 260 by more than 30nm, that is, in FIG. 3 , the height difference H1 ranges above 30nm. At this time, the isolation between the reset transistor 230t and the photodiode region 260 is more ideal.

Please continue to refer to FIG. 3 , as mentioned above, the floating diffusion region 240 is located in one of the second regions, and the second region is a raised structure, and the raised structure also has a top surface and two side surfaces. The bottoms of the two sides of the protruding structure also have sidewalls 241 , and the sidewalls 241 help to isolate the gate 251 of the transfer transistor 250 t from the floating diffusion region 240 .

In this embodiment, the upper surface of the semiconductor substrate corresponding to the floating diffusion region 240 is higher than the corresponding upper surface of the semiconductor substrate of the photodiode region 260, that is, as shown in FIG. 3 , the upper surface of the semiconductor substrate corresponding to the floating diffusion region 240 There is a height difference H2 between the surface and the corresponding upper surface of the semiconductor substrate of the photodiode region 260 . Since the transfer transistor 250t is located between the floating diffusion region 240 and the photodiode region 260, and the transfer transistor 250t has a channel region 250, the upper surface of the channel region 250 (ie, the upper surface of the semiconductor substrate corresponding to the channel region) It is on the same plane as the upper surface of the photodiode region 260 (that is, the upper surface of the semiconductor substrate corresponding to the photodiode), so at this time, the upper surface of the semiconductor substrate corresponding to the floating diffusion region 240 is on the same plane as the channel region region 250 of the transfer transistor 250t. The upper surfaces are not on the same plane, and there is a height difference H2 between them, as shown in Figure 3. Compared with the conventional planar structure, in the back-illuminated image sensor provided by this embodiment, the miller capacitance between the floating diffusion region 240 and the transfer transistor 250t will be reduced, so that the photocharges (photogenerated carriers) ) The transfer and transmission speed is accelerated, and the conversion efficiency is improved.

Further, the upper surface of the floating diffusion region 240 is higher than the upper surface of the photodiode region 260 by more than 30 nm, that is, in FIG. 3 , the height difference H2 is more than 30 nm. Since the upper surface of the channel region 250 of the transfer transistor 250t is flush with the upper surface of the photodiode region 260, when the upper surface of the floating diffusion region 240 is higher than the upper surface of the photodiode region 260 by more than 30nm, the floating diffusion region 240 The height difference H2 between the upper surface and the upper surface of the channel region 250 of the transfer transistor 250t is also more than 30nm. At this time, the bulk capacitance between the floating diffusion region 240 and the transfer transistor 250t is greatly reduced, and the conversion efficiency of photoelectric charges is remarkable. improve.

In this embodiment, the floating diffusion region 240 and the plug 242 are electrically connected through an ohmic contact region (not shown), and the ohmic contact region can reduce the contact resistance between the plug 242 and the floating diffusion region 240, so that the pixel Unit performance improved.

In this embodiment, the floating diffusion region 240 is also connected to the external circuit L22 through the plug 242 , and the external circuit L22 is connected to a corresponding control circuit to perform operations such as resetting the floating diffusion region 240 .

Please continue to refer to FIG. 3. In this embodiment, the channel region 250 of the transfer transistor 250t is located in the semiconductor substrate 200 between the photodiode region 260 and the floating diffusion region 240, and the gate 251 of the transfer transistor 250t is located therein. On the surface of the channel region 250 , there is a gate dielectric layer (not shown) between the gate 251 and the channel region 250 .

Please continue to refer to FIG. 3 , the gate 251 of the transfer transistor 250 t is also connected to the external circuit L23 through the plug 252 , and the external circuit L23 is connected to the control circuit to control the gate 251 .

Please continue to refer to FIG. 3 , a photodiode is formed in the photodiode region 260 , and the structure of the photodiode generally includes a PN junction or a PIN junction. The PN junction (or PIN junction) of the photodiode has a relatively large area in order to receive more incident light. The photodiode works under the action of reverse voltage. When there is no light, the reverse current (dark current) is extremely weak. When there is light, the reverse current increases rapidly. This reverse current is called photocurrent. A photodiode with a PIN junction is doped with an N-type semiconductor layer with a very low concentration in the middle of the PN junction to increase the width of the depletion region, reduce the influence of diffusion movement, and increase the response speed. Because the doping concentration of the N-type semiconductor layer of the doped layer is low, it is almost an intrinsic (Intrinsic) semiconductor, so it is called the I layer, so this structure becomes a PIN photodiode.

It should be noted that there is a double broken line with an arrow below the bottom of the semiconductor substrate 200 corresponding to the photodiode region 260 in FIG. It is a back-illuminated sensor, and the rest of this manual follows this operation.

Please continue to refer to FIG. 3 , the source follower transistor 270 t is located in the second region on the right of the floating diffusion region 240 . The second area can be specifically divided into a first part 2701 and a second part 2702 . The channel region of the source follower transistor 270t is located in the region where the second portion 2702 is located, that is, the channel region of the source follower transistor 270t is located in the second portion 2702 in the beam structure. The second portion 2702 has a top surface and two sides (faces not labeled). The top surface and two sides of the second part 2702 are covered by a gate dielectric layer (not shown), and the gate dielectric layer is covered by the gate 271 of the source follower transistor 270t, that is, the gate 271 surrounds the top of the channel region. face and two sides.

Since the gate 271 of the source follower transistor 270t covers the top surface and two sides of the second portion 2702, that is, the gate 271 of the source follower transistor 270t covers the top surface and two sides of the channel region of the source follower transistor 270t, therefore, At this time, the source follower transistor 270t has a gate-enclosed structure on three sides. This surrounding gate structure can increase the physical width of the channel region of the source-following transistor 270t, so the performance of the source-following transistor 270t can be improved, such as reducing leakage current and shortening the physical length of the channel region, etc., and can make the source-following transistor 270t The feature size is reduced.

It should be noted that, in other embodiments of the present invention, the source follower transistor 270t may also form a gate on only one side of the second part 2702, or form a gate on both sides of the second part 2702, or form a gate on the second part 2702. The top surface and one side surface of the two parts 2702 form a gate.

Please continue to refer to FIG. 3 , the source follower transistor 270t also has sidewalls 272 located between the well region 210 and the gate 271 to isolate the gate 271 from the well region 210 and improve the performance of the source follower transistor 270t.

Please continue to refer to FIG. 3 , the gate 271 of the source follower transistor 270 t is also connected to the external circuit L24 through the plug 273 , and the external circuit L24 is connected to a corresponding control circuit to control the gate 271 .

In this embodiment, the upper surface of the semiconductor substrate corresponding to the channel region of the source follower transistor 270t and the upper surface of the semiconductor substrate corresponding to the photodiode region 260 are not on the same plane, that is, as shown in FIG. 3 , the second part 2702 There is a height difference H3 between the upper surface and the upper surface of the photodiode region 260 . At this time, there is no horizontal isolation problem between the channel region of the source follower transistor 270 t and the photodiode region 260 . Therefore, no isolation structure is required between the source follower transistor 270 t and the photodiode region 260 . Compared with the traditional planar structure, the back-illuminated image sensor provided by this embodiment can reduce the original isolation structure provided between the source follower transistor 270t and the photodiode region in the traditional image sensor, so that under the same pixel unit size condition , the back-illuminated image sensor provided in this embodiment can reduce the area of the pixel unit occupied by the non-photoelectric conversion element, increase the filling rate of the photoelectric conversion element, and improve the utilization rate of the area of the pixel unit.

Further, the upper surface of the semiconductor substrate corresponding to the channel region of the source follower transistor 270t is higher than the upper surface of the semiconductor substrate corresponding to the photodiode region 260 by more than 30nm, that is, the size range of the height difference H3 in FIG. 3 is more than 30nm. At this time, the isolation between the source follower transistor 270t and the photodiode region 260 is more ideal.

Please refer to FIG. 4 , which shows a schematic diagram of the three-dimensional structure of the source follower transistor 270t shown in FIG. 3 .

Comparing with the existing planar source-follower transistor in FIG. 1 , it can be seen that the structure of the source-follower transistor is redesigned and transformed in this embodiment to form a three-dimensional source-follower transistor structure. Specifically, the source follower transistor 270t has a channel region located in the area where the second part 2702 is located, and the second part 2702 is located above the first part 2701, and the second part 2702 and the first part 2701 constitute the second part in a raised structure. region, so the source follower transistor 270t has a three-dimensionally independent channel region. The source follower transistor 270t also has a gate 271 surrounding the top surface and two sides of the channel region, and a gate dielectric layer (not shown) between the gate 271 and the channel region.

It can also be seen from FIG. 4 that there is a spacer 272 between the well region 210 and the gate 271 , and the sidewall 272 can enhance the insulating effect between the well region 210 and the gate 271 .

It can also be seen from FIG. 4 that the source 274 of the source follower transistor 270t is formed on one of the end surfaces of the second part 2702 (in FIG. 4, the source 274 is actually covered by a dielectric layer, so it is shown by a dotted line), and the The drain (not shown) of the source follower transistor 270t is formed on the other end face of the second portion 2702 .

Please continue to refer to FIG. 4 , in this embodiment, the source follower transistor 270t is a masked channel transistor, that is, when the source follower transistor 270t is working, the channel of the source follower transistor 270t is formed inside the channel region. The specific formation position of the trench is shown in the area TA (trench area) in FIG. , the region TA represents the part where the channel doping region is located, and the non-channel doping region is located between the region TA and the gate 271 .

The low-frequency 1/f noise of the source follower transistor 270t (the power spectral density of the current noise of the low-frequency part is inversely proportional to the frequency f, and the noise is called "1/f noise") is one of the key factors affecting the performance of the pixel unit. The lower the f noise, the better the performance of the pixel unit and the higher the image quality. When the source follower transistor 270t is a buried channel device, low frequency 1/f noise can be reduced. Because when the buried channel device is working, the current mainly flows in the channel away from the surface of the channel region region, avoiding the flow of electrons in the region close to the surface of the channel region region, thereby reducing the flow of current in the region close to the surface of the channel region region, Scattering occurs at the interface, resulting in reduced low-frequency 1/f noise, ultimately improving the performance of back-illuminated image sensors. In addition, the source-follower transistor 270t adopts a buried channel device, which can also save manufacturing cost.

In this embodiment, the channel region of the source-following transistor 270t is located inside the second portion 2702. Therefore, the source-following transistor 270t can easily form a buried channel device, and after forming the buried channel device, the gate 271 can be formed from the vertical channel region. The same voltage is applied in three directions on the top surface and two sides of the region, so that when electrons flow, they flow concentratedly inside the channel region.

After testing, when the source-follower transistor 270t of this embodiment is in the working state, the current density in the region far away from the surface of the channel region region is relatively large (that is, the internal current in the channel region region is relatively large), and the region close to the surface of the channel region region The current density is small, and the current density of the former is more than 10% larger than that of the latter, and the low-frequency 1/f noise is greatly reduced at this time.

Please continue to refer to FIG. 4 , the source-follower transistor 270t has a gate 271 surrounding three surfaces (including the top surface and two side surfaces) of the channel region. Since the channel is formed in the region where the channel region is opposite to the gate, in this embodiment, the channel physical width of the source follower transistor 270t can be greatly increased. Specifically, in an ideal state, the region TA in FIG. 4 That is, it represents the channel formed when the source follower transistor 270t works, and the entire second part 2072 is the channel region. At this time, the physical width of the channel region is equal to (2h+l), while the channel region in the existing planar source follower transistor is usually only 1. It can be seen that, compared with the existing planar source-follower transistor, the physical width of the channel region of the source-follower transistor 270t provided in this embodiment can be significantly extended. Therefore, in the source follower transistor 270t provided by this embodiment, the current passing through the channel region can be significantly increased. Conversely, when the same passing current is to be achieved, only a small device size is required to adopt the follower transistor provided by this embodiment.

As can be seen from the above description, the three-dimensional source follower transistor 270t provided by this embodiment can reduce the lateral size of the transistor while maintaining the physical length and physical width of the effective channel region of the transistor, and increase the photoelectric conversion element (that is, the photoelectric conversion element) in the pixel unit. Diode) filling rate, so as to achieve the purpose of reducing the chip area.

In this embodiment, the channel area of the source follower transistor 270t can be conveniently adjusted according to actual needs, and more importantly, the shape and position of the gate 271 can also be conveniently adjusted according to actual needs. For example, as mentioned above, the gate 271 may only cover one of the side surfaces and the top surface of the channel region. Also, there are various ways to connect the gate 271 of the source follower transistor 270t. Therefore, the source-following transistor 270t can be controlled flexibly and variously. Compared with the control method of the traditional source-following transistor 270t, the source-following transistor 270t of this embodiment has a stronger control over the channel, so the control of the source-following transistor 270t can be improved. performance, thereby improving image quality.

It should be noted that the image sensor provided in this embodiment usually includes a pixel array formed by a plurality of pixel units arranged in an array, therefore, transistors between different pixel units can be sequentially formed along the same raised structure, As shown in FIG. 4 , two gates 271 are sequentially formed along the channel region of the same raised structure (in fact, multiple gates may be sequentially formed along the same channel region of the beam structure).

It should be noted that, although not shown in FIG. 4, in the image sensor provided by this embodiment, the reset transistor may have the same three-dimensional structure and properties as the source follower transistor, so that the The image sensor can further reduce the chip area.

Although not shown in FIG. 3 and FIG. 4 , in this embodiment, the back-illuminated image sensor may also have an isolation structure (not shown), and the isolation structure may specifically be a shallow trench isolation structure. The photodiode region may be disposed below the bottom of the STI structure, that is, the STI structure at this time is located above the upper surface of the photodiode region, thereby isolating the upper surface of the photodiode region from other devices. And because the photodiode region is located below the bottom of the trench between adjacent channel regions, the photodiode region can be closer to the light source. Compared with the traditional planar structure, the image sensor provided by this embodiment can be incident on the back Under the condition of light, the loss of luminous flux caused by passing through the semiconductor substrate in the optical path is reduced, and the conversion efficiency of light is improved.

As mentioned above, when the photodiode region can be disposed below the bottom of the shallow trench isolation structure, the gate of the transfer transistor can be correspondingly disposed above the shallow trench isolation structure. It should be noted that the above and below in this embodiment are opposite to the incident direction of light, and when viewed along the incident direction of light, the gate of the transfer transistor is located at the bottom of the shallow trench isolation structure.

It should be noted that, in other embodiments of the present invention, the pixel unit of the back-illuminated image sensor may also have a gate transistor, and the structure of the gate transistor may be the same as that of the reset transistor or source follower in this embodiment. The structures of the transistors are similar or the same, and the functions and configurable positions of the gate transistors are well known to those skilled in the art, and will not be repeated here.

Still another embodiment of the present invention provides another back-illuminated image sensor, the back-illuminated image sensor includes a pixel array, and the pixel array includes a plurality of pixel units arranged in an array.

Please refer to FIG. 5 , which shows the pixel units in the back-illuminated image sensor provided by this embodiment.

The pixel unit includes:

A semiconductor substrate 300. The semiconductor substrate 300 includes a first region (not marked) and three second regions (not marked), and the second regions are in a raised structure. In FIG. 5 , the first area and the second area are separated by a dotted line to show the difference. The semiconductor substrate 300 has a well region 310 on it. The region where the well region 310 is located includes all the three second regions with raised structures, and also includes part of the first region.

a photoelectric conversion element located in the first region. In this embodiment, the photoelectric conversion element is a photodiode, and the photodiode is located in the photodiode region 360 on the semiconductor substrate 300 , and the photodiode in the photodiode region 360 is used for photoelectric conversion to generate signal charges.

The floating diffusion region 340 is located on the well region 310 , and the floating diffusion region 340 is partially located in one of the second regions and is partially located in the first region, as shown in FIG. 5 . The floating diffusion region 340 is used to collect signal charges to generate a signal potential.

A transfer transistor located on the well region 310 and between the floating diffusion region 340 and the photodiode region 360 . The transfer transistor includes a source (not shown) and a drain (not shown) in the semiconductor substrate 300 . The source is electrically connected to the photodiode region 360 , and the drain is electrically connected to the floating diffusion region 340 . The transfer transistor is used to control the transfer of the signal charge from the photodiode region 360 to the floating diffusion region 340 .

The pinning layer 351 is located on the channel region 350 of the transfer transistor. In this embodiment, the pinning layer 351 also serves as the gate of the transfer transistor.

The reset transistor is located on the well region 310 . And the channel region of the reset transistor is located in another second region (in FIG. 5 , the channel region of the reset transistor is located in the second region to the left of the floating diffusion region 340 ). The reset transistor has a gate 331, the reset transistor also has a drain located in the semiconductor substrate 300, the drain is electrically connected to the floating diffusion region 340, the source of the reset transistor is usually connected to a reset voltage, and the reset transistor is used for resetting The potential of the floating diffusion region 340 .

A source-following transistor, the source-following transistor is located on the well region 310, and the channel region of the source-following transistor is located in another said second region (in FIG. in the second region to the right). The source follower transistor includes a gate 371 located on the semiconductor substrate 300, the gate 371 is electrically connected to the floating diffusion region 340, and the source follower transistor is used to amplify the signal potential, that is, the drain of the source follower transistor outputs one and floats Electrical signals related to the potential of the diffusion region 340 .

The dielectric layer 320 , the dielectric layer 320 fills and surrounds the surface of the gate region of each transistor, and the dielectric layer 320 is penetrated by the plug 333 , the plug 342 , the plug 352 and the plug 373 . The plug 333 is connected to the gate 331 of the reset transistor, the plug 342 is connected to the floating diffusion region 340 , the plug 352 is connected to the pinning layer 351 , and the plug 373 is connected to the gate 371 of the source follower transistor.

The reset transistor, the floating diffusion region, the transfer transistor and the source follower transistor in the pixel unit will be further described below in order from left to right in FIG. 5 .

Please continue to refer to FIG. 5 , the reset transistor is located in the second region to the left of the floating diffusion region 340 . The second area can be specifically divided into a first part 3301 and a second part 3302 . The channel region of the reset transistor is located in the area where the second portion 3302 is located. The second portion 3302 has a top surface and two sides (faces not labeled). The top surface and two side surfaces of the second part 3302 are covered by a gate dielectric layer (not shown), and the gate dielectric layer is covered by the gate 331 of the reset transistor, that is, the gate 331 surrounds the top surface and the top surface of the channel region. two sides.

Since the gate 331 of the reset transistor covers the top surface and two sides of the second part 3302, that is, the gate 331 of the reset transistor covers the top surface and two sides of the channel region of the reset transistor, therefore, the reset transistor has three sides at this time. fence structure. The surrounding gate structure can increase the physical width of the channel region of the reset transistor, thereby improving the performance of the reset transistor.

It should be noted that, in other embodiments of the present invention, the gate 331 of the reset transistor may only cover one side of the second part 3302, or only cover two sides of the second part 3302, or only cover the second side. The top surface and one of the sides of portion 3302.

Please continue to refer to FIG. 5 , the reset transistor further has sidewalls 332 located between the well region 310 and the gate 331 , and the sidewalls 232 cover two sides of the first portion 2301 . Therefore, the sidewall 332 can isolate the gate 331 from the well region 310 , so that the performance of the reset transistor is improved.

Please continue to refer to FIG. 5 , the gate 331 is also connected to an external circuit L31 through a plug 333 , and the external circuit is connected to a corresponding control circuit to control the gate 331 .

In this embodiment, the upper surface of the semiconductor substrate corresponding to the channel region of the reset transistor is not on the same plane as the upper surface of the photodiode region 360, that is, as shown in FIG. There is a height difference H4 between the upper surfaces of 360 . At this time, there is no horizontal isolation problem between the channel region of the reset transistor and the photodiode region 360 .

Further, the upper surface of the semiconductor substrate corresponding to the channel region of the reset transistor is higher than the upper surface of the semiconductor substrate corresponding to the photodiode region 360 by more than 30 nm, that is, in FIG. 5 , the height difference H4 ranges above 30 nm. At this time, the isolation between the reset transistor and the photodiode region 360 is more ideal.

Please continue to refer to FIG. 5 , as mentioned above, the floating diffusion region 340 is located in one of the second regions, and the second region is a raised structure, and the raised structure also has a top surface and two side surfaces. The bottoms of the two sides of the protruding structure also have sidewalls 341 , and the sidewalls 341 help to isolate the gate of the transfer transistor from the floating diffusion region 340 .

In this embodiment, the upper surface of the floating diffusion region 340 is higher than the upper surface of the photodiode region 360 , that is, as shown in FIG. 5 , there is a height difference H5 between the upper surface of the floating diffusion region 340 and the upper surface of the photodiode region 360 . Since the upper surface of the channel region 350 of the transfer transistor is on the same plane as the upper surface of the photodiode region 360, the upper surface of the floating diffusion region 340 is not on the same plane as the upper surface of the channel region of the transfer transistor. There is a height difference H5 between them, as shown in Figure 5. Compared with the traditional planar structure, in the back-illuminated image sensor provided by this embodiment, the bulk capacitance between the floating diffusion region 340 and the transfer transistor is reduced, so that the transfer and transmission speed of photocharges (photogenerated carriers) Speed up and improve conversion efficiency.

Further, the upper surface of the floating diffusion region 340 is higher than the upper surface of the photodiode region 360 by more than 30 nm, that is, as shown in FIG. 5 , the height difference H5 is more than 30 nm. At this time, the bulk capacitance between the floating diffusion region 340 and the transfer transistor is greatly reduced, and the conversion efficiency of photoelectric charges is significantly improved.

In this embodiment, there is a highly doped ohmic contact region (not shown) on the upper surface of the floating diffusion region 340, the floating diffusion region 340 is connected to the plug 342 through the ohmic contact region, and the ohmic contact region helps to reduce There is a contact resistance between the plug 342 and the floating diffusion region 340, which improves the performance of the pixel unit.

In this embodiment, the floating diffusion area 340 is also connected to the external circuit L32 through the plug 342 , and the external circuit L32 is connected to a corresponding control circuit to perform operations such as resetting the floating diffusion area 340 .

Please continue to refer to FIG. 5 , in this embodiment, the back-illuminated image sensor further has a pinning layer 351 located on the upper surface of the photodiode region 360 . As mentioned above, the pinning layer 351 also serves as the gate of the transfer transistor, that is, the gate of the transfer transistor is not only located on the surface of the channel region 350 , but also located on the upper surface of the photodiode region 360 .

The channel region 350 of the transfer transistor is located in the semiconductor substrate 300 between the photodiode region 360 and the floating diffusion region 340, and there is a gate dielectric layer (not shown) between the pinning layer 351 and the channel region 350 . Due to the existence of the pinning layer 351 , dark current caused by interface defects between the semiconductor substrate (usually silicon) and the dielectric layer (usually silicon oxide) can be reduced, thereby improving the photosensitive performance of the photodiode in the photodiode region 360 .

In this embodiment, the pinning layer 351 is connected to the external circuit L33 through the plug 352, and the external circuit L33 is connected to the control circuit to control the gate.

Please continue to refer to FIG. 5 , the source follower transistor is located in the second region on the right of the floating diffusion region 340 . The second area can be specifically divided into a first part 3701 and a second part 3702 . The channel region of the source-follower transistor is located in the region where the second portion 3702 is located, that is, the channel region of the source-follower transistor is located in the second portion 3702 in the beam structure. The second portion 3702 has a top surface and two sides (faces not labeled). The top surface and two sides of the second part 3702 are covered by a gate dielectric layer (not shown), and the gate dielectric layer is covered by the gate 371 of the source follower transistor, that is, the gate 371 surrounds the top surface of the channel region and two sides.

Since the gate 371 of the source-following transistor covers the top surface and two sides of the second part 3702, that is, the gate 371 of the source-following transistor covers the top surface and two sides of the channel region of the source-following transistor, therefore, the source The follower transistor has a gate-enclosed structure on three sides. The surrounding gate structure can increase the physical width of the channel region of the source follower transistor, thereby improving the performance of the source follower transistor (such as reducing leakage current and shortening the physical length of the channel region, etc.).

It should be noted that, in other embodiments of the present invention, the source follower transistor can also form a gate on one side of the second part 3702, or form a gate on both sides of the second part 3702, or form a gate on the second part 3702 The top surface of 3702 and one of the sides form the gate.

Please continue to refer to FIG. 5 , the source follower transistor also has a sidewall 372 located between the well region 310 and the gate 371 , thereby isolating the gate 371 from the well region 310 and improving the performance of the source follower transistor.

Please continue to refer to FIG. 5 , the gate 371 is also connected to an external circuit L34 through a plug 373 , and the external circuit is connected to a corresponding control circuit to control the gate 371 .

In this embodiment, the upper surface of the gate 371 of the source follower transistor (corresponding to the upper surface of the semiconductor substrate silicon) and the upper surface of the photodiode region 360 are not on the same plane, that is, as shown in FIG. 5 , the second part 3702 There is a height difference H3 between the upper surface and the upper surface of the photodiode region 360 . At this time, the upper surface of the channel region region of the source follower transistor (the upper surface of the corresponding semiconductor substrate silicon) is also not on the same plane as the upper surface of the photodiode region 360, so the channel region region of the source follower transistor is not on the same plane as the photodiode region. There is no problem of horizontal isolation between regions 360 . Moreover, no isolation structure is required between the source follower transistor and the photodiode region 360 . Compared with the traditional planar structure, the back-illuminated image sensor provided by this embodiment can reduce the original isolation structure between the source follower transistor and the photodiode region in the traditional image sensor, so that under the same pixel unit size condition, The back-illuminated image sensor provided by this embodiment can reduce the area of the pixel unit occupied by the non-photosensitive element, increase the filling rate of the photoelectric conversion element, and improve the utilization rate of the area of the pixel unit.

Further, the upper surface of the channel region region (corresponding to the semiconductor substrate) of the source follower transistor is higher than the upper surface of the photodiode region 360 (corresponding to the semiconductor substrate) by more than 30nm, that is, the size of the height difference H6 in FIG. 5 is 30nm above. At this time, the isolation between the source follower transistor and the photodiode region 360 is more ideal.

In this embodiment, the source-follower transistor may be a buried channel device to reduce low-frequency 1/f noise and save manufacturing costs, and reference may be made to the corresponding content in the foregoing embodiments.

It should be noted that although not shown in FIG. 5 , the back-illuminated image sensor provided in this embodiment may also have an isolation structure (not shown), and the photodiode region 360 may be disposed in the isolation structure, that is, When the isolation structure is located above the upper surface of the photodiode region 360, the upper surface of the photodiode region 360 is isolated from other devices. And the photodiode region 360 is located in the bottom of the trench between adjacent channel regions, therefore, the photodiode region 360 can be closer to the light source. Compared with the traditional planar structure, the image sensor provided in this embodiment can be in Under the condition of incident light from the back, the light flux loss caused by passing through the semiconductor substrate in the light path is reduced, and the light conversion efficiency is improved.

For more details about the structure and properties of the back-illuminated image sensor provided in this embodiment, reference may be made to the corresponding content in the foregoing embodiments.

Another embodiment of the present invention also provides a method for forming a back-illuminated image sensor, please refer to FIG. 6 to FIG. 15 in conjunction.

Referring to FIG. 6 , a semiconductor substrate 400 is provided.

In this embodiment, the semiconductor substrate 400 may be a silicon substrate or a silicon germanium substrate, etc., or may be silicon-on-insulator. In this embodiment, a silicon substrate is taken as an example, and the semiconductor substrate 400 provides a carrier for forming pixel units.

Referring to FIG. 7 , a dielectric layer is formed on the surface of the semiconductor substrate 400 . Specifically, the dielectric layer may include a buffer layer 401 and a mask layer 402 .

In this embodiment, the material of the buffer layer 401 can be silicon dioxide (SiO2), and the buffer layer 401 can release the stress between the mask layer 402 and the semiconductor substrate 400, and can also increase the thickness of the mask layer 402 and the semiconductor substrate. Adhesion between 400. The buffer layer 401 may be formed on the semiconductor substrate 400 using a wet oxidation method.

In this embodiment, the material of the mask layer 402 may be silicon nitride (SiN), so as to prevent the stress of silicon nitride from causing defects in the semiconductor substrate 400 through the buffer layer 401 . A mask layer 402 may be formed on the buffer layer 401 by using low pressure chemical vapor deposition (Low Pressure Chemical Vapor Deposition, LPCVD), and then the mask layer 402 is annealed.

Please continue to refer to FIG. 7, the buffer layer 401, the mask layer 402 and the semiconductor substrate 400 are etched to form a plurality of discrete shallow trenches in the semiconductor substrate 400. The shallow trenches 403a and 403a are shown in FIG. Shallow trench 403b is representative.

The semiconductor substrate 400 between adjacent shallow trenches forms a second region (not labeled), and the second region is a raised structure. Three of the second regions are shown in FIG. 7 , and the middle one is the The second region is located between the shallow trench 403a and the shallow trench 403b, and the other two second regions are respectively located on the left side of the shallow trench 403a and on the right side of the shallow trench 403b. The rest of the semiconductor substrate 400 is a first region (not marked). In this embodiment, the second region is separated from the first region by a dotted line to distinguish them.

The process of forming the shallow trench may be: pattern the mask layer 402 and the buffer layer 401, and then use the patterned mask layer 402 and the buffer layer 401 as a mask to etch the semiconductor substrate by reactive ion etching. Bottom 400, shallow trenches 403a and shallow trenches 403b are formed.

Referring to FIG. 8 , the shallow trench 403 a and the shallow trench 403 b are filled with the first dielectric layer 404 .

In this embodiment, after the first dielectric layer 404 fills the shallow trenches 403a and 403b, the buffer layer 401 and mask layer 402 shown in FIG. 7 can be removed by chemical mechanical polishing (CMP) to form a flat surface , at this time the upper surface of the first dielectric layer 404 is flush with the upper surface of the semiconductor substrate 400 .

In this embodiment, the material of the first dielectric layer 404 may be silicon oxide or silicon nitride, and the dielectric layer deposition process for forming the first dielectric layer 404 may specifically be Physical Vapor Deposition (Physical Vapor Deposition, PVD) or Chemical Vapor Deposition ( Chemical Vapor Deposition, CVD).

It should be noted that the shallow trenches are not marked in FIGS. 8 to 10 , therefore, the shallow trenches 403 a and 403 b may refer to FIGS. 7 and 11 .

Referring to FIG. 9 , etch back the first dielectric layer 404 located in the shallow trenches 403 a and 403 b until the upper surface of the first dielectric layer 404 is lower than the upper surface of the semiconductor substrate 400 to form a first dielectric layer 406 .

The first dielectric layer 404 can be etched by wet etching, dry etching or a combination thereof.

Specifically, in this embodiment, a wet etching process is used to etch the first dielectric layer 404. The process may be as follows: firstly, a photoresist layer 405 is formed on the surface of the semiconductor substrate 400 and the first dielectric layer 404, and then patterned The photoresist layer 405 forms an opening (not labeled) exposing the first dielectric layer 404, and then using the photoresist layer 405 with the opening as a mask, using dilute hydrofluoric acid (HF) solution as an etchant, Perform wet etching. Wet etching has excellent selectivity without damaging other material layers.

Please refer to FIG. 10, after forming the first dielectric layer 406, continue to etch the first dielectric layer 406 until the bottom surfaces of the shallow trenches 403a and 403b are exposed. Some still have the remaining first dielectric layer 407 .

Please refer to FIG. 11, remove the photoresist layer 405 shown in FIG. 10, and continue to pattern the first dielectric layer 407 shown in FIG. 10 through the patterning process until the remaining first dielectric layer 407 remains in the shallow trench The sides form respective side walls. The patterning process can also be a wet etching process. Finally, the remaining first dielectric layer 407 forms sidewalls 412 , sidewalls 422 and sidewalls 432 respectively. Each of the sidewalls can strengthen the isolation between each gate and each channel region.

In this embodiment, before performing subsequent steps, one or more thermal oxidation and etching processes may be used to repair each surface, so as to eliminate the (silicon) surface damage caused by the above-mentioned etching processes.

Referring to FIG. 12 , photoelectric conversion elements are formed in the first region. In this embodiment, the photoelectric conversion element is specifically a photodiode, therefore, the process of forming the photoelectric conversion element is the process of forming the photodiode.

The process of forming a photodiode includes: forming a well region 409 through a patterning process and a doping process, and the well region 409 includes a region where the raised structure (ie, the second region) located between adjacent shallow trenches is located, and then A photodiode region 440 is formed at the bottom of the shallow trench 403b by a doping process.

It should be noted that although not shown in the figure, in this embodiment, an isolation structure may be formed at the bottom of the shallow trench 403b, and the photodiode region 440 may be located in the isolation structure. When the photodiode region 440 is located in the isolation structure, the electrical isolation between the photodiode and other devices is better, so that the performance of the finally formed back-illuminated image sensor is improved.

The well region 409 also provides a region for the formation of subsequent transistors, and the subsequent floating diffusion region, the channel region region of the source follower transistor, and the channel region region of the reset transistor can all be located in the well region 409 .

In this embodiment, the well region 409 can be P-type doped, and can be doped with boron or boron fluoride. The photodiode region 440 has a photodiode including a PN junction or a PIN junction (not labeled). The process of forming a photodiode is well known to those skilled in the art and will not be repeated here.

Referring to FIG. 13 , the gate dielectric layer and the gate of the source follower transistor, the reset transistor and the transfer transistor are formed.

In this embodiment, each gate dielectric layer is not shown. However, in this embodiment, a deposition process may be used to form an entire layer of gate dielectric layer covering the surface of each raised structure (including the top surface and two side surfaces), and then each discrete gate dielectric layer may be formed through a patterning process.

Please continue to refer to FIG. 13 , the process of forming each gate can be: using a deposition process to form a gate layer (not shown) covering the top of the semiconductor substrate 400 (including covering each well region and the upper surface of each gate dielectric layer); Resist 460 covers the gate layer; then using a corresponding photoresist plate, the photoresist layer 460 is patterned to form an opening 409 through an exposure and development process, and the opening 409 exposes the gate layer located in the non-gate region; The photoresist layer 460 having the opening 409 is used as a mask, and the gate layer exposed by the opening 409 is etched away (the removed part is the gate layer 421 shown in FIG. 13 ), and the remaining gate layer becomes a different transistor The gates include the gate 431 of the source follower transistor, the gate 411 of the reset transistor, and the gate 451 of the transfer transistor, as shown in FIG. 13 .

In this embodiment, the material of the gate layer may be polysilicon, or metal, or a combination of polysilicon and metal. When the material of the gate layer 421 is polysilicon, the gate layer 421 covering the surface of the floating diffusion region may be removed by etching with a wet etching solution such as hot phosphoric acid solution.

It should be noted that, in other embodiments of the present invention, the gate dielectric layer and the gate layer covering the surface of each raised structure may also be formed together first, and then the stacked layers of the gate dielectric layer and the gate layer are patterned together to form Separate gate dielectric layers and gates.

Please continue to refer to FIG. 13 , the raised structure on the far left in FIG. 13 (that is, the second region on the left) is divided into a first part 4101 and a second part 4102. A dotted line separates them for distinction. Wherein, the first part has two sides, and the second part 4102 has a top surface and two sides. The gate 411 covers the top surface and two side surfaces of the second part 4102 , in fact, there is the aforementioned gate dielectric layer between the gate 411 and the second part 4102 , which is not shown.

Since the gate 411 covers the top surface and two side surfaces of the second part 4102, the second part 4102 is the channel region of the reset transistor, and it can be known that the reset transistor in this embodiment has a three-sided gate-enclosed structure. The structure can increase the physical width of the channel region of the reset transistor, thereby improving the performance of the reset transistor, such as reducing leakage current and shortening the physical length of the channel region, and reducing the feature size of the reset transistor.

It should be noted that, in other embodiments of the present invention, the gate of the reset transistor may only cover one side of the channel region of the reset transistor, or only cover two sides of the channel region of the reset transistor, or Only the top surface and one side surface of the channel region of the reset transistor are covered, which is not limited in the present invention.

Please continue to refer to FIG. 13, the protruding structure located on the far right in FIG. A dotted line separates them for distinction. Wherein, the first part has two sides, and the second part 4302 has a top surface and two sides. The gate 431 covers the top surface and two side surfaces of the second part 4302 , in fact, there is the aforementioned gate dielectric layer between the gate 431 and the second part 4302 , which is not shown.

Since the gate 431 covers the top surface and two side surfaces of the second part 4302, the second part 4302 is the channel region of the source follower transistor, and it can be seen that the source follower transistor in this embodiment has a three-sided surrounding gate structure. The surrounding gate structure can increase the physical width of the channel region of the source-following transistor, so it can improve the performance of the source-following transistor, such as reducing the leakage current and shortening the physical length of the channel region, etc., and can reduce the feature size of the source-following transistor.

It should be noted that, in other embodiments of the present invention, the gate of the source-following transistor may only cover one side of the channel region of the source-following transistor, or only cover two sides of the channel region of the source-following transistor. side, or only cover the top surface and one side of the channel region of the source follower transistor, which is not limited in the present invention.

Please refer to FIG. 14 , the source, drain and gate of the source follower transistor, the reset transistor and the transfer transistor are respectively formed by a doping process to form a floating diffusion region 420 .

In this embodiment, the floating diffusion region 420 is partly located in the first region, and partly located in one of the second regions (the middle one among the three second regions shown in FIG. 14 ), as shown in FIG. 14 shown.

In this embodiment, since the floating diffusion region 420 is partly located in one of the second regions, the upper surface of the floating diffusion region 420 is higher than the upper surface of the photodiode region 440, thereby preventing the floating diffusion region 420 from contacting the photodiode region. The diode region 440 has bulk capacitance to improve the performance of the back-illuminated image sensor.

Furthermore, the upper surface of the floating diffusion region 420 is higher than the upper surface of the photodiode region 440 by more than 30nm. At this time, the bulk capacitance between the floating diffusion region and the transfer transistor is greatly reduced, and the conversion efficiency of photoelectric charges is significantly improved.

In this embodiment, the upper surface of the channel region (that is, the second portion 4302) of the source follower transistor is higher than the upper surface of the semiconductor substrate corresponding to the photodiode region 440, so that there is a relatively small distance between the photodiode region 440 and the source follower transistor. Good isolation, the distance between the two can be reduced, so the size of the entire pixel unit can be reduced.

Further, the upper surface of the channel region of the source follower transistor is higher than the upper surface of the semiconductor substrate corresponding to the photodiode region 440 by more than 30 nm, so that the isolation between the photodiode region 440 and the source follower transistor is better.

In this embodiment, in the process of forming the gate 411 of the reset transistor, channel doping can be performed on the inside of the second part 4102 first, and the part of the second part 4102 that is channel-doped is the channel doping region (not shown), the region of the second part 4102 that is not subjected to channel doping is a non-channel doped region (not shown). Since the channel doping is performed on the inside of the second part 4102, the non-channel doping region is located between the channel doping region and the gate 411, so that the final dry reset transistor is a buried channel device, achieving reduction The purpose of small low frequency noise and cost reduction.

In this embodiment, in the process of forming the gate 431 of the source follower transistor, channel doping can be performed on the inside of the second part 4302 first, and the part of the second part 4302 that is channel-doped is the channel doping region ( not shown), the region of the second part 4302 that is not channel-doped is a non-channel doped region (not shown). Since the channel is doped inside the second part 4302, the non-channel doped region is located between the channel doped region and the gate 431, so that the final dry source follower transistor is a buried channel device, achieving The purpose of reducing low-frequency noise and reducing costs.

In this embodiment, the source and drain of the source follower transistor, the reset transistor and the transfer transistor can be formed by using a heavily doped process. When the material of the gate is polysilicon, it can be heavily doped by ion implantation process, so as to improve the conductivity of each gate. In the process of forming the source and the drain, the fabrication of other parts of the transistor, such as the fabrication of passive elements (resistors and capacitors, etc.), can also be completed at the same time.

Please continue to refer to FIG. 14 , in this embodiment, a dielectric layer 470 may be used to cover the source follower transistor, reset transistor and transfer transistor, and chemical mechanical polishing may be used to form a flat surface.

Please continue to refer to FIG. 14. In this embodiment, subsequently, in the dielectric layer 470, a plug 413 is formed to connect to the gate 411 of the reset transistor, a plug 421 is formed to connect to the floating diffusion region 420, and a plug 452 is formed to connect to the gate of the transfer transistor. Pole 451, forming a plug 433 connected to the gate 431 of the source follower transistor, the plug 413, the plug 421 and the plug 433 are filled in the formed opening, and the plug 413, the plug 421 and the plug 433 are respectively connected To the external circuit (including each metal layer), so as to realize the control of each transistor through the external circuit.

Please refer to FIG. 15. In the back-illuminated image sensor formed by the method for forming the back-illuminated image sensor provided in this embodiment, the three-dimensional structure of the source-following transistor is shown in FIG. The dielectric layer 470 and the corresponding plug structure).

As shown in FIG. 15, the source follower transistor has a well region 409 located on the semiconductor substrate 400, a channel region region (that is, the second part 4302) located on the well region 409, and the channel region region is located in the first part 4301 in a beam structure. Above, the beam structure has a top surface and two side surfaces, and the gate 431 simultaneously covers the top surface and two side surfaces of the channel region. There is also a sidewall 432 between the well region 409 and the gate 431 , and the sidewall 432 strengthens the isolation between the gate 431 and the well region. The source follower transistor also has a source 434 at one end of the channel region and a drain (not shown) at the other end of the channel region.

Due to the three-dimensional structure shown in Figure 15, the volume of the source-following transistor in this embodiment can be made smaller, therefore, the area of the back-illuminated image sensor using this source-following transistor can be reduced, and the photoelectric conversion element can be made The occupied area is increased to achieve the purpose of improving the image quality.

It should be noted that, in this embodiment, the reset transistor may have the same three-dimensional structure and properties as the source follower transistor. For more structures and properties of each transistor, reference may be made to the corresponding content in the foregoing embodiments of this specification.

Another implementation of the present invention provides another back-illuminated image sensor, please refer to FIG. 16 to FIG. 19 in conjunction.

Referring to FIG. 16 , a semiconductor substrate 500 is provided.

In this embodiment, the semiconductor substrate 500 may be a silicon substrate 500 or a silicon-germanium substrate 500, etc., or may be a silicon-on-insulator. In this embodiment, the silicon substrate 500 is taken as an example, and the semiconductor substrate 500 provides for forming pixel units. a carrier.

Please continue to refer to FIG. 16 , a plurality of discrete shallow trenches are formed in the semiconductor substrate 500 . In FIG. 16 , shallow trenches 501 a and 501 b are represented.

A second region (not labeled) is formed on the semiconductor substrate 500 between adjacent shallow trenches, and the second region is a raised structure. Figure 16 shows three of the second regions, the second region in the middle is located between the shallow trench 501a and the shallow trench 501b, and the other two second regions are respectively located on the left side of the shallow trench 501a and the shallow trench 501b. To the right of trench 501b. The rest of the semiconductor substrate 500 is a first region (not marked). In this embodiment, the second region is separated from the first region by a dotted line to distinguish them.

In this embodiment, the second region is an epitaxially grown single crystal semiconductor layer, specifically a single crystal silicon layer. The process of forming the shallow trench and the second region may be: forming a second dielectric layer (not shown) on the surface of the semiconductor substrate 500; a groove (not shown); epitaxially grow the single crystal semiconductor layer (ie, the second region) on the surface of the semiconductor substrate 500 exposed by the groove, and etch back the second dielectric layer until the formed The shallow trenches (including shallow trenches 501a and shallow trenches 501b), and the remaining second dielectric layer forms sidewalls covering the sides of the raised structure (such as sidewalls 512, 522 and 522 in Figure 16 side wall 532).

Please continue to refer to FIG. 16 , a photoelectric conversion element is formed in the first region. In this embodiment, the photoelectric conversion element is specifically a photodiode, therefore, the process of forming the photoelectric conversion element is the process of forming the photodiode.

The process of forming a photodiode includes: forming a well region 502 through a patterning process and a doping process, and the well region 502 includes a region where a raised structure (ie, the second region) is located between adjacent shallow trenches, and then A photodiode region 540 is formed at the bottom of the shallow trench 501b by a doping process.

It should be noted that although not shown in the figure, in this embodiment, an isolation structure may be formed at the bottom of the shallow trench 501b, and the photodiode region 540 may be located in the isolation structure. When the photodiode region 440 is located in the isolation structure, the electrical isolation between the photodiode and other devices is better, so that the performance of the finally formed back-illuminated image sensor is improved.

The well region 502 also provides a region for the formation of subsequent transistors, and the subsequent floating diffusion region, the channel region region of the source follower transistor, and the channel region region of the reset transistor can all be located in the well region 502 .

In this embodiment, the well region 502 can be P-type doped, and can be doped with boron or boron fluoride. The photodiode region 540 has a photodiode including a PN junction (not labeled) or a PIN junction. The process of forming a photodiode is well known to those skilled in the art and will not be repeated here.

Referring to FIG. 17 , the gate dielectric layers of the source follower transistor, the reset transistor and the transfer transistor are formed.

In this embodiment, each gate dielectric layer is not shown. The process of forming each gate can be as follows: a whole layer of gate dielectric layer is formed to cover the surface of each raised structure (including the top surface and two side surfaces) by deposition process, and then each discrete gate dielectric layer is formed by patterning process.

Please continue to refer to FIG. 17 to form the gates of the source follower transistor, the reset transistor and the transfer transistor. Specifically, a gate layer (not shown) can be formed by a deposition process to cover the semiconductor substrate 500 (including covering each well region and each The upper surface of the gate dielectric layer), and then remove the gate layer located in the non-channel region (please refer to FIG. 18 and FIG. 19 in conjunction). The gates include a gate 531 of a source follower transistor, a gate 511 of a reset transistor, and a pinning layer 550 . The pinning layer 550 can reduce the dark current of the photodiode region 540 .

Please continue to refer to FIG. 17 , a pinning layer 550 is formed on the surface of the shallow trench (ie, the upper surface of the photodiode region 540 ), and the pinning layer is located on the photodiode region 540 . In this embodiment, the pinning layer 550 covers the surface of the channel region (not marked) of the transfer transistor at the same time, and there is a gate dielectric layer (not shown) between the pinning layer 550 and the channel region of the transfer transistor. , therefore, the pinning layer 550 simultaneously functions as the gate of the transfer transistor.

Please continue to refer to FIG. 17 , the source (not shown) and drain (not shown) of the source follower transistor, the reset transistor and the transfer transistor are respectively formed through a doping process, and the floating diffusion region 520 is formed by doping.

In this embodiment, the floating diffusion region 520 is partly located in the first region, and partly located in one of the second regions (the middle one among the three second regions shown in FIG. 17 ), as shown in FIG. 17 shown.

In this embodiment, since the floating diffusion region 520 is partly located in one of the second regions, the upper surface of the floating diffusion region 520 is higher than the upper surface of the photodiode region 540, thereby preventing the floating diffusion region 520 from contacting the photodiode region. The diode region 540 has bulk capacitance to improve the performance of the back-illuminated image sensor.

Furthermore, the upper surface of the floating diffusion region 520 is higher than the upper surface of the photodiode region 540 by more than 30nm. At this time, the bulk capacitance between the floating diffusion region and the transfer transistor is greatly reduced, and the conversion efficiency of photoelectric charges is significantly improved.

In this embodiment, the upper surface of the channel region (that is, the second portion 4302) of the source follower transistor is higher than the upper surface of the semiconductor substrate corresponding to the photodiode region 540, so that there is a relatively small distance between the photodiode region 540 and the source follower transistor. Good isolation, the distance between the two can be reduced, so the size of the entire pixel unit can be reduced.

Further, the upper surface of the channel region of the source follower transistor is higher than the upper surface of the semiconductor substrate corresponding to the photodiode region 540 by more than 30 nm, so that the isolation between the photodiode region 540 and the source follower transistor is better.

Please continue to refer to FIG. 17 , the raised structure located on the far left in FIG. A dotted line separates them for distinction. Wherein, the first part has two side faces, and the second part 5102 has a top face and two side faces. The gate 511 covers the top surface and two side surfaces of the second part 5102 , in fact, there is the aforementioned gate dielectric layer between the gate 511 and the second part 5102 , which is not shown.

Since the gate 511 covers the top surface and two side surfaces of the second part 5102, the second part 5102 is the channel region of the reset transistor, and it can be seen that the reset transistor in this embodiment has a three-sided gate-enclosed structure. The structure can increase the physical width of the channel region of the reset transistor, thereby improving the performance of the reset transistor, such as reducing leakage current and shortening the physical length of the channel region, and reducing the feature size of the reset transistor.

It should be noted that, in other embodiments of the present invention, the gate of the reset transistor may only cover one side of the channel region of the reset transistor, or only cover two sides of the channel region of the reset transistor, or Only the top surface and one side surface of the channel region of the reset transistor are covered, which is not limited in the present invention.

Please continue to refer to FIG. 17, the protruding structure located on the far right in FIG. A dotted line separates them for distinction. Wherein, the first part has two sides, and the second part 5302 has a top surface and two sides. The gate 531 covers the top surface and two side surfaces of the second part 5302 , in fact, there is the aforementioned gate dielectric layer between the gate 531 and the second part 5302 , which is not shown.

Since the gate 531 covers the top surface and two side surfaces of the second part 5302, the second part 5302 is the channel region of the source follower transistor, and it can be known that the source follower transistor in this embodiment has a three-sided surrounding gate structure. The surrounding gate structure can increase the physical width of the channel region of the source-following transistor, so it can improve the performance of the source-following transistor, such as reducing the leakage current and shortening the physical length of the channel region, etc., and can reduce the feature size of the source-following transistor.

It should be noted that, in other embodiments of the present invention, the gate of the source-following transistor may only cover one side of the channel region of the source-following transistor, or only cover two sides of the channel region of the source-following transistor. side, or only cover the top surface and one side of the channel region of the source follower transistor, which is not limited in the present invention.

Please continue to refer to FIG. 17 , the gate layer is covered with a dielectric layer 560 , that is, the dielectric layer 560 covers the source follower transistor, the reset transistor and the transfer transistor. In this embodiment, the dielectric layer 560 may be silicon oxide, and the dielectric layer 560 may be formed by chemical vapor deposition.

Please refer to FIG. 18 , using chemical mechanical polishing to planarize the dielectric layer 560 to form a flat surface, then pattern the dielectric layer 560 to form an opening 503, and the opening 503 exposes the gate layer located in the non-gate region (that is, as shown in FIG. 18 gate layer 521 ); then using the dielectric layer 560 with the opening 503 as a mask, etch and remove the gate layer located in the non-gate region, that is, the gate layer 521 exposed by the opening 503 .

In this embodiment, the dielectric layer 560 can be patterned by using a photoresist patterning process to form the opening 503 , and the specific process is well known to those skilled in the art, and will not be repeated here.

In this embodiment, the material of the gate layer may be polysilicon, or metal, or a combination of polysilicon and metal. When the material of the gate layer 521 is polysilicon, the gate layer 521 covering the surface of the floating diffusion region may be removed by etching with a wet etching solution such as hot phosphoric acid solution.

It should be noted that in other embodiments of the present invention, each gate dielectric layer and each gate can also be formed in other ways. For example, the process of forming each gate dielectric layer and each gate can also be: Dummy gate dielectric layer; forming a third dielectric layer on the surface of the dummy gate dielectric layer; patterning the third dielectric layer to form a window, the window exposing the dummy gate dielectric layer in the gate region; removing the The dummy gate dielectric layer exposed by the window; after removing the dummy gate dielectric layer exposed by the window, forming the gate dielectric layer at the bottom of the window; forming the gate on the gate dielectric layer . Wherein, the gate dielectric layer filled in the window may be a gate dielectric layer of high dielectric material. The high dielectric material may be a dielectric material with a dielectric constant greater than 4. The gate filled in the window may include: a gate made of metal, a gate made of polysilicon, or a composite gate made of metal and polysilicon.

Referring to FIG. 19 , the dielectric layer 570 is filled in the opening 503 shown in FIG. 18 , and chemical mechanical polishing is used to form a flat surface for opening holes and laying metal layers. In FIG. 19 , the dielectric layer 560 shown in FIG. 18 is omitted, and the dielectric layer 560 and the dielectric layer 570 are shown as an integral structure, and the dielectric layer 570 is shown collectively.

In this embodiment, in the dielectric layer 570, the following can be performed: forming a plug 513 to connect to the gate 511 of the reset transistor; forming a plug 523 to connect to the floating diffusion region 520; forming a plug 551 to connect to the pinning layer 550; forming a plug 533 The gate 531 of the source follower transistor is connected. And the plug 513 , the plug 523 and the plug 533 are respectively connected to an external circuit, so as to control each transistor through the external circuit.

The method for forming the back-illuminated image sensor provided in this embodiment can flexibly adopt various processes, and the formed back-illuminated image sensor has good performance. For more content of this embodiment, reference may be made to the corresponding content of the foregoing embodiments of this specification.

Although the present invention is disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, so the protection scope of the present invention should be based on the scope defined in the claims.

Claims (28)

1. a back side illumination image sensor, it is characterised in that include multiple pixel cell, described pixel cell Including:

Semiconductor substrate, described Semiconductor substrate includes first area and at least one second area；

Photo-electric conversion element, is positioned in described first area, is used for receiving light to produce signal charge；

Floating diffusion region, part is positioned in a described second area, and part is positioned at described first area In, the upper surface of described second area is used higher than the upper surface of described first area, described floating diffusion region In collecting described signal charge to produce signal potential；

Transfering transistor, including the source electrode being positioned in described Semiconductor substrate and drain electrode, described source electrode and institute State drain electrode to electrically connect with described photo-electric conversion element and described floating diffusion region respectively, described transfering transistor Described floating diffusion region is transferred to for controlling described signal charge；

Transistor is followed in source, and including the grid being positioned in described Semiconductor substrate, described grid is floating with described Putting diffusion region electrical connection, transistor is followed for amplifying described signal potential in described source；

Reset transistor, including the drain electrode being positioned in described Semiconductor substrate, described drain electrode is floating with described Diffusion region electrically connects, and described reset transistor is for the current potential of the described floating diffusion region that resets；

Described second area is bulge-structure, including Part I and second be positioned on described Part I Part, described Part I has two sides, and described Part II has end face and two sides.

2. back side illumination image sensor as claimed in claim 1, it is characterised in that on described floating diffusion region Surface exceeds Semiconductor substrate more than the upper surface 30nm that described photo-electric conversion element is corresponding.

3. back side illumination image sensor as claimed in claim 1, it is characterised in that transistor is followed in described source Channel region upper surface exceed Semiconductor substrate upper surface 30nm corresponding to described photo-electric conversion element with On.

4. back side illumination image sensor as claimed in claim 1, it is characterised in that transistor is followed in described source Channel region be positioned at the described Part II of another described second area, transistor is followed in described source Grid covers the end face of described Part II and the one side at least within of two sides.

5. back side illumination image sensor as claimed in claim 4, it is characterised in that transistor is followed in described source Channel region there is channel doping district and non-channel doping district, described non-channel doping district is positioned at described ditch Road doped region and described source are followed between the grid of transistor.

6. back side illumination image sensor as claimed in claim 1, it is characterised in that described reset transistor Channel region is positioned at the described Part II of another described second area, the grid of described reset transistor Cover the end face of described Part II and the one side at least within of two sides.

7. the back side illumination image sensor as described in claim 4 or 6, it is characterised in that described quasiconductor serves as a contrast The end, has multiple described second area, and described Semiconductor substrate also has and is positioned at adjacent described second area Between isolation structure, described photo-electric conversion element is positioned in described isolation structure.

8. back side illumination image sensor as claimed in claim 7, it is characterised in that described transfering transistor Grid is positioned at described photo-electric conversion element and described isolation structure upper surface simultaneously.

9. back side illumination image sensor as claimed in claim 1, it is characterised in that described pixel cell also wraps Including: side wall, described side wall covers two sides of described Part I.

10. back side illumination image sensor as claimed in claim 1, it is characterised in that described photo-electric conversion element For photodiode.

The forming method of 11. 1 kinds of back side illumination image sensors, it is characterised in that including:

Thering is provided Semiconductor substrate, described Semiconductor substrate includes first area and at least one second area；

Photo-electric conversion element is formed in described first area；

Form source in described Semiconductor substrate and follow transistor, reset transistor and transfering transistor, described The source electrode of transfering transistor electrically connects described photo-electric conversion element；

Forming floating diffusion region in described Semiconductor substrate, described floating diffusion region part is positioned at an institute Stating in second area, part is positioned in described first area, and described second area upper surface is higher than described the One region upper surface；And described floating diffusion region electrical connection the drain electrode of described reset transistor, described turn The grid of transistor is followed in the drain electrode of shifting transistor and described source；

Described second area is bulge-structure, including Part I and second be positioned on described Part I Part, described Part I has two sides, and described Part II has end face and two sides.

The forming method of 12. back side illumination image sensors as claimed in claim 11, it is characterised in that described Floating diffusion region upper surface exceeds the Semiconductor substrate upper surface 30nm that described photo-electric conversion element is corresponding Above.

The forming method of 13. back side illumination image sensors as claimed in claim 11, it is characterised in that described source The channel region upper surface following transistor exceeds table in the Semiconductor substrate that described photo-electric conversion element is corresponding Face more than 30nm.

The forming method of 14. back side illumination image sensors as claimed in claim 11, it is characterised in that described source The channel region following transistor is formed at the described Part II of another described second area, described source The grid following transistor covers the end face of described Part II and the one side at least within of two sides.

The forming method of 15. back side illumination image sensors as claimed in claim 14, it is characterised in that described multiple The channel region of bit transistor is formed at the described Part II of another described second area, described reset The grid of transistor covers the end face of described Part II and the one side at least within of two sides.

The forming method of 16. back side illumination image sensors as claimed in claim 15, it is characterised in that form institute The process stating second area includes:

Multiple discrete shallow trench is formed at described semiconductor substrate surface, surplus between adjacent described shallow trench Remaining described Semiconductor substrate is described second area.

The forming method of 17. back side illumination image sensors as claimed in claim 16, it is characterised in that described The source that formed in Semiconductor substrate is followed transistor, reset transistor and transfering transistor and is included:

Described Semiconductor substrate being doped, being positioned at the well region in described Semiconductor substrate until being formed, Described well region includes described second area and the described first area of part；

The gate dielectric layer of transistor, reset transistor and transfering transistor is followed in the source that formed on described well region；

Described gate dielectric layer is formed described source and follows transistor, reset transistor and transfering transistor Grid；

Well region described to part is doped, until forming described source to follow transistor and reset transistor Source electrode and drain electrode.

The forming method of 18. back side illumination image sensors as claimed in claim 17, it is characterised in that formed After described shallow trench, and before forming described gate dielectric layer, described forming method also includes:

First medium layer is used to fill described shallow trench；

First medium layer described in etch-back, until remaining described first medium layer to form described first of covering Divide the side wall of side.

The forming method of 19. back side illumination image sensors as claimed in claim 18, it is characterised in that form institute State grid to include:

Grid layer is formed on described gate dielectric layer surface；

Photoresist is used to cover described grid layer；

Patterning described photoresist layer and form opening, described opening exposes the described grid being positioned at non-area of grid Pole layer；

With described photoresist layer as mask, the described grid layer exposed by described opening, residue are removed in etching Described grid layer is described grid.

The forming method of 20. back side illumination image sensors as claimed in claim 19, it is characterised in that formed Before described photo-electric conversion element, described method also includes:

Isolation structure is being formed in described first area；

When forming described photo-electric conversion element, described photo-electric conversion element is formed at described isolation structure In.

The forming method of 21. back side illumination image sensors as claimed in claim 20, it is characterised in that form institute The source of stating is followed the channel region of transistor and is included:

Described Part II carrying out channel doping and forms channel doping district, described Part II does not carries out institute The region stating channel doping is non-channel doping district, and described non-channel doping district is positioned at described channel doping district And between described grid.

The forming method of 22. back side illumination image sensors as claimed in claim 20, it is characterised in that formed During the grid of described transfering transistor, the grid of described transfering transistor is covered described photoelectricity simultaneously and turns Change element and described isolation structure upper surface.

The forming method of 23. back side illumination image sensors as claimed in claim 15, it is characterised in that described Two regions are epitaxially grown single-crystal semiconductor layer, and the process forming described second area includes:

Second dielectric layer is formed at described semiconductor substrate surface；

Pattern described second dielectric layer and form the groove exposing described Semiconductor substrate；

At single-crystal semiconductor layer described in the described semiconductor substrate surface epitaxial growth exposed by described groove.

The forming method of 24. back side illumination image sensors as claimed in claim 23, it is characterised in that described shape One-tenth method also includes:

Second dielectric layer described in etch-back, until remaining described second dielectric layer to form described first of covering Divide the side wall of side.

The forming method of 25. back side illumination image sensors as claimed in claim 17, it is characterised in that form institute The process stating gate dielectric layer and described grid includes:

Pseudo-gate dielectric layer is formed on described well region surface；

The 3rd dielectric layer is formed at dummy gate dielectric layer surface；

Patterning described 3rd dielectric layer and form window, described window exposes the described puppet being positioned at area of grid Gate dielectric layer；

Remove the dummy gate dielectric layer exposed by described window；

After removing the dummy gate dielectric layer exposed by described window, form institute at described bottom of window State gate dielectric layer；

Described gate dielectric layer is formed described grid.

The forming method of 26. back side illumination image sensors as claimed in claim 25, it is characterised in that described grid The material of dielectric layer is high dielectric material, the material of described grid include polysilicon, metal or both Combination.

The forming method of 27. back side illumination image sensors as claimed in claim 26, it is characterised in that described height Dielectric material refers to the material that dielectric constant is more than 4.

The forming method of 28. back side illumination image sensors as claimed in claim 11, it is characterised in that described light Electric transition element is photodiode.