CN103929131B - Doubler and signal frequency multiplication method - Google Patents

Abstract

The invention relates to a frequency multiplier and a signal frequency multiplication method. The frequency multiplier of the present invention includes: a first impedance module, a second impedance module, a first path and a second path. When the first path is turned on, the first impedance module generates a first output signal and the second impedance module generates a second output signal. When the second path is turned on, the first impedance module generates a third output signal and the second impedance module generates a fourth output signal. The first path and the second path are not conducted at the same time, and the frequency of a first composite signal obtained from the first and third output signals and the frequency of a second composite signal obtained from the second and fourth output signals are input N times the signal frequency, where N is a positive rational number.

Description

Frequency multiplier and signal frequency multiplication method

technical field

The invention relates to a frequency multiplier and a signal frequency multiplication method, in particular to a frequency multiplier and a signal frequency multiplication method capable of reducing power consumption.

Background technique

In the known technology, a frequency multiplier is usually used to increase the frequency of a signal. However, frequency multipliers usually only generate a single output signal, and additional circuits must be added to generate differential signals. Therefore, not only the consumption of electric energy will be increased, but also the area of the circuit will be increased.

Contents of the invention

Therefore, it is an object of the present invention to provide a frequency multiplier capable of generating differential signals without using additional circuits.

Another object of the present invention is to provide a signal frequency multiplication method capable of generating differential signals without using additional circuits.

An embodiment of the present invention discloses a frequency multiplier, comprising: a first output terminal; a second output terminal; a first impedance module, one end of which is coupled to a first predetermined potential, and the other end is coupled to the first predetermined potential An output end; a second impedance module, one end of which is coupled to a second predetermined potential, and the other end is coupled to the second output end; a first path, coupled to the first output end and the second output end and a second path, coupled between the first output terminal and the second output terminal; wherein the first path and the second path respectively receive an input signal and an inverted input signal, and the inverted The phase of the phase input signal is inverse to the input signal, and the first path and the second path are turned on or off depending on the input signal and the inverted input signal; when the first path is turned on, a first The current flows out from the first impedance module and flows through the first path to flow into the second impedance module, whereby the first impedance module generates a first output signal at the first output terminal and the second impedance module generates a first output signal at the first output terminal. The second output terminal generates a second output signal; wherein when the second path is turned on, a second current flows out from the first impedance module, flows through the second path and flows into the second impedance module, whereby the first impedance module An impedance module generates a third output signal at the first output end and the second impedance module generates a fourth output signal at the second output end; wherein the first path and the second path are not simultaneously conducted, and The frequency of a first composite signal composed of the first output signal and the third output signal and the frequency of a second composite signal composed of the second output signal and the fourth output signal are N times the frequency of the input signal , where N is a positive rational number.

An embodiment of the present invention discloses a signal frequency multiplication method, which is used in a frequency multiplier. The frequency multiplier includes a first path, a second path, a first impedance module, and a second impedance module. The signal frequency multiplication method includes: using the first path and the second path to respectively receive an input signal and An inverting input signal, the phase of the inverting input signal is inverse to the input signal, the first path and the second path are determined to be conductive or non-conductive by the input signal and the inverting input signal; A current flows out from the first impedance module and flows through the first path to flow into the second impedance module when the first path is turned on, so that the first impedance module generates a first output at the first output terminal signal and make the second impedance module generate a second output signal at the second output terminal; make a second current flow out from the first impedance module and flow through the first path to flow in when the second path is turned on The second impedance module, so that the first impedance module generates a third output signal at the first output end and makes the second impedance module generate a fourth output signal at the second output end; with the first output signal and the third output signal to synthesize a first composite signal; and synthesize a second composite signal with the second output signal and the fourth output signal; wherein the first path and the second path are not simultaneously turned on , and the frequencies of the first composite signal and the second composite signal are N times the frequency of the input signal, where N is a positive rational number.

By means of the aforementioned embodiments, the frequency-multiplied differential signal can be generated without additional circuits, which can reduce power consumption and circuit area.

Description of drawings

FIG. 1 illustrates a frequency multiplier according to an embodiment of the invention.

FIG. 2 illustrates an example of the detailed circuit of the frequency multiplier shown in FIG. 1 .

FIG. 3 is a schematic diagram illustrating the current of the frequency multiplier shown in FIG. 2 and the relationship among various signals.

4 to 6 illustrate other examples of detailed circuits of the frequency multiplier shown in FIG. 1 .

FIG. 7 illustrates a signal frequency multiplication method according to an embodiment of the present invention.

Description of main component symbols

100, 400, 500, 600 multiplier

101 First Path

103 Second Path

105 first impedance module

107 second impedance module

T _o1 first output terminal

T _o2 second output terminal

C, C1, C2 capacitance

L ₁ , L ₂ inductance

C _a1 , C _a2 variable capacitance

N _1st NMOSFET

N _2nd NMOSFET

P ₁ First PMOSFET

P2 _Second PMOSFET

T _1N1 , T _1N2 , T _1P1 , T _1P2 first end

T _2N1 , T _2N2 , T _2P1 , T _2P2 second terminal

T _CN1 , T _CN2 , T _CP1 , T _CP2 control terminals

T _c connection point

detailed description

FIG. 1 illustrates a frequency multiplier 100 according to an embodiment of the invention. As shown in FIG. 1 , the frequency multiplier 100 includes a first output terminal T _o1 , a second output terminal T _o2 , a first path 101 , a second path 103 , a first impedance module 105 and a second Impedance module 107 . Both the first path 101 and the second path 103 are coupled between the first output terminal T _o1 and the second output terminal T _o2 . The first path 101 and the second path 103 respectively receive an input signal V _in+ and an inverted input signal V _in− . The phase of the inverting input signal V _in- is inverse to that of the input signal V _in+ , and the first path 101 and the second path 103 are conducting or not conducting according to the input signal V _in+ and the inverting input signal V _in- . When the first path 101 is turned on, a first current _I1 flows out from the first impedance module 101 and flows through the first path 101 to flow into the second impedance module 107, whereby the first impedance module 101 is at the first output T _o1 A first output signal V _o1 is generated and the second impedance module V _o2 generates a second output signal V _o2 at the second output terminal T _o2 . When the second path 103 is turned on, a second current _I2 flows out from the first impedance module 105, flows through the second path 103 and flows into the second impedance module 107, whereby the first impedance module 105 is at the first output T _o1 A third output signal V _o3 is generated and the second impedance module 103 generates T _o2 at the second output terminal to generate a fourth output signal V _o4 . The first output signal V _o1 and the third output signal V _o3 are combined to generate a first composite signal V _c1 , and the second output signal V _o2 and the fourth output signal V _o4 are combined to generate a second composite signal V _c2 . Wherein the first path 101 and the second path 103 are not conducted at the same time, and the frequency of the first composite signal V _c1 and the frequency of the second composite signal V _c2 are N times the frequency of the input signal V _in+ or the inverted input signal V _in- , where N is a positive rational number.

FIG. 2 illustrates an example of the detailed circuit of the frequency multiplier shown in FIG. 1 , but is not intended to limit the present invention. As shown in FIG. 2 , the first path 101 of the frequency multiplier 100 includes a first NMOSFET (N type metal–oxide–semiconductor field-effect transistor) N ₁ and a first P NMOSFET (P type metal–oxide–semiconductor field- effect transistor) P ₁ . The second path 103 includes a second NMOSFET N ₂ and a second PMOSFET P ₂ . The first impedance module 105 includes an inductor L ₁ and a variable capacitor C _a1 , and the second impedance module 107 includes an inductor L ₂ and a variable capacitor C _a2 . The first NMOSFET N ₁ includes a first terminal T _1N1 , a second terminal T _2N1 and a control terminal T _CN1 . The first PMOSFET P ₁ includes a first terminal T _1P1 , a second terminal T _2P1 and a control terminal T _CP1 . The second NMOSFET N ₂ includes a first terminal T _1N2 , a second terminal T _2N2 and a control terminal T _CN2 . The second PMOSFET P ₂ includes a first terminal T _1P2 , a second terminal T _2P2 and a control terminal T _CP2 . The connection relationship among the components has been shown in detail in FIG. 2 , so it will not be repeated here. Please note that NMOSFET and PMOSFET can also be replaced by other types of transistors.

FIG. 3 is a schematic diagram illustrating the current of the frequency multiplier shown in FIG. 2 and the relationship among various signals. Please refer to FIG. 2 and FIG. 3 cross-referenced to understand the operation mode of the frequency multiplier shown in FIG. 2 . The control terminal T _CN1 of the first NMOSFET N ₁ and the control terminal T _CP1 of the first PMOSFET P ₁ of the first path 101 respectively receive the input signal V _in+ and the inverting input signal V _in− . Therefore, the first path 101 is turned on when the input signal V _in+ is at a high level and the inverted input signal V _in− is at a low level (periods T ₁ and T 3 in FIG. ₃ ). The control terminal T _CN2 of the second NMOSFET N ₂ and the control terminal T _CP2 of the second PMOSFET P ₂ of the second path 103 respectively receive the inverting input signal V _in− and the input signal V _in+ . Therefore, the second path 103 is turned on when the input signal V _in+ is at a low level and the inverted input signal V _in− is at a high level (periods T ₂ and T ₄ in FIG. 3 ). When the first path 101 is turned on, because the first impedance module 105 and the second impedance module 107 have inductances L1 and L2, the _first output signal V _o1 and the _second output signal V o1 as shown in Figure 3 will resonate Signal V _o2 . Similarly, when the second path 103 is turned on, because the _first impedance module 105 and the second impedance module 107 have inductances L1 and L2, the third output signal V _o3 as shown in FIG. ₃ will resonate and the fourth output signal V _o4 . Through the aforementioned actions, the first composite signal T _c1 is generated at the first output terminal T ₁ , and the second composite signal T _c2 is generated at the second output terminal T ₂ . The first composite signal T _c1 is synthesized by the first output signal V _o1 and the third output signal V _o3 , and the second composite signal T _c2 is synthesized by the second output signal V _o2 and the fourth output signal V _o4 .

In this embodiment, since the first composite signal T _c1 and the second composite signal T _c2 are generated according to the resonance of the input signal V _in+ and the inverted input signal V _in- , the first composite signal T _c1 and the second composite signal The frequency of T _c2 and the frequencies of the input signal V _in+ and the inverting input signal V _in− will have a multiple relationship. In this example, the frequency of the first composite signal T _c1 and the second composite signal T _c2 is twice the frequency of the input signal V _in+ and the inverted input signal V _in− , but it is not limited thereto. By adjusting the inductance or capacitance in the first impedance module 105 and the second impedance module 107, the relationship between the two frequencies can be adjusted. That is to say, the frequency of the first composite signal T _c1 and the second composite signal T _c2 is N times the frequency of the input signal V _in+ and the inverted input signal V _in− , and N can be a positive rational number.

4 to 6 illustrate other examples of detailed circuits of the frequency multiplier shown in FIG. 1 . In FIG. 4 , the frequency multiplier 400 also includes capacitors C ₁ and C ₂ . One end of the capacitor C ₁ is coupled to the second end T _2N1 of the first NMOSFET N ₁ , and the other end is coupled to the ground potential. One end of the capacitor C ₂ is coupled to the second end T _2N2 of the second NMOSFET N ₂ , and the other end is coupled to the ground potential. With such a structure, noise can be reduced and the current can be more stable. Please refer to FIG. 2 again. In FIG. 2, the second terminals T _2N1 and T _2N2 of the first NMOSFET N ₁ and the second NMOSFET N ₂ are not coupled to each other, and the first PMOSFET P ₁ and the second terminals of the second PMOSFET P ₂ The two terminals T _2P1 and T _2P2 are not coupled to each other. However, in the embodiment of FIG. 5 , the second terminals T _2N1 and T _2N2 of the first NMOSFET N ₁ and the second NMOSFET N ₂ of the frequency multiplier 500 and the second terminals of the first PMOSFET P ₁ and the second PMOSFET P ₂ Terminals T _2P1 , T _{2P2 are} coupled to the same connection point T _c . With the structure of FIG. 5 , the circuit design can be made easier. In the embodiment of FIG. 6 , the frequency multiplier 600 further includes a capacitor C, one end of which is coupled to the connection point Tc and the other end is coupled to the ground potential. With such a structure, noise can be reduced and the current can be more stable.

According to the foregoing embodiments, a signal frequency multiplication method can be obtained, as shown in FIG. 7 , which includes the following steps:

Step 701

An input signal Vin+ and an inverted input signal Vin− are respectively received through the first path 101 and the second path 103 . The phase of the inverted input signal Vin- is inverted from that of the input signal Vin+, and the first path 101 and the second path 103 are turned on or off depending on the input signal Vin+ and the inverted input signal Vin-.

Step 703

Make a first current I ₁ flow out from the first impedance module 105 and flow through the first path 101 to flow into the second impedance module 107 when the first path 101 is turned on, so that the first impedance module 105 is at the first output terminal T _o1 generates a first output signal Vo1 and enables the second impedance module 107 to generate a second output signal V _{o2 at the second output terminal T o2 .}

Step 705

Make a second current I ₂ flow out from the first impedance module 105 and flow through the second path 103 to flow into the second impedance module 107 when the second path 103 is turned on, so that the first impedance module 105 is at the first output terminal T _o1 generates a third output signal V _o3 and enables the second impedance module 107 to generate a fourth output signal V _o4 at the second output terminal T _o2 .

Step 707

A first composite signal V _c1 is synthesized with the first output signal V _o1 and the third output signal V _o3 .

Step 709

A second composite signal V _c2 is synthesized by the second output signal V _o2 and the fourth output signal V _o4 .

The first path 101 and the second path 103 are not turned on at the same time, and the frequencies of the first composite signal V _c1 and the second composite signal V _c2 are N times the frequency of the input signal, where N is a positive rational number.

The aforementioned first composite signal V _c1 and second composite signal V _c2 can form a differential signal, but can also be regarded as two separate signals. Therefore, the aforementioned frequency multiplier can be regarded as a frequency multiplier generating a differential signal, but it can also be regarded as a frequency multiplier generating two separate signals.

By means of the aforementioned embodiments, the frequency-multiplied differential signal can be generated without additional circuits, which can reduce power consumption and circuit area.

The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the scope of the patent application of the present invention shall fall within the scope of the present invention.

Claims (7)

1. a doubler, comprises:

One first outfan；

One second outfan；

One first impedance module, its one end couples one first predetermined potential, and the other end is coupled to this first outfan；

One second impedance module, its one end couples one second predetermined potential, and the other end is coupled to this second outfan；

One first path, is coupled between this first outfan and this second outfan；And

One second path, is coupled between this first outfan and this second outfan；

Wherein this first path and this second path receive an input signal and a rp input signal respectively, and this is anti-phase defeated Entering the phase place of signal and this input signal is anti-phase, this first path and this second path are by this input signal and this is anti-phase defeated Enter signal deciding conducting or be not turned on；When this first path turns on, one first electric current flows out from this first impedance module and flows Through this first path to flow into this second impedance module, thereby this first impedance module is defeated in the generation one first of this first outfan Go out signal and this second impedance module and produce one second output signal at this second outfan；When this second path turns on, one Second electric current flows out and flows through this second path and flows into this second impedance module from this first impedance module, thereby this first resistance Anti-module produces one the 3rd output signal and this second impedance module at this first outfan and produces one the at this second outfan Four output signals；

Wherein this first path does not simultaneously turns on this second path, and this first output signal synthesizes with the 3rd output signal The one second synthesis letter that the frequency of one first composite signal gone out and the second output signal synthesize with the 4th output signal Number N times of the frequency that frequency is this input signal, wherein N is a positive rational number；

Described doubler also comprises:

One first electric capacity, one end is coupled to this first path, and the other end couples an earth potential；And

One second electric capacity, one end is coupled to this second path, and the other end couples an earth potential；

Or described doubler also comprises:

One electric capacity, one end is coupled to this first path and this second path, and the other end is coupled to an earth potential.

2. doubler as claimed in claim 1, it is characterised in that this first path comprises:

One first kind one transistor, has one first end coupling this first outfan, and has one second end and reception One control end of this input signal；And

One first kind two-transistor, has one first end of this second end coupling this first kind one transistor, couples this One second end of the second outfan, and receive a control end of this rp input signal；

Wherein this second path comprises:

One Second Type one transistor, has one first end coupling this first outfan, and has one second end and reception One control end of this rp input signal；And

One Second Type two-transistor, has one first end of this second end coupling this Second Type one transistor, couples this One second end of the second outfan, and receive a control end of this input signal.

3. doubler as claimed in claim 2, it is characterised in that this second end of this first kind one transistor and should This second end of Second Type one transistor is not coupled against each other, and this first end of this first kind two-transistor and this second This first end of type two-transistor is not coupled against each other.

4. doubler as claimed in claim 3, it is characterised in that

This first electric capacity, one end is coupled to this second end of this first kind one transistor, and the other end couples an earth potential；And

This second electric capacity, one end is coupled to this second end of this Second Type one transistor, and the other end couples an earth potential.

5. doubler as claimed in claim 2, it is characterised in that this second end of this first kind one transistor, this is second years old This second end of type one transistor, this first end of this first kind two-transistor, and this Second Type two-transistor This first end is coupled to same junction point.

6. doubler as claimed in claim 5, it is characterised in that:

This electric capacity, one end is coupled to this junction point, and the other end is coupled to an earth potential.

7. doubler as claimed in claim 1, it is characterised in that this first impedance module comprises at least one inductance element, uses With this first output signal or the 3rd output signal of resonating out, this second impedance module comprises at least one inductance element, in order to Resonate out this second output signal or the 4th output signal.