CN103922267A - Inertial sensor production and wafer level package process based on MEMS (micro-electromechanical system) - Google Patents
Inertial sensor production and wafer level package process based on MEMS (micro-electromechanical system) Download PDFInfo
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- CN103922267A CN103922267A CN201310009174.XA CN201310009174A CN103922267A CN 103922267 A CN103922267 A CN 103922267A CN 201310009174 A CN201310009174 A CN 201310009174A CN 103922267 A CN103922267 A CN 103922267A
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- 238000004519 manufacturing process Methods 0.000 title abstract description 12
- 229910052751 metal Inorganic materials 0.000 claims abstract description 47
- 239000002184 metal Substances 0.000 claims abstract description 47
- 239000010703 silicon Substances 0.000 claims abstract description 19
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 19
- 238000004806 packaging method and process Methods 0.000 claims abstract description 10
- 238000013461 design Methods 0.000 claims abstract description 9
- 230000005496 eutectics Effects 0.000 claims abstract description 9
- 238000000206 photolithography Methods 0.000 claims description 36
- 238000005516 engineering process Methods 0.000 claims description 21
- 238000001259 photo etching Methods 0.000 claims description 21
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 18
- 229910052732 germanium Inorganic materials 0.000 claims description 15
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 15
- 238000004544 sputter deposition Methods 0.000 claims description 12
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical group [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 10
- 229910052782 aluminium Inorganic materials 0.000 claims description 9
- 238000005530 etching Methods 0.000 claims description 9
- 238000012536 packaging technology Methods 0.000 claims description 9
- 238000002360 preparation method Methods 0.000 claims description 9
- 239000004593 Epoxy Substances 0.000 claims description 6
- 239000004642 Polyimide Substances 0.000 claims description 6
- 239000004411 aluminium Substances 0.000 claims description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 6
- 238000000708 deep reactive-ion etching Methods 0.000 claims description 6
- 239000003822 epoxy resin Substances 0.000 claims description 6
- 229920000647 polyepoxide Polymers 0.000 claims description 6
- 229920001721 polyimide Polymers 0.000 claims description 6
- 238000005538 encapsulation Methods 0.000 claims description 5
- 238000012545 processing Methods 0.000 claims description 5
- 238000013459 approach Methods 0.000 claims description 3
- 238000005229 chemical vapour deposition Methods 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 3
- 230000008021 deposition Effects 0.000 claims description 3
- 229910052737 gold Inorganic materials 0.000 claims description 3
- 239000010931 gold Substances 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
- 238000012856 packing Methods 0.000 claims description 3
- 238000001020 plasma etching Methods 0.000 claims description 3
- 238000005498 polishing Methods 0.000 claims description 3
- 238000001039 wet etching Methods 0.000 claims description 3
- 239000012212 insulator Substances 0.000 abstract 1
- 238000003754 machining Methods 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 2
- ROXBGBWUWZTYLZ-UHFFFAOYSA-N [6-[[10-formyl-5,14-dihydroxy-13-methyl-17-(5-oxo-2h-furan-3-yl)-2,3,4,6,7,8,9,11,12,15,16,17-dodecahydro-1h-cyclopenta[a]phenanthren-3-yl]oxy]-4-methoxy-2-methyloxan-3-yl] 4-[2-(4-azido-3-iodophenyl)ethylamino]-4-oxobutanoate Chemical compound O1C(C)C(OC(=O)CCC(=O)NCCC=2C=C(I)C(N=[N+]=[N-])=CC=2)C(OC)CC1OC(CC1(O)CCC2C3(O)CC4)CCC1(C=O)C2CCC3(C)C4C1=CC(=O)OC1 ROXBGBWUWZTYLZ-UHFFFAOYSA-N 0.000 description 1
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Abstract
The invention discloses an inertial sensor production and wafer level package process based on an MEMS (micro-electromechanical system). The process includes the steps: 1) forming an E-SOI (engineering-silicon on insulator); 2) performing surface machining on an MEMS wafer; 3) producing an ASIC (application specific integrated circuit) wafer on a standard ASIC foundry; 4) performing metal eutectic bonding for the MEMS wafer and the ASIC wafer; 5) performing WLCSP (wafer level chip size packaging). The area of an ASIC chip is identical with that of an MEMS chip, the effective areas of the MEMS chip and the ASIC chip are sufficiently used, the most effective space is provided for the design of the MEMS chip and the ASIC chip, subsequent package procedures of the chips are omitted by the aid of the wafer level chip size packaging, Flip-Chip of a terminal circuit board is finished directly through a BGA (ball grid array), and the sizes of the chips and production cost are greatly reduced.
Description
Technical field
The present invention relates to MEMS(MEMS) production running inertia sensor, comprise gyroscope and accelerator, relate in particular to a kind of based on MEMS(MEMS) inertial sensor produce and wafer-level packaging technique.
Background technology
In the last few years, the inertial sensor such as gyroscope obtained applying more and more widely in fields such as automobile, smart mobile phone, panel computer, toy helicopter, air mouse.Gyroscope and the accelerometer based on MEMS, produced are current main products, and the design of chip and the processing of wafer are two committed steps that inertial sensor is manufactured.
And existing inertial sensor on packaged chip and wafer, exist following several shortcoming (U.S. Patent number 7,104,129B2):
(1), due to must be with scribing process cut-out MEMS(MEMS) thereby area exposing metal district is used for package lead, part MEMS area is wasted.For consumer product, the loss of area can reach 10 left and right.Its negative effect has two aspects: A.MEMS chip and ASIC(special IC) chip do not mate (area that the area of MEMS chip is less than the chip of ASIC), limited the design space of MEMS structure; B. due to the Partial Resection of chip, cause the corresponding raising of production cost;
(2), ASIC circuit face and MEMS structural plane key and be integrated, cause ASIC circuit face part area can not be used as circuit, and for the groove of MEMS structure, the corresponding raising that this has limited equally the design space of ASIC and has caused chip production cost;
(3), ASIC circuit face is that packaged wafer can not be done wafer level chip scale packaging technology (WLCSP) and inverse bonding chip package (Flip-Chip) towards the another one shortcoming of MEMS;
(4), owing to connecting technique as package lead with wire, the performance of device is had to certain influence.
Summary of the invention
The object of the invention is to solve in prior art the waste of MEMS area, ASIC design space restricted with and production cost high, the problems such as chip size is large, provide a kind of inertial sensor based on MEMS to produce and wafer-level packaging technique, chip size can be dropped to 2-4 square millimeter, production cost can lower 30-40% with traditional handicraft ratio.
Technical scheme of the present invention is: a kind of based on the production of MEMS inertial sensor and wafer-level packaging technique, its step is as follows:
1) SOI of through engineering approaches forms:
A, first with silicon holder lining wafer (handle wafer) < < 5 > >, back etched location alignment mark (the first reticle), then at front wafer surface using plasma technique etching groove (the second photolithography plate) < < 1 > >; By the thermal oxidation technology layer oxide film < < 7 > > that grow; Yong Gui Rong bonding technology is integrated with other a slice micro electro mechanical device wafer (MEMS device wafer) < < 4 > > bondings;
B, at micro electro mechanical device wafer face, be ground to ideal thickness; See Fig. 2.
2) with plasma etch process, on micro electro mechanical device wafer, form and enclose ditch (the 3rd photolithography plate), then vapour deposition one deck germanium or silicon < < 6 > > are for later wafer bonding, to germanium or the thin Mo of silicon with enclose that ditch is corresponding makes litho pattern (the 4th photolithography plate) and plasma etching removes unwanted germanium, finally by DRIE technique, complete the etching (the 5th photolithography plate) of MEMS structure; See Fig. 3.
3) at standard A SIC band plant produced ASIC wafer < < 2 > >; < < 3 > > are scolding tin positions (bondpads) of ASIC face.Then on this wafer, carry out following processing technology: (Fig. 4)
A, at the positive photoetching silicon through hole (the 6th photolithography plate) of the ASIC that is having circuit, with the enough dark groove of DRIE technique etching, its degree of depth is 100-150 micron, according to standard TSV operation, groove is carried out to oxide, the filling < < 8 > > of metal, and the polishing of CMP, ASIC wafer rear is ground to the thickness of 100-150 micron, then polishes wafer surface (back side of ASIC face) by CMP technique;
B, with sputtering technology growth layer of metal layer < < 9 > >; Metal level < < 9 > > are carried out to photoetching cabling design producing (the 7th photolithography plate) and wet method metal etch, with the long one deck oxide of chemical vapor deposition method < < 10 > >, its thickness is 5-6 times of metal level < < 9 > >;
C, further photoetching oxide pattern (the 8th photolithography plate) exposing metal layer < < 9 > >, for metal level < < 11 > > prepare, first with sputtering technology growth layer of metal layer < < 11 > >, its thickness is about 3-4 times of < < 9 > >, metal level < < 11 > > are carried out to photoetching wiring (the 9th photolithography plate), make metal level < < 11 > > and micro electro mechanical device wafer < < 6 > > carry out metal eutectic bonding,
D, final step operation are photoengraving pattern preparations and with plasma process etched trench < < 12 > > (the tenth photolithography plate); See Fig. 4.
4) MEMS wafer and ASIC wafer germanium/aluminium, silicon/aluminium or germanium/gold, silicon/metal eutectic bonding, this technique is carried out under vacuum, and the pressure of last gyroscope groove inner chamber body should not be greater than 0.50-0.75Torr; See Fig. 5.
So far, wafer can carry out scribing (wafer dicing), carry out again wafer-level package (CSP-Chip scalepackaging), such as the packing forms with LGA or QFN, the present invention proposes with wafer level chip scale packaging technology (WLCSP) and follow-up inverse bonding chip (Flip-Chip) encapsulation; Fig. 6 has illustrated the structure chart of last chip.
5) wafer level chip scale packaging technology
A, at the ASIC face of the good wafer of bonding, form one deck polyimides (polyimide-PI) or epoxy resin (Epoxy) < < 13 > >; B, with photoetching process preparation, open the pattern (the 11 photolithography plate) of pad; With sputtering technology (Sputtering) growth layer of metal (Al or Cu) < < 14 > >;
C, with photoetching process preparation layer (RDL) (the 12 photolithography plate) that reroute; With dry method or wet etching process, prepare the metal layer that reroutes;
D, form one deck polyimides (polyimide-PI) or epoxy resin (Epoxy) < < 15 > > again.
E, by photoetching process, prepare tin ball BGA pattern (the 13 photolithography plate); Finally form UBM < < 16 > > and BGA tin ball < < 17 > >.
What time following the beneficial effect that technical solution of the present invention is brought is:
(1) owing to having adopted TSV technique, asic chip area is identical with MEMS chip area, thereby can make full use of the effective area of MEMS chip and asic chip, for the design of MEMS and asic chip provides the most effective space;
(2) because MEMS and asic chip area fully the most effectively utilize, production cost can significantly be reduced, and estimates in 30-40% left and right;
(3) use TSV technique that circuit lead is directly drawn, further improved the performance of device;
(4) by ASIC circuit face outwardly, packaged wafer can further be done chip wafer scale packaging technology and surface-mounted technology in the present invention, goes for widely encapsulation field and further reduces production costs.
(5) simultaneously due to AISC chip and MEMS chip are carried out to wafer-level packaging, saved the follow-up packaging technology of chip.Encapsulation, the paster technique of terminal client circuit board directly by BGA, have been encapsulated.Make like this production and the testing cost of product significantly reduce, chip size is obviously dwindled.
Accompanying drawing explanation
Fig. 1 is the cross section that the present invention processes MEMS inertial sensor device;
Fig. 2 is for being used this process engineeringization SOI (E-SOI) to form schematic diagram;
Fig. 3 is for being used this technique MEMS structure to form schematic diagram;
Fig. 4 is the schematic diagram with plant produced ASIC wafer processing TSV and metal line at ASIC;
Fig. 5 is for being used this technique chip metal eutectic bonding schematic diagram;
Fig. 6 is the tin ball structure schematic diagram of layer (RDL) and spherical point contacts array (BGA) of rerouting after chip metal eutectic bonding.
The specific embodiment
For technological means, technical characterictic, goal of the invention and the technique effect that the present invention is realized is easy to understand, below in conjunction with concrete diagram, further set forth the present invention.
Based on MEMS inertial sensor, produce and a wafer-level packaging technique, see Fig. 1, its step is as follows:
1) SOI of through engineering approaches forms (E-SOI):
A, first with silicon holder lining wafer (handle wafer) < < 5 > >, back etched location alignment mark (the first reticle), then at wafer frontside using plasma technique etching groove < < 1 > > (the second photolithography plate); By the thermal oxidation technology layer oxide film < < 7 > > that grow; Yong Gui Rong bonding technology is integrated with other a slice micro electro mechanical device wafer (Device wafer) < < 4 > > bondings;
B, at micro electro mechanical device wafer face, be ground to ideal thickness, as shown in Figure 2;
2) with plasma etch process, on micro electro mechanical device wafer, form and enclose ditch (the 3rd photolithography plate), then vapour deposition one deck germanium or silicon < < 6 > > are for later wafer bonding, to germanium or the thin Mo of silicon with enclose that ditch is corresponding makes litho pattern (the 4th photolithography plate) and plasma etching removes unwanted germanium, finally by DRIE technique, complete the etching (the 5th photolithography plate) of MEMS structure, as shown in Figure 3;
3) at standard A SIC band plant produced ASIC wafer 2.< < 3 > > are scolding tin positions (bondpads) of ASIC face.Then on this wafer, carry out following processing technology as shown in Figure 4:
A, at the positive photoetching silicon through hole (the 6th photolithography plate) of the ASIC that is having circuit, with the enough dark groove of DRIE technique etching, its degree of depth is 100-150 micron, according to standard TSV operation, groove is carried out to oxide, the filling < < 8 > > of metal, and the polishing of CMP, ASIC wafer rear is ground to the thickness of 100-150 micron, then polishes wafer surface (back side of ASIC face) by CMP technique;
B, with sputtering technology growth layer of metal layer < < 9 > >.Metal level < < 9 > > are carried out to photoetching cabling design producing (the 7th photolithography plate) and wet method metal etch, with the long one deck oxide of chemical vapor deposition method < < 10 > >, its thickness is 5-6 times of metal level < < 9 > >;
C, further photoetching oxide pattern (the 8th photolithography plate) exposing metal layer < < 9 > >, for metal level < < 11 > > prepare, the 3-4 that is first about < < 9 > > with sputtering technology growth layer of metal layer < < 11 its thickness of > > doubly, metal level < < 11 > > are carried out to photoetching wiring (the 9th photolithography plate), make metal level < < 11 > > and micro electro mechanical device wafer < < 6 > > carry out metal eutectic bonding,
D, final step operation are photoengraving pattern preparations and with plasma process etched trench < < 12 > > (the tenth photolithography plate), as shown in Figure 4;
4) MEMS wafer and ASIC wafer germanium/aluminium, silicon/aluminium or germanium/gold, silicon/metal eutectic bonding, this technique is carried out under vacuum, and the pressure of last gyroscope groove inner chamber body should not be greater than 0.50-0.75Torr; See Fig. 5.
So far, wafer can carry out scribing (wafer dicing), carry out again wafer-level package (CSP-Chip scalepackaging), such as the packing forms with LGA or QFN, the present invention proposes with wafer level chip scale packaging technology (WLCSP) and the encapsulation of follow-up inverse bonding chip (Flip-Chip), and Fig. 6 has illustrated last chip structure figure;
5) wafer level chip scale packaging technology
A, at the ASIC face of the good wafer of bonding, form one deck polyimides (polyimide-PI) or epoxy resin (Epoxy) < < 13 > >; B, with photoetching process preparation, open the pattern (the 11 photolithography plate) of pad < < 3 > >; With sputtering technology (Sputtering) growth layer of metal < < 14 > > (Al or Cu);
C, with photoetching process preparation layer (RDL) (the 12 photolithography plate) that reroute; With dry method or wet etching process, prepare the metal layer that reroutes;
D, form one deck polyimides (polyimide-PI) or epoxy resin (Epoxy) < < 15 > > again;
E, by photoetching process, prepare tin ball BGA pattern (the 13 photolithography plate); Finally form UBM < < 16 > > and BGA tin ball < < 17 > >.
Be only preferred embodiment of the present invention in sum, be not used for limiting practical range of the present invention.Be that all equivalences of doing according to the content of the present patent application the scope of the claims change and modify, all should belong to technology category of the present invention.
Claims (1)
1. based on MEMS inertial sensor, produce and a wafer-level packaging technique, its step is as follows:
1) SOI of through engineering approaches forms (Engineered-SOI wafer):
A, first with silicon holder lining wafer (handle wafer) < < 5 > >, back etched location alignment mark (the first reticle), then at front wafer surface using plasma technique etching groove < < 1 > > (the second photolithography plate); By the thermal oxidation technology layer oxide film < < 7 > > that grow; Yong Gui Rong bonding technology is integrated with other a slice micro electro mechanical device wafer (MEMS device wafer) < < 4 > > bondings;
B, at micro electro mechanical device wafer face, be ground to ideal thickness;
2) with plasma etch process, on micro electro mechanical device wafer, form and enclose ditch (the 3rd photolithography plate), then vapour deposition one deck germanium or silicon < < 6 > > are for later wafer bonding, to germanium or the thin Mo of silicon with enclose that ditch is corresponding makes litho pattern (the 4th photolithography plate) and plasma etching removes unwanted germanium, finally by DRIE technique, complete the etching (the 5th photolithography plate) of MEMS structure;
3) at standard A SIC band plant produced ASIC wafer < < 2 > >; < < 3 > > are scolding tin positions (bondpads) of ASIC face; Then on this wafer, carry out following processing technology:
A, at the positive photoetching silicon through hole (TSV) (the 6th photolithography plate) of the ASIC that is having circuit, with the enough dark groove of DRIE technique etching, its degree of depth is 100-150 micron, according to standard TSV operation, groove is carried out to oxide, the filling < < 8 > > of metal, and the polishing of CMP, ASIC wafer rear is ground to the thickness of 100-150 micron, then polishes wafer surface (back side of ASIC face) by CMP technique;
B, with sputtering technology growth layer of metal layer < < 9 > >; Metal < < 9 > > are carried out to photoetching cabling design producing (the 7th photolithography plate) and wet method metal etch, with the long one deck oxide of chemical vapor deposition method < < 10 > >, its thickness is 5-6 times of metal level < < 9 > >;
C, further photoetching oxide pattern (the 8th photolithography plate) exposing metal layer < < 9 > >, for metal level < < 11 > > prepare, first with sputtering technology growth layer of metal layer < < 11 > >, its thickness is about 3-4 times of < < 9 > >, metal level < < 11 > > are carried out to photoetching wiring (the 9th photolithography plate), make metal level < < 11 > > and micro electro mechanical device wafer < < 6 > > carry out metal eutectic bonding,
D, final step operation are photoengraving pattern preparations and with plasma process etched trench < < 12 > > (the tenth photolithography plate);
4) MEMS wafer and ASIC wafer germanium/aluminium, silicon/aluminium or germanium/gold, silicon/metal eutectic bonding, this technique is carried out under vacuum, and the pressure of last gyroscope groove inner chamber body should not be greater than 0.50-0.75Torr;
Everywhere, wafer can carry out scribing (wafer dicing) and wafer-level package (CSP-chip scale packaging).Packing forms such as LGA or QFN.The present invention proposes with wafer level chip scale packaging technology (WLCSP) and follow-up inverse bonding encapsulation (Flip-Chip);
5) wafer level chip scale packaging technology (WLCSP)
A, at the ASIC face of the good wafer of bonding, form one deck polyimides (polyimide-PI) or epoxy resin (Epoxy) < < 13 > >;
B, with photoetching process preparation, open the pattern (the 11 photolithography plate) of pad; With sputtering technology (Sputtering) growth layer of metal (Al or Cu) < < 14 > >;
C, with photoetching process preparation layer (RDL) (the 12 photolithography plate) that reroute; With dry method or wet etching process, prepare the metal layer < < 14 > > that reroute;
D, form one deck polyimides (polyimide-PI) or epoxy resin (Epoxy) < < 15 > > again;
E, by photoetching process, prepare tin ball BGA pattern (the 13 photolithography plate); Finally form UBM < < 16 > > and BGA tin ball < < 17 > >.
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| CN104692319A (en) * | 2015-03-16 | 2015-06-10 | 安徽北方芯动联科微系统技术有限公司 | Manufacturing method of MEMS chip insensitive to packaging stress and MEMS chip |
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| CN105621348A (en) * | 2015-12-29 | 2016-06-01 | 苏州工业园区纳米产业技术研究院有限公司 | MEMS inertial sensor device and preparation method thereof |
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