CN103944571B - High-speed configurable assembly line analog-to-digital converter - Google Patents

Abstract

The present invention provides a high-speed configurable pipeline analog-to-digital converter, comprising: a first-level circuit, a second-level circuit, a third-level circuit, a fourth-level circuit, a fifth-level circuit, a sixth-level circuit, and a first-level circuit connected in sequence. The seven-level circuit, the eighth-level circuit, the ninth-level circuit, the tenth-level circuit, and a two-bit flash analog-to-digital sub-converter; a redundant calibration circuit connected to the above-mentioned levels of circuits; the first-level circuit passes through the first The switch is connected to the redundant calibration circuit; the second level circuit is connected to the redundant calibration circuit through the second switch; when both the first switch and the second switch are closed, the first level circuit to the tenth level circuit and the flash modulus sub All the converters work to realize the working mode of the first frequency; when both the first switch and the second switch are turned off, the first-stage circuit and the second circuit are disconnected, and the third-stage circuit to the tenth-stage circuit and the flash mode The digital converter works to realize the working mode of the second frequency. The invention has the advantages of high speed, adjustable sampling rate, configurable and optional number of digits.

Description

A High-Speed Configurable Pipelined Analog-to-Digital Converter

technical field

The invention relates to the field of integrated circuits, in particular to a high-speed configurable pipeline analog-to-digital converter. Background technique

With the rapid development of wireless communication technology, the coexistence of multiple protocol standards has become inevitable. Since different protocol standards have different requirements for transmission speed and transmission quality, there are also differences in the frequency range, bandwidth, and dynamic range of input signals that they allow. Therefore, for multi-standard terminal equipment, it requires AD (analog-to-digital) converters with different resolutions and different sampling rates.

In order to realize an analog-to-digital converter with variable resolution and sampling rate, there are currently two traditional solutions in the industry: The first solution is to integrate several dedicated ADCs (analog-to-digital converters) in parallel, one for each communication protocol ADC, the advantage of this solution is low power consumption. When one ADC is working, the other ADCs are turned off. Each protocol has an optimized dedicated ADC. The disadvantage is that the area is large, the development cycle is long, and the development of various dedicated ADCs requires a lot of investment.

The second option is to use a unified ADC. This general-purpose ADC is designed for worst-case scenarios across all communication protocols. The advantages of this solution are small area and low cost. For different communication protocols, they all rely on an ADC to solve the problem. The disadvantage is that the performance is excessive, and it consumes too much energy under multiple protocols, and for a wide range of performance requirements. Technically difficult to achieve.

In view of the above reasons, a configurable A/D converter with low area, low power consumption and avoiding excess performance becomes a demand.

Contents of the invention

The technical problem to be solved by the present invention is to provide an analog-to-digital converter with high speed, adjustable sampling rate, configurable and optional bits.

In order to solve the above technical problems, an embodiment of the present invention provides a high-speed configurable pipeline analog-to-digital converter, including:

The first level circuit, the second level circuit, the third level circuit, the fourth level circuit, the fifth level circuit, the sixth level circuit, the seventh level circuit, the eighth level circuit, the ninth level circuit, the tenth level circuit connected in sequence stage circuit and a two-bit flash analog-to-digital sub-converter;

and the first level circuit, the second level circuit, the third level circuit, the fourth level circuit, the fifth level circuit, the sixth level circuit, the seventh level circuit, the eighth level circuit, the ninth level circuit, the tenth level circuit stage circuit and a redundant calibration circuit connected to a two-bit flash analog-to-digital sub-converter;

Wherein, the first stage circuit is connected to the redundant calibration circuit through a first switch; the second stage circuit is connected to the redundant calibration circuit through a second switch;

When both the first switch and the second switch are closed, all the circuits from the first stage to the tenth stage and the flash analog-to-digital sub-converter work to realize the working mode of the first frequency;

When both the first switch and the second switch are turned off, the first stage circuit and the second stage circuit are turned off, the third stage circuit to the tenth stage circuit and the flash The analog-to-digital sub-converter works to realize the working mode of the second frequency.

Wherein, with the first-level circuit, the second-level circuit, the third-level circuit, the fourth-level circuit, the fifth-level circuit, the sixth-level circuit, the seventh-level circuit, the eighth-level circuit, the ninth-level circuit, The reference voltage generation circuit connected to the tenth stage circuit and a two-bit flash analog-to-digital sub-converter provides a stable reference voltage for each stage circuit.

Wherein, with the first-level circuit, the second-level circuit, the third-level circuit, the fourth-level circuit, the fifth-level circuit, the sixth-level circuit, the seventh-level circuit, the eighth-level circuit, the ninth-level circuit, The clock generation circuit connected to the tenth stage circuit and a two-bit flash analog-to-digital sub-converter provides an accurate clock circuit for each stage circuit.

Wherein, the above-mentioned analog-to-digital converter also includes:

and the first level circuit, the second level circuit, the third level circuit, the fourth level circuit, the fifth level circuit, the sixth level circuit, the seventh level circuit, the eighth level circuit, the ninth level circuit, the tenth level circuit A reference current generating circuit connected to a stage circuit and a two-bit flash analog-to-digital sub-converter, and a frequency-to-current converter connected to the reference current generating circuit.

Wherein, the frequency-to-current converter includes: an operational amplifier, at least one MOS transistor, a decoupling capacitor and a switched capacitor circuit;

Wherein, the input terminal of the operational amplifier is connected to Vbg and the drain of the first MOS transistor in the at least 3 MOS transistors, and the output is connected to the gate of each MOS in the at least 1 MOS transistor, forming a unity gain structure;

The drain of the first MOS transistor is simultaneously connected to the decoupling capacitor and the switched capacitor circuit controlled by a clock.

Wherein, each stage circuit of the first stage circuit to the tenth stage circuit includes:

a first CMOS transmission gate switch, a second CMOS transmission gate switch, a third CMOS transmission gate switch, and a fourth CMOS transmission gate switch controlled by a first clock signal;

The first sampling capacitor connected to the first CMOS transmission gate switch, the second sampling capacitor connected to the second CMOS transmission gate switch, the third sampling capacitor connected to the third CMOS transmission gate switch, and the The fourth sampling capacitor connected to the fourth CMOS transmission gate switch;

The fifth CMOS transmission gate switch and the sixth CMOS transmission gate switch controlled by the second clock signal, one end of the fifth CMOS transmission gate switch is connected to the first sampling capacitor, and the other end is connected to the output end of the residual amplifier ; One end of the sixth CMOS transmission gate switch is connected to the fourth sampling capacitor, and the other end is connected to the output end of the residual amplifier;

The first sub-ADC, the first sub-DAC connected to the first sub-ADC, the first sub-DAC is further connected to the second sampling capacitor and the first sub-ADC Three sampling capacitor connections;

a common-mode feedback unit connected to the output terminal of the residual amplifier;

The surplus amplifier is also connected to the output terminal of the frequency-to-current converter.

Wherein, the first sub-digital-to-analog converter is also connected to a reference voltage;

The first input terminal of the residual amplifier is also connected to the first sampling capacitor and the second sampling capacitor;

The second input terminal of the residual amplifier is also connected to the third sampling capacitor and the fourth sampling capacitor;

The first input terminal and the second input terminal of the residual amplifier are connected through a seventh CMOS transmission gate switch controlled by a third clock.

Wherein, the operational amplifier circuit in the first sub-digital-to-analog converter includes:

The thirteenth MOS tube (M13), the fourteenth MOS tube (M14), the fifteenth MOS tube (M15), the sixteenth MOS tube (M16), and the seventeenth MOS tube (M17) as each branch tail current source;

The third MOS tube (M3) and the fourth MOS tube (M4) are the input stage differential pair tubes, the input end is connected to the differential input signal, and the drain end is respectively connected to the fifth MOS tube (M5) and the sixth MOS tube (M6) Drain;

And the fifth MOS transistor (M5) to the tenth MOS transistor (M10) are respectively connected end to end to form a cascode structure;

The drains of the seventh MOS transistor (M7) and the eighth MOS transistor (M8) are respectively connected to the gates of the first MOS transistor (M1) and the second MOS transistor (M2);

At the same time, the first Maitreya compensation capacitor (C0) is connected to the source terminal of the ninth MOS transistor (M9) and the drain terminal of the eleventh MOS transistor (M11), and the second Maitreya compensation capacitor (C1) is connected to the ninth MOS transistor through the switch T1. The source end of the tube (M9) and the drain end of the eleventh MOS tube (M11);

The third Maitreya compensation capacitor (C2) is connected to the source terminal of the tenth MOS transistor (M10) and the drain terminal of the twelfth MOS transistor (M12), and the fourth Maitreya compensation capacitor (C3) is connected to the tenth MOS transistor through the switch T2 The source terminal of (M10) and the drain terminal of the twelfth MOS transistor (M12);

The eleventh MOS tube (M11), the twelfth MOS tube (M12), the first MOS tube (M1), the second MOS tube (M2), and the sixteenth MOS tube (M16) form an output stage differential op amp;

The seventeenth MOS tube (M17), the eighteenth MOS tube (M18), the nineteenth MOS tube (M19), the twenty MOS tube (M20), the twenty-first MOS tube (M21), the twenty-second The MOS tube (M22) is respectively connected with the fifth MOS tube (M5), the sixth MOS tube (M6), the eleventh MOS tube (M11), the twelfth MOS tube (M12), the fourteenth MOS tube (M14), The fifteenth MOS transistor (M15) is connected in parallel, and the gate is controlled by the first sub-switch T0 and the second sub-switch T of the universal serial bus SPI port signal to determine whether it is connected to the bias voltage Vbias1;

The third sub-switch T1 and the fourth sub-switch T2 are respectively connected between the output nodes of the second Miller compensation capacitor ( C1 ) and the fourth Miller compensation capacitor ( C3 ) for controlling the phase margin.

Wherein, through the configuration of MOS transistors and capacitors, the analog-to-digital converter also has the following working modes:

Shutdown mode in which all 11 circuits are shut down;

The 11-level circuits are all turned off, the reference voltage generating circuit and the clock generating circuit are also turned off, and only the reference current generating circuit is turned on for the preparation mode;

All 11-level circuits are working, the sampling rate is much lower than the low-speed mode of 100M, and the reference current generation circuit, reference voltage generation circuit, and clock generation circuit are working normally;

The internal reference current generation circuit of the analog-to-digital converter is turned off, and the reference current of each stage is provided by an external reference current mode;

The internal reference voltage generating circuit of the analog-to-digital converter is turned off, and the reference voltage of each stage is provided by an external reference voltage mode;

The clock generation circuit inside the analog-to-digital converter is turned off, and the clock of each stage circuit is provided by an external clock mode.

The beneficial effects of above-mentioned technical scheme of the present invention are as follows:

In the above solution, through the setting of the first switch and the second switch, an analog-to-digital converter with optional digits (first frequency mode or second frequency mode) is provided, and the sampling rate of the analog-to-digital converter is adjustable (32MSPS to 100MSPS) is configurable, and is also suitable for different applications and working conditions.

Description of drawings

Fig. 1 is the pipeline structure diagram of analog-to-digital converter of the present invention;

Fig. 2 is each stage pipeline circuit structure diagram of analog-to-digital converter shown in Fig. 1;

Fig. 3 is the structural diagram of the digital-to-analog converter in the circuit shown in Fig. 2;

FIG. 4 is a structural diagram of an operational amplifier in the circuit shown in FIG. 2 .

detailed description

In order to make the technical problems, technical solutions and advantages to be solved by the present invention clearer, the following will describe in detail with reference to the drawings and specific embodiments.

As shown in FIG. 1 , an embodiment of the present invention provides an analog-to-digital converter, including: a first-level circuit, a second-level circuit, a third-level circuit, a fourth-level circuit, a fifth-level circuit, and a first-level circuit connected in sequence. A sixth-level circuit, a seventh-level circuit, an eighth-level circuit, a ninth-level circuit, a tenth-level circuit, and a two-bit flash analog-to-digital sub-converter;

and the first level circuit, the second level circuit, the third level circuit, the fourth level circuit, the fifth level circuit, the sixth level circuit, the seventh level circuit, the eighth level circuit, the ninth level circuit, the tenth level circuit stage circuit and a redundant calibration circuit connected to a two-bit flash analog-to-digital sub-converter;

Wherein, the first stage circuit is connected to the redundant calibration circuit through a first switch K1; the second stage circuit is connected to the redundant calibration circuit through a second switch K2;

When both the first switch K1 and the second switch K2 are closed, all the circuits from the first stage to the tenth stage and the flash analog-to-digital sub-converter work to realize the operation of the first frequency mode, such as the high-resolution working mode with a resolution of 12, the sampling rate is 100M or close to 100M, all 11 pipeline stages are working, and other circuit modules such as the reference current generation circuit, the reference voltage generation circuit, and the clock generation circuit are also working normally ;

When both the first switch K1 and the second switch K2 are turned off, the first stage circuit and the second stage circuit are turned off, and the third stage circuit to the tenth stage circuit and the The flash analog-to-digital sub-converter works to realize the working mode of the second frequency, such as the low-resolution working mode with a resolution of 10.

Among them, the above-mentioned analog-to-digital converter also includes:

and the first level circuit, the second level circuit, the third level circuit, the fourth level circuit, the fifth level circuit, the sixth level circuit, the seventh level circuit, the eighth level circuit, the ninth level circuit, the tenth level circuit The reference voltage generation circuit connected to the two-stage circuit and a two-bit flash analog-to-digital sub-converter provides a stable reference voltage for each stage circuit.

Wherein, the above-mentioned analog-to-digital converter also includes: the first-level circuit, the second-level circuit, the third-level circuit, the fourth-level circuit, the fifth-level circuit, the sixth-level circuit, the seventh-level circuit, The eighth stage circuit, the ninth stage circuit, the tenth stage circuit and a two-bit flash analog-to-digital sub-converter are all connected to a clock generation circuit to provide each stage circuit with an accurate clock clock circuit.

Among them, the above-mentioned analog-to-digital converter also includes:

and the first level circuit, the second level circuit, the third level circuit, the fourth level circuit, the fifth level circuit, the sixth level circuit, the seventh level circuit, the eighth level circuit, the ninth level circuit, the tenth level circuit A reference current generating circuit connected to a stage circuit and a two-bit flash analog-to-digital sub-converter, and a frequency-to-current converter connected to the reference current generating circuit. The reference current generating circuit provides each stage circuit with an adaptive bias current with frequency. The frequency current converter (FCC) generates a reference current that varies with frequency. When the sampling rate is reduced, the op amp of each stage The bias current is also reduced, thereby reducing the overall power consumption while keeping the performance of the converter unchanged, and achieving the purpose of reducing the power consumption of the analog-to-digital converter as the frequency decreases.

As shown in Figure 3, the frequency-to-current converter includes: an operational amplifier, at least one MOS transistor, a decoupling capacitor and a switched capacitor circuit;

Wherein, the input terminal of the operational amplifier is connected to Vbg and the drain of the first MOS transistor in the at least 3 MOS transistors, and the output is connected to the gate of each MOS in the at least 1 MOS transistor, forming a unity gain structure;

The drain of the first MOS transistor is simultaneously connected to the decoupling capacitor and the switched capacitor circuit controlled by a clock.

As shown in Figure 2, each stage circuit of the first stage circuit to the tenth stage circuit includes:

The first CMOS transmission gate switch L1, the second CMOS transmission gate switch L2, the third CMOS transmission gate switch L3 and the fourth CMOS transmission gate switch L4 controlled by the first clock signal CLK1;

The first sampling capacitor C11 connected to the first CMOS transmission gate switch L1, the second sampling capacitor C12 connected to the second CMOS transmission gate switch L2, the third sampling capacitor C12 connected to the third CMOS transmission gate switch L3 A sampling capacitor C13, a fourth sampling capacitor C14 connected to the fourth CMOS transmission gate switch L4;

The fifth CMOS transmission gate switch L5 and the sixth CMOS transmission gate switch L6 controlled by the second clock signal CLK2, one end of the fifth CMOS transmission gate switch L5 is connected to the first sampling capacitor C11, and the other end is connected to the margin The output end of the amplifier AMP is connected; one end of the sixth CMOS transmission gate switch L6 is connected to the fourth sampling capacitor C14, and the other end is connected to the output end of the residual amplifier AMP;

A first sub-analog-to-digital converter (Sub_ADC), a first sub-digital-to-analog converter (DAC) connected to the first sub-analog-to-digital converter (Sub_ADC), the first sub-digital-to-analog converter (DAC) connected to the second sampling capacitor C12 and the third sampling capacitor C13;

a common mode feedback unit CMFB connected to the output end of the margin amplifier AMP;

The residual amplifier AMP is also connected to the output of the frequency current converter (FCC).

Wherein, the first sub-digital-to-analog converter (DAC) is also connected to the reference voltage Vref;

The first input end of the residual amplifier AMP is also connected to the first sampling capacitor C11 and the second sampling capacitor C12;

The second input terminal of the residual amplifier AMP is also connected to the third sampling capacitor C13 and the fourth sampling capacitor C14;

The first input terminal and the second input terminal of the residual amplifier AMP are connected through a seventh CMOS transmission gate switch L7 controlled by the third clock CLK1a.

Wherein, as shown in FIG. 4, the CMOS operational amplifier circuit in the first sub-digital-to-analog converter (DAC) includes:

The thirteenth MOS tube M13, the fourteenth MOS tube M14, the fifteenth MOS tube M15, the sixteenth MOS tube M16, and the seventeenth MOS tube M17 serve as tail current sources for each branch;

The third MOS transistor M3 and the fourth MOS transistor M4 are input stage differential pair transistors, the input end is connected to the differential input signal, and the drain end is respectively connected to the drains of the fifth MOS transistor M5 and the sixth MOS transistor M6;

And the fifth MOS transistor M5 to the tenth MOS transistor M10 are respectively connected end to end to form a cascode structure;

The drains of the seventh MOS transistor M7 and the eighth MOS transistor M8 are respectively connected to the gates of the first MOS transistor M1 and the second MOS transistor M2;

At the same time, the first Maitreya compensation capacitor C0 is connected to the source end of the ninth MOS transistor M9 and the drain end of the eleventh MOS transistor M11, and the second Maitreya compensation capacitor C1 is connected to the source end of the ninth MOS transistor M9 and the drain end of the eleventh MOS transistor M11 through a switch T1. A drain terminal of the MOS transistor M11;

The third Maitreya compensation capacitor C2 is connected to the source end of the tenth MOS transistor M10 and the drain end of the twelfth MOS transistor M12, and the fourth Maitreya compensation capacitor C3 is connected to the source end of the tenth MOS transistor M10 and the drain end of the twelfth MOS transistor M12 through a switch T2. The drain end of the MOS tube M12;

The eleventh MOS transistor M11, the twelfth MOS transistor M12, the first MOS transistor M1, the second MOS transistor M2, and the sixteenth MOS transistor M16 form an output stage differential operational amplifier;

The seventeenth MOS tube M17, the eighteenth MOS tube M18, the nineteenth MOS tube M19, the twenty MOS tube M20, the twenty-first MOS tube M21, the twenty-second MOS tube M22 and the fifth MOS tube M5 respectively , the sixth MOS transistor M6, the eleventh MOS transistor M11, the twelfth MOS transistor M12, the fourteenth MOS transistor M14, and the fifteenth MOS transistor M15 are connected in parallel, and the gate is controlled by the first universal serial bus SPI port signal The sub-switch T0 and the second sub-switch T determine whether to connect to the bias voltage Vbias1;

The third sub-switch T1 and the fourth sub-switch T2 are connected between the output nodes of the second Miller compensation capacitor C1 and the fourth Miller compensation capacitor C3 for controlling the phase margin.

In this embodiment, the converter adopts a programmable design at the transistor level, and the operational amplifier of each stage is a programmable operational amplifier. The number of connected load tubes is set through digital switches T0 and T, and the Miller compensation capacitor is also set through the same The method is adjustable. When the sampling rate changes, the bias current of the operational amplifier also changes. Through the fine-tuning of the digital switch, while ensuring the stability of the operational amplifier, the DC gain, small signal bandwidth, and slew rate of the operational amplifier can meet the requirements. Frequency requirements, so that the converter works at its best.

Through the configurable principle of the above two points, the above-mentioned analog-to-digital converter of the present invention has the following six working modes in addition to the above-mentioned first frequency working mode and the second frequency working mode of normal operation:

1: Shutdown mode. At this time, all 11 pipeline stages are turned off, and other circuit modules are also turned off, and the power consumption of the converter is the minimum value. At this time, the switches Ta, Tb, and Tc in Figure 1 are all turned off, and the digital code output is uniformly zero. .

2: Preparatory mode. At this time, all 11 pipeline stages are turned off, the reference voltage generation circuit, the clock generation circuit and other modules are also turned off, and only the reference current generation circuit is turned on, that is, Ta and Tb are turned off, and Tc is turned on. The purpose of using this mode is to reduce the start-up time of the converter (the start-up of the reference current generation circuit takes a certain amount of time). This mode consumes more power than shutdown mode and less than other operating modes.

3: Low speed mode. At this time, all 11 pipeline stages are working, and the sampling rate is far less than 100 megabytes. Through the fine-tuning of the operational amplifier, each stage can work in a suitable state. The converter has the best performance at this frequency. At this time, the reference current generation circuit , The reference voltage generating circuit and the clock generating circuit work normally, that is, Ta, Tb, and Tc are all turned on.

4: Externally provided reference current mode. At this time, although the converter has been started, the internal reference current generation circuit is turned off, that is, Tc is turned off, Ta and Tb are all turned on, and the reference current of each stage is provided externally.

5: The reference voltage mode is provided externally. At this time, the reference voltage generation circuit inside the converter is turned off, that is, Tb is turned off, Ta and Tc are all turned on, and the reference voltage of each stage is provided externally.

6: Externally provided clock mode. At this time, the clock generation circuit inside the converter is turned off, that is, Ta is turned off, Tb and Tc are all turned on, and the clock of each stage is provided externally.

In addition, in the above-mentioned working mode of the first resolution controlled by the first switch K1 and the second switch K2, the resolution of the analog-to-digital converter can be 12, the sampling rate is 100 Mbits or close to 100 Mbits, and the 11-stage pipeline stage All work, and other circuit modules such as the reference current generation circuit, the reference voltage generation circuit, and the clock generation circuit also work normally.

In the above-mentioned second resolution working mode controlled by the first switch K1 and the second switch K2, the resolution of the analog-to-digital converter can be 10. At this time, among the 11 pipeline stages, the first two stages are turned off, and the latter stages are turned off. Level nine works normally, the number of digits is 10, and the sampling rate is 100 megabytes or close to 100 megabytes. At this time, the reference current generation circuit, reference voltage generation circuit, and clock generation circuit work normally.

The above-mentioned analog-to-digital converter of the present invention adopts a reconfigurable design on the system structure, and the highest two bits have a shutdown function, which realizes the optional number of bits (10-bit or 12-bit conversion) and adjustable sampling rate (32MSPS to 100MSPS) configurable A/D converter, which contains eight working modes, suitable for different applications and working states.

The above description is a preferred embodiment of the present invention, it should be pointed out that for those of ordinary skill in the art, without departing from the principle of the present invention, some improvements and modifications can also be made, and these improvements and modifications can also be made. It should be regarded as the protection scope of the present invention.

Claims (5)

1. A high-speed configurable pipeline analog-to-digital converter, characterized in that, comprising: The first level circuit, the second level circuit, the third level circuit, the fourth level circuit, the fifth level circuit, the sixth level circuit, the seventh level circuit, the eighth level circuit, the ninth level circuit, the tenth level circuit connected in sequence stage circuit and a two-bit flash analog-to-digital sub-converter; and the first level circuit, the second level circuit, the third level circuit, the fourth level circuit, the fifth level circuit, the sixth level circuit, the seventh level circuit, the eighth level circuit, the ninth level circuit, the tenth level circuit stage circuit and a redundant calibration circuit connected to a two-bit flash analog-to-digital sub-converter; Wherein, the first stage circuit is connected to the redundant calibration circuit through a first switch; the second stage circuit is connected to the redundant calibration circuit through a second switch; When both the first switch and the second switch are closed, all the circuits from the first stage to the tenth stage and the flash analog-to-digital sub-converter work to realize the working mode of the first frequency; When both the first switch and the second switch are turned off, the first stage circuit and the second stage circuit are turned off, and the third stage circuit to the tenth stage circuit and the fast The flash-to-analog-digital sub-converter works to realize the working mode of the second frequency; and the first level circuit, the second level circuit, the third level circuit, the fourth level circuit, the fifth level circuit, the sixth level circuit, the seventh level circuit, the eighth level circuit, the ninth level circuit, the tenth level circuit A reference voltage generation circuit connected to the two-stage circuit and a two-bit flash analog-to-digital sub-converter provides a stable reference voltage for each stage circuit; and the first level circuit, the second level circuit, the third level circuit, the fourth level circuit, the fifth level circuit, the sixth level circuit, the seventh level circuit, the eighth level circuit, the ninth level circuit, the tenth level circuit The clock generation circuit connected to the two-stage circuit and a two-bit flash analog-to-digital sub-converter provides an accurate clock circuit for each stage circuit; and the first level circuit, the second level circuit, the third level circuit, the fourth level circuit, the fifth level circuit, the sixth level circuit, the seventh level circuit, the eighth level circuit, the ninth level circuit, the tenth level circuit A reference current generating circuit connected to a stage circuit and a two-bit flash analog-to-digital sub-converter, and a frequency-to-current converter connected to the reference current generating circuit; The frequency-to-current converter includes: an operational amplifier, at least one MOS transistor, a decoupling capacitor and a switched capacitor circuit; Wherein, the input terminal of the operational amplifier is connected to Vbg and the drain of the first MOS transistor in the at least 3 MOS transistors, and the output is connected to the gate of each MOS in the at least 1 MOS transistor, forming a unity gain structure; The drain of the first MOS transistor is simultaneously connected to the decoupling capacitor and the switched capacitor circuit controlled by a clock. 2. The analog-to-digital converter according to claim 1, wherein each stage of the circuit from the first stage circuit to the tenth stage circuit comprises: a first CMOS transmission gate switch, a second CMOS transmission gate switch, a third CMOS transmission gate switch, and a fourth CMOS transmission gate switch controlled by a first clock signal; The first sampling capacitor connected to the first CMOS transmission gate switch, the second sampling capacitor connected to the second CMOS transmission gate switch, the third sampling capacitor connected to the third CMOS transmission gate switch, and the The fourth sampling capacitor connected to the fourth CMOS transmission gate switch; The fifth CMOS transmission gate switch and the sixth CMOS transmission gate switch controlled by the second clock signal, one end of the fifth CMOS transmission gate switch is connected to the first sampling capacitor, and the other end is connected to the output end of the residual amplifier ; One end of the sixth CMOS transmission gate switch is connected to the fourth sampling capacitor, and the other end is connected to the output end of the residual amplifier; The first sub-ADC, the first sub-DAC connected to the first sub-ADC, the first sub-DAC is also connected to the second sampling capacitor and the third Sampling capacitor connection; a common-mode feedback unit connected to the output terminal of the residual amplifier; The surplus amplifier is also connected to the output terminal of the frequency-to-current converter. 3. The analog-to-digital converter according to claim 2, wherein the first sub-digital-to-analog converter is also connected to a reference voltage; The first input terminal of the residual amplifier is also connected to the first sampling capacitor and the second sampling capacitor; The second input terminal of the residual amplifier is also connected to the third sampling capacitor and the fourth sampling capacitor; The first input terminal and the second input terminal of the residual amplifier are connected through a seventh CMOS transmission gate switch controlled by a third clock. 4. The analog-to-digital converter according to claim 2 or 3, wherein the operational amplifier circuit in the first sub-digital-to-analog converter comprises: The thirteenth MOS tube (M13), the fourteenth MOS tube (M14), the fifteenth MOS tube (M15), the sixteenth MOS tube (M16), and the seventeenth MOS tube (M17) are used as each branch tail current source; The third MOS transistor (M3) and the fourth MOS transistor (M4) are input stage differential pair transistors, the input end is connected to the differential input signal, and the drain end is respectively connected to the fifth MOS transistor (M5) and the sixth MOS transistor (M6) Drain; And the fifth MOS transistor (M5) to the tenth MOS transistor (M10) are respectively connected end to end to form a cascode structure; The drains of the seventh MOS transistor (M7) and the eighth MOS transistor (M8) are respectively connected to the gates of the first MOS transistor (M1) and the second MOS transistor (M2); At the same time, the first Maitreya compensation capacitor (C0) is connected to the source end of the ninth MOS transistor (M9) and the drain end of the eleventh MOS transistor (M11), and the second Maitreya compensation capacitor (C1) passes through the third sub-switch (T1) connected to the source end of the ninth MOS transistor (M9) and the drain end of the eleventh MOS transistor (M11); The third Maitreya compensation capacitor (C2) is connected to the source end of the tenth MOS transistor (M10) and the drain end of the twelfth MOS transistor (M12), and the fourth Maitreya compensation capacitor (C3) is connected through the fourth sub-switch (T2) to the source end of the tenth MOS transistor (M10) and the drain end of the twelfth MOS transistor (M12); The eleventh MOS transistor (M11), the twelfth MOS transistor (M12), the first MOS transistor (M1), the second MOS transistor (M2), and the sixteenth MOS transistor (M16) form an output stage differential operational amplifier; The seventeenth MOS tube (M17), the eighteenth MOS tube (M18), the nineteenth MOS tube (M19), the twentieth MOS tube (M20), the twenty-first MOS tube (M21), the twenty-second The MOS tube (M22) is respectively connected with the fifth MOS tube (M5), the sixth MOS tube (M6), the eleventh MOS tube (M11), the twelfth MOS tube (M12), the fourteenth MOS tube (M14), The fifteenth MOS tube (M15) is connected in parallel, and the gate is controlled by the first sub-switch (T0) and the second sub-switch (T) of the universal serial bus SPI port signal to determine whether it is connected to the bias voltage Vbias1; The third sub-switch ( T1 ) and the fourth sub-switch ( T2 ) are respectively connected between the output nodes of the second Maitreya compensation capacitor ( C1 ) and the fourth Maitreya compensation capacitor ( C3 ) for controlling the phase margin. 5. The analog-to-digital converter according to claim 4, characterized in that, through the configuration of the MOS tube and the capacitor, the analog-to-digital converter also has the following operating modes: Shutdown mode in which all 11 circuits are turned off; The 11-level circuits are all turned off, the reference voltage generating circuit and the clock generating circuit are also turned off, and only the reference current generating circuit is turned on for the preparation mode; All 11-level circuits are working, the sampling rate is much lower than the low-speed mode of 100M, and the reference current generation circuit, reference voltage generation circuit, and clock generation circuit are working normally; The internal reference current generation circuit of the analog-to-digital converter is turned off, and the reference current of each stage is provided by an external reference current mode; The reference voltage generation circuit inside the analog-to-digital converter is turned off, and the reference voltage of each stage is provided by an external reference voltage mode; The clock generation circuit inside the analog-to-digital converter is turned off, and the clock of each stage circuit is provided by an external clock mode.