CN103972050A - Preparation method of polycrystalline silicon thin film, polycrystalline silicon thin film transistor and array substrate - Google Patents

Abstract

The embodiment of the present invention provides a method for preparing a polysilicon thin film, a polysilicon thin film transistor, and an array substrate, which relates to the field of display technology, can make polysilicon crystallize uniformly, increase the grain size, improve the crystallization quality, and thereby improve the electrical properties of the thin film transistor. Performance is improved. The preparation method of the polysilicon thin film comprises: forming an amorphous silicon thin film on a substrate; using an excimer laser annealing method to process the amorphous silicon thin film to crystallize the amorphous silicon thin film into a polysilicon thin film; further forming the amorphous silicon thin film After the silicon thin film, before adopting the excimer laser annealing method to process the amorphous silicon thin film, the method also includes: treating the surface of the amorphous silicon thin film with a nickel salt solution, so that the nickel salt solution is evenly coated on the amorphous silicon thin film surface. It is used for the preparation of polysilicon thin films, low-temperature polysilicon thin film transistors and array substrates that need to improve the uniformity of polysilicon crystallization, increase the grain size, and improve the crystal quality.

Description

Preparation method of polysilicon film, polysilicon thin film transistor and array substrate

technical field

The invention relates to the field of display technology, in particular to a method for preparing a polysilicon thin film, a method for preparing a low-temperature polysilicon thin film transistor, and a method for preparing an array substrate.

Background technique

Low Temperature Poly-Silicon-Thin Film Transistor (LTPS-TFT) display has the advantages of high resolution, fast response, high brightness, high aperture ratio, etc., and because of the characteristics of LTPS, it has high Electron mobility; in addition, the peripheral drive circuit can also be produced on the glass substrate at the same time to achieve the goal of system integration, save space and cost of the drive IC, and reduce product defect rate.

At present, the low-temperature polysilicon thin film transistor includes an active layer, a gate insulating layer, a gate electrode, a source electrode, and a drain electrode arranged on a substrate; the active layer includes a source region, a drain region, and a Channel region between source region and drain region etc.

Wherein, the active layer is obtained by performing an ion implantation process on the polysilicon layer, and the polysilicon layer is generally formed by forming an amorphous silicon thin film on the substrate, and then using an excimer laser annealing method to convert the amorphous silicon into polysilicon, Then, the polysilicon film is formed into a polysilicon layer with a specific pattern through a patterning process.

However, as a gas laser, the excimer laser has relatively poor stability, and the prepared polysilicon grains have relatively poor uniformity, resulting in poor uniformity of electrical characteristics of the thin film transistor. In addition, the usual excimer laser crystallization process melts and recrystallizes amorphous silicon in a short period of time. The grain size is small and the crystal quality is not high, which limits the improvement of the electrical performance of thin film transistor devices.

Contents of the invention

Embodiments of the present invention provide a method for preparing a polysilicon film, a polysilicon thin film transistor, and an array substrate, which can make the polysilicon crystallize uniformly, increase the grain size, improve the crystallization quality, and improve the electrical performance of the thin film transistor.

In order to achieve the above object, embodiments of the present invention adopt the following technical solutions:

On the one hand, a method for preparing a polysilicon thin film is provided, comprising: forming an amorphous silicon thin film on a base substrate; using an excimer laser annealing method to process the amorphous silicon thin film to crystallize the amorphous silicon thin film It is a polysilicon film; further, after forming the amorphous silicon film, before using the excimer laser annealing method to treat the amorphous silicon film, the method also includes: performing Nickel salt solution treatment, so that the nickel salt solution is evenly coated on the surface of the amorphous silicon film.

In another aspect, a method for preparing a polysilicon thin film transistor is provided, comprising: forming an active layer, a gate insulating layer above the active layer, a gate electrode, a source electrode and a drain electrode on a base substrate; The source layer includes a source region, a drain region, and a channel region between the source region and the drain region; wherein, the active layer is connected to the polysilicon layer and the source region and The region corresponding to the drain region is formed by a doping process; the polysilicon layer is obtained by performing a patterning process on the above-mentioned polysilicon film.

In yet another aspect, a method for preparing an array substrate is provided, including: forming a thin film transistor and a pixel electrode; wherein, the thin film transistor is formed by the above method for preparing a polysilicon thin film transistor.

The embodiment of the present invention provides a method for preparing a polysilicon thin film, a polysilicon thin film transistor, and an array substrate. The method for preparing the polysilicon thin film includes forming an amorphous silicon thin film on a substrate; Crystalline silicon film is processed to crystallize the amorphous silicon film into a polysilicon film; further, after forming the amorphous silicon film, before using the excimer laser annealing method to process the amorphous silicon film, the The method further includes: treating the surface of the amorphous silicon film with a nickel salt solution, so that the nickel salt solution is evenly coated on the surface of the amorphous silicon film.

Because before adopting excimer laser annealing method to described amorphous silicon thin film is processed, the surface of amorphous silicon thin film has been carried out nickel salt solution treatment, can remain nickel on the surface of amorphous silicon thin film, after excimer laser annealing treatment , the nickel silicide formed by nickel and silicon is used as the seed crystal of amorphous silicon, which can promote the transformation of amorphous silicon to polysilicon, and make the crystallization of polysilicon uniform, with large grain size and high crystal quality, so that the prepared thin film transistor The electrical performance is improved.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only These are some embodiments of the present invention. Those skilled in the art can also obtain other drawings based on these drawings without creative work.

FIG. 1 is a schematic flow diagram of a method for preparing a polysilicon thin film transistor provided by an embodiment of the present invention;

2-7 are schematic diagrams of a process for preparing a polysilicon thin film transistor according to an embodiment of the present invention;

FIG. 8 is a first structural schematic diagram of an array substrate provided by an embodiment of the present invention;

FIG. 9 is a second structural schematic diagram of an array substrate provided by an embodiment of the present invention.

Reference signs:

10-substrate substrate; 20-buffer layer; 30-polysilicon layer; 301-amorphous silicon film; 302-polysilicon film; 40-gate insulating layer; 50-gate electrode; 60-active layer; 601-source region ; 602-drain region; 603-channel region; 70-interlayer insulating layer; 801-source electrode; 802-drain electrode; 90-planarization layer; 100-pixel electrode; 110-passivation layer; 120-public electrode.

Detailed ways

The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

An embodiment of the present invention provides a method for preparing a polysilicon thin film, comprising: forming an amorphous silicon thin film on a base substrate; using an excimer laser annealing method to treat the amorphous silicon thin film, so that the amorphous silicon thin film crystallized into a polysilicon film; further, after forming the amorphous silicon film, before adopting the excimer laser annealing method to process the amorphous silicon film, the method also includes: The surface is treated with a nickel salt solution, so that the nickel salt solution is evenly coated on the surface of the amorphous silicon film.

Wherein, the amorphous silicon thin film is processed by excimer laser annealing method, and the crystallization of the amorphous silicon thin film into a polysilicon thin film is realized through the following process, namely: adopting excimer laser irradiation treatment, within about 50-150 ns The surface of the amorphous silicon film reaches a high temperature of more than 1000 ℃ in an instant to become a molten state; then the molten amorphous silicon is annealed to crystallize it to form a polysilicon film.

During this process, it can also be ensured that the temperature of the glass substrate is around or below 400°C. The mechanism is: the laser pulse first excites hot electron-hole pairs in the amorphous silicon film, and then the electron-hole pairs transfer energy to the lattice atoms in a non-radiative recombination manner, thereby realizing the formation of the amorphous silicon film. Heats up instantly. Among them, since the instantaneous energy of the laser pulse is absorbed by the amorphous silicon film and converted into phase transition energy, there will not be too much thermal energy conducted to the glass substrate, which can avoid the temperature rise of the glass substrate during general furnace annealing resulting in deformation problems.

On the basis of the above, since the surface of the amorphous silicon film has been treated with nickel (Ni) salt solution before adopting the excimer laser annealing method to process the amorphous silicon film, nickel will remain on the surface of the amorphous silicon film. The surface, therefore, undergoes excimer laser annealing, where nickel and silicon react to form nickel-silicon bonds, forming a nickel-silicon mixture. Since the free energy of the crystalline silicon state is lower than that of the amorphous state, the thermal equilibrium process of breaking and recombining the nickel-silicon bond promotes the local lattice reorganization from amorphous silicon to polysilicon. Among them, nickel silicide (SiN ₂ ) formed by nickel and silicon is easy to form at 350°C, and its lattice constant is only 0.4% different from that of silicon, which is very suitable as a seed crystal for the crystallization of amorphous silicon. On the one hand, It can promote the transformation of amorphous silicon to polysilicon. On the other hand, due to the relatively uniform nucleation center (seed crystal), it can make polysilicon crystallize uniformly, and due to the catalytic effect of nickel, at the same temperature and time, it catalyzes the growth. The larger grain size results in higher crystalline quality.

An embodiment of the present invention provides a method for preparing a polysilicon thin film, comprising: forming an amorphous silicon thin film on a base substrate; using an excimer laser annealing method to treat the amorphous silicon thin film to make the amorphous silicon thin film into a polycrystalline silicon film; further, after forming the amorphous silicon film, before adopting the excimer laser annealing method to process the amorphous silicon film, the method also includes: treating the surface of the amorphous silicon film Nickel salt solution treatment is carried out so that the nickel salt solution is evenly coated on the surface of the amorphous silicon film. Because before adopting excimer laser annealing method to described amorphous silicon thin film is processed, the surface of amorphous silicon thin film has been carried out nickel salt solution treatment, can remain nickel on the surface of amorphous silicon thin film, after excimer laser annealing treatment , the nickel silicide formed by nickel and silicon is used as the seed crystal of amorphous silicon, which can promote the transformation of amorphous silicon to polysilicon, and make polysilicon crystallize uniformly, with large grain size and high crystal quality; when the polysilicon film is used for the preparation of When used as the active layer of the thin film transistor, the electrical performance of the thin film transistor can be improved.

Optionally, the nickel salt solution can be uniformly coated on the surface of the amorphous silicon film by soaking or spraying.

Considering that when the concentration of nickel in the nickel salt solution is too high, more nickel metal ions will enter the amorphous silicon layer, resulting in too many nucleation centers and affecting the growth of grains, reducing the grain size. At the same time, it is also possible Cause metal ion pollution; therefore, the nickel salt solution in the embodiment of the present invention only needs to use a solution containing a small amount of nickel, preferably a solution with a nickel concentration of 1-1000 μg/mg.

Based on the above description, in order to avoid the problem of hydrogen explosion when the excimer laser annealing method is used to process the amorphous silicon thin film. In the embodiment of the present invention, it is preferable to dehydrogenate the amorphous silicon film after the surface of the amorphous silicon film is treated with a nickel salt solution and before the amorphous silicon film is treated by an excimer laser annealing method. Process treatment, so that the hydrogen content in the amorphous silicon film is below 3%.

Here, the dehydrogenation temperature may be 400-600° C., and the treatment time may be 20-120 minutes.

It should be noted that if other methods are used to control the hydrogen content in the amorphous silicon film below 3%, this step can be omitted, and it can be performed according to the actual situation.

The embodiment of the present invention also provides a method for preparing a polysilicon thin film transistor, comprising: forming an active layer, a gate insulating layer above the active layer, a gate electrode, a source electrode and a drain electrode on a base substrate; The active layer includes a source region, a drain region, and a channel region between the source region and the drain region; wherein, the active layer is connected to the source through the polysilicon layer The region corresponding to the drain region is formed by a doping process; the polysilicon layer is obtained by patterning the polysilicon film obtained above.

Because before adopting excimer laser annealing method to described amorphous silicon thin film is processed, the surface of amorphous silicon thin film has been carried out nickel salt solution treatment, can remain nickel on the surface of amorphous silicon thin film, after excimer laser annealing treatment , the nickel silicide formed by nickel and silicon is used as the seed crystal of amorphous silicon, which can promote the transformation of amorphous silicon to polysilicon, and make the crystallization of polysilicon uniform, with large grain size and high crystal quality, so that the electrical properties of thin film transistors can be improved. promote.

Preferably, the thickness of the polysilicon layer is

Preferably, the polysilicon layer is obtained by patterning the polysilicon film, which can be achieved through the following steps:

S101, forming a photoresist film on the substrate on which the polysilicon film is formed.

S102. Exposing the substrate on which the photoresist thin film is formed by using a common mask, and forming a photoresist completely retained part and a photoresist completely removed part after development; wherein, the photoresist completely retained part and the The polysilicon layer corresponds, and the part where the photoresist is completely removed corresponds to the rest.

S103, using dry etching to remove the polysilicon film in the part where the photoresist is completely removed, to form the polysilicon layer.

Among them, plasma etching, reactive ion etching, inductively coupled plasma etching and other methods can be used for dry etching, and the etching gas can be selected from gases containing fluorine and chlorine, such as carbon tetrafluoride (CF ₄ ), trifluorine Methane (CHF ₃ ), sulfur hexafluoride (SF ₆ ), difluorodichloromethane (CCl ₂ F ₂ ), etc., or a mixed gas of these gases and oxygen (O ₂ ).

S104, using a lift-off process to remove the completely remaining part of the photoresist.

In the embodiment of the present invention, the polysilicon layer is formed by dry etching, because dry etching can control the sidewall profile of the formed polysilicon layer very well, that is, it can control the sidewalls on both sides of the polysilicon layer. The base substrate can be vertical, so that the performance of the finally formed active layer is better, and the influence on the performance of the thin film transistor is avoided.

On the basis of the above, considering that the glass substrate contains harmful substances, such as alkali metal ions, which may affect the performance of the polysilicon layer, the implementation of the present invention is preferably: before forming the polysilicon film, the A buffer layer is formed on the surface of the substrate.

Based on the above description of the preparation method of the polysilicon thin film transistor, the embodiment of the present invention provides a specific embodiment to describe the preparation method of the polysilicon thin film transistor in detail. As shown in Figure 1, the method includes the following steps:

S201 , as shown in FIG. 2 , forming a buffer layer 20 on the base substrate 10 .

Specifically, on a pre-cleaned transparent substrate 10 such as glass, plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), atmospheric pressure chemical vapor deposition (APCVD), electron cyclotron resonance chemical vapor deposition (ECR-CVD) or sputtering and other methods to form the buffer layer 20, which is used to prevent impurities contained in the glass from diffusing into the active layer, so as to prevent the influence on the characteristics such as threshold voltage and leakage current of the thin film transistor element.

Wherein, the buffer layer 20 may be a single layer of silicon oxide, silicon nitride or a stack of both. The thickness of the buffer layer 20 can be The preferred thickness is

When the buffer layer 20 is formed by a deposition method, the deposition temperature is controlled at 600° C. or lower.

In addition, due to the high content of metal impurities such as aluminum, barium, and sodium in traditional alkali glass, the diffusion of metal impurities is easy to occur in the high-temperature treatment process. Therefore, the glass substrate in the embodiment of the present invention is preferably an alkali-free glass.

S202 , as shown in FIG. 2 , on the basis of completing S201 , forming an amorphous silicon thin film 301 on the buffer layer 20 .

Specifically, the amorphous silicon film 301 can be formed by PECVD, LPCVD or sputtering. When the amorphous silicon thin film 301 is formed by a deposition method, the deposition temperature is controlled below 600°C.

Wherein, the thickness of the amorphous silicon film 301 can be The preferred thickness is

S203 , on the basis of completing S202 , soaking or sputtering the amorphous silicon film with a nickel salt solution, so that the nickel salt solution is evenly coated on the surface of the amorphous silicon film.

Specifically, the amorphous silicon thin film is preferably soaked or sputtered with a nickel salt solution having a nickel concentration of 1-1000 μg/mg.

S204. After completing S203, place the substrate formed with the amorphous silicon thin film in an annealing furnace for dehydrogenation treatment.

Specifically, the substrate is kept in an annealing furnace for a certain period of time to reduce the hydrogen content in the amorphous silicon, which usually needs to be controlled below 3%, so as to avoid hydrogen explosion during the subsequent laser annealing process.

Wherein, the dehydrogenation temperature may be 400-600° C., and the treatment time may be 20-120 minutes.

S205 , on the basis of completing S204 , using an excimer laser annealing method to process the amorphous silicon film 301 to crystallize the amorphous silicon film 301 into a polysilicon film 302 as shown in FIG. 3 .

The lasers that can be used in this step are: ArF, KrF and XeCl, the corresponding laser wavelengths are 193nm, 248nm and 308nm respectively, and the pulse width is between 10-50ns. Since the laser wavelength of the XeCl laser is longer, the laser energy is injected deeper into the amorphous silicon film, and the crystallization effect is better, therefore, the embodiment of the present invention preferably uses the XeCl laser.

S206 , on the basis of completing S205 , patterning the polysilicon film 302 to form the polysilicon layer 30 as shown in FIG. 4 .

Specifically, a photoresist film is formed on the polysilicon film 302; and a common mask is used to expose the substrate on which the photoresist film is formed, and after development, a photoresist is completely retained and a photoresist is completely removed part; wherein, the part where the photoresist is completely retained corresponds to the polysilicon layer, and the part where the photoresist is completely removed corresponds to the remaining part; dry etching is used to remove the polysilicon film in the part where the photoresist is completely removed, forming The polysilicon layer; using a stripping process to completely retain and partially remove the photoresist.

Among them, plasma etching, reactive ion etching, inductively coupled plasma etching and other methods can be used for dry etching, and the etching gas can be selected from gases containing fluorine and chlorine, such as CF ₄ , CHF ₃ , SF ₆ , CCl _{2 F2} , etc. or a mixture of these gases with _O2 .

S207 , as shown in FIG. 5 , on the basis of completing S206 , forming a gate insulating layer 40 and a gate electrode 50 .

Specifically, the gate insulating layer 40 may be deposited by methods such as PECVD, LPCVD, APCVD or ECR-CVD. Then, a gate metal layer is formed on the gate insulating layer 40 by sputtering, thermal evaporation or methods such as PECVD, LPCVD, APCVD, ECR-CVD, and the gate electrode 50 is formed by a patterning process.

Wherein, the gate insulating layer 40 may be a single layer of silicon oxide, silicon nitride or a stack of both. The thickness of the gate insulating layer 40 can be The preferred thickness is

The gate electrode 50 can be made of metal, metal alloy such as molybdenum, molybdenum alloy and other conductive materials. Thickness can be The preferred thickness is

S208 , on the basis of completing S207 , perform an ion implantation process on the region of the polysilicon layer 30 corresponding to the source region and the drain region, to form the active layer 60 as shown in FIG. 6 . The active layer 60 includes a source region 601 , a drain region 602 , and a channel region 603 between the source region 601 and the drain region 602 .

Specifically, ion implantation can adopt methods such as ion implantation with a mass analyzer, ion cloud implantation without a mass analyzer, plasma implantation, or solid-state diffusion implantation, and boron-containing materials such as B ₂ H ₆ /H can be used according to design requirements. ₂ , or a mixed gas containing phosphorus such as PH ₃ /H ₂ for implantation, the ion implantation energy can be 10-200keV, preferably 40-100keV, and the implantation dose can be within the range of 1x10 ^{11-1x10 20} atoms/cm ³ , preferably The dose is 1x10 ¹³ -8x10 ¹⁵ atoms/cm ³ .

In addition, activation may be performed by rapid thermal annealing, laser annealing, or furnace annealing after ion implantation. Among them, the furnace annealing method is more economical, simple, and has better uniformity. In the embodiment of the present invention, it is preferred to use an activation heat treatment at 300-600° C. for 0.5-4 hours (preferably 1-3 hours) in the annealing furnace. .

S209 , as shown in FIG. 7 , on the basis of completing S208 , an interlayer insulating layer 70 is formed, and a source electrode 801 and a drain electrode 802 are formed on the interlayer insulating layer 70 . Wherein, the source electrode 801 and the drain electrode 802 are respectively in contact with the source region 601 and the drain region 602 through via holes formed on the interlayer insulating layer 70 and the gate insulating layer 40 .

Specifically, the interlayer insulating layer 70 may be deposited at a temperature below 600° C. by using methods such as PECVD, LPCVD, APCVD or ECR-CVD. Then use sputtering, thermal evaporation or methods such as PECVD, LPCVD, APCVD, ECR-CVD to form a source-drain metal layer on the gate insulating layer, and form the source electrode 801 and drain electrode 802 through a patterning process.

Wherein, the interlayer insulating layer 70 may be a single layer of silicon oxide, or a stack of silicon oxide and silicon nitride. The thickness of the interlayer insulating layer 70 may be The preferred thickness is

When forming the via holes on the interlayer insulating layer 70, dry etching can be used, that is, methods such as plasma etching, reactive ion etching, and inductively coupled plasma etching can be used, and the etching gas can be selected to contain Fluorine and chlorine gases, such as CF ₄ , CHF ₃ , SF ₆ , CCl ₂ F ₂ , etc., or the mixed gas of these gases and O ₂ .

The source electrode 801 and the drain electrode 802 can be made of metal, metal alloy such as molybdenum, molybdenum alloy, aluminum, aluminum alloy, titanium and other conductive materials. Thickness can be The preferred thickness is

When forming the source electrode 801 and the drain electrode 802 through a patterning process, wet etching or dry etching may be used.

Through the above steps S201-S209, a high-quality low-temperature polysilicon thin film transistor can be prepared.

On the basis of the polysilicon thin film transistor formed above, an embodiment of the present invention also provides a method for preparing an array substrate, including:

S301 , as shown in FIG. 8 , on the basis of the above step S209 , a planarization layer 90 is formed, and a pixel electrode 100 electrically connected to the drain electrode 802 is formed on the planarization layer 90 .

Wherein, the material of the planarization layer 100 may be, for example, photosensitive or non-photosensitive resin material, and the thickness may be 1.5 μm˜5 μm.

The material of the pixel electrode 100 may be indium tin oxide (ITO), and the thickness may be

On this basis, the method can also include:

S302 , as shown in FIG. 9 , on the basis of the above S301 , a passivation layer 110 is formed, and a common electrode 120 is formed on the passivation layer 110 .

Here, it is only described by taking different layers of the pixel electrode 100 and the common electrode 120 as an example, but the embodiment of the present invention is not limited thereto, and the pixel electrode 100 and the common electrode 120 are formed in the same layer at intervals.

Certainly, the array substrate provided by the embodiment of the present invention is also used in an OLED display, which will not be repeated here.

The above is only a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Anyone skilled in the art can easily think of changes or substitutions within the technical scope disclosed in the present invention. Should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be determined by the protection scope of the claims.

Claims (10)

1. a preparation method for polysilicon membrane, comprising: on underlay substrate, form amorphous silicon membrane; Adopt quasi-molecule laser annealing method to process described amorphous silicon membrane, making described amorphous silicon membrane crystallization is polysilicon membrane; It is characterized in that, after forming described amorphous silicon membrane, before employing quasi-molecule laser annealing method is processed described amorphous silicon membrane, described method also comprises:

Nickel salt solution processing is carried out in the surface of described amorphous silicon membrane, make described nickel salt solution evenly be applied to the surface of described amorphous silicon membrane.

2. method according to claim 1, is characterized in that, described nickel salt solution processing is carried out in the surface of described amorphous silicon membrane, makes described nickel salt solution evenly be applied to the surface of described amorphous silicon membrane, comprising:

The method that adopts immersion or splash, makes described nickel salt solution evenly be applied to the surface of described amorphous silicon membrane.

3. method according to claim 1, is characterized in that, in described nickel salt solution, the concentration of nickel is 1～1000 μ g/mg.

4. according to the method described in claims 1 to 3 any one, it is characterized in that, after nickel salt solution processing is carried out in the surface of described amorphous silicon membrane, before employing quasi-molecule laser annealing method is processed described amorphous silicon membrane, described method also comprises:

Described amorphous silicon membrane is carried out to dehydrogenating technology processing, make hydrogen content in described amorphous silicon membrane below 3%.

5. a preparation method for polycrystalline SiTFT, comprising: on underlay substrate, form active layer, be positioned at gate insulation layer, gate electrode, source electrode and drain electrode above described active layer; Described active layer comprises source area, drain region, the channel region between described source area and described drain region; Wherein, described active layer is to carry out doping process formation by the region corresponding with described source area and described drain region to polysilicon layer; It is characterized in that,

Described polysilicon layer obtains for the polysilicon membrane described in claim 1 to 4 any one is carried out to composition technique.

6. method according to claim 5, is characterized in that, described polysilicon layer obtains for polysilicon membrane is carried out to composition technique, comprising:

Be formed with on the substrate of polysilicon membrane, forming photoresist film;

Adopt normal masks plate to being formed with the base board to explosure of described photoresist film, after developing, the formation complete reserve part of photoresist and photoresist are removed part completely; Wherein, the complete reserve part of described photoresist is corresponding with described polysilicon layer, and photoresist is removed the corresponding remainder of part completely;

Adopt dry etching to remove the described polysilicon membrane that described photoresist is removed part completely, form described polysilicon layer;

Adopt stripping technology that the complete reserve part of described photoresist is removed.

7. method according to claim 5, is characterized in that, the thickness of described polysilicon layer is

8. according to the method described in claim 5 to 7 any one, it is characterized in that, described method also comprises: before forming described polysilicon membrane, on described underlay substrate surface, form resilient coating.

9. a preparation method for array base palte, comprising: form thin-film transistor and pixel electrode; It is characterized in that, described thin-film transistor forms by the preparation method of the polycrystalline SiTFT described in claim 5 to 8 any one.

10. method according to claim 9, is characterized in that, also comprises formation public electrode.