CN103972235B - Electronic device and forming method thereof - Google Patents

Abstract

The present invention relates to electronic devices and methods of forming them. A method of manufacturing an electronic device includes the following steps. At least one first set of nanowires and liners and at least one second set of nanowires and liners are etched in the SOI layer of the SOI wafer. A first gate stack is formed surrounding at least a portion of each nanowire of the first set of nanowires serving as a channel region of a capacitor device. A second gate stack is formed surrounding at least a portion of each nanowire of the second set of nanowires serving as the channel region of the FET device. Source and drain regions of the FET device are selectively doped. A first silicide is formed on the source and drain regions of the capacitor device, the first silicide extending at least to an edge of the first gate stack. A second silicide is formed on the source and drain regions of the FET device.

Description

Electronic device and method of forming the same

technical field

The present invention relates to capacitors in non-planar device structures, and more particularly, to techniques for forming bidirectional capacitors in an all-around gate nanowire integration flow.

Background technique

Non-field effect transistor (FET) elements such as capacitors and diodes are important elements in complementary metal-oxide semiconductor (CMOS) technology. For example, capacitors are used to store energy in an electric field. Capacitors are also used for power decoupling in analog circuits. Decoupling capacitors are used to reduce noise caused by one or more circuit components.

Much research has been done on planarizing capacitor device structures. See, eg, US Patent Application Publication No. 2011/0108900 Al, filed by Chang et al., entitled "Bi-Directional Self-Aligned FET Capacitor." However, the formation of capacitors in non-planar, fully depleted devices remains a challenge in the industry.

Therefore, techniques for fabricating capacitors in non-planar integrated process flows are desirable.

Contents of the invention

The present invention provides a technique for forming a bidirectional capacitor in an all-around gate nanowire integrated flow. In one aspect of the invention, a method of manufacturing an electronic device is provided. The method includes the following steps. An SOI wafer is provided having an SOI layer on a BOX. Etching at least one first set of nanowires and a first set of liners in the SOI layer and etching at least one second set of nanowires and a second set of liners in the SOI layer, wherein the first set of liners attached to opposite ends of the first set of nanowires in a ladder-like configuration, and wherein the second set of pads is attached to opposite ends of the second set of nanowires in a ladder-like configuration. forming a first gate stack surrounding at least a portion of each nanowire in the first set of nanowires serving as a channel region of a capacitor device, wherein the first set of nanowires Portions of the gate stack extending from the gate stack and the first set of pads serve as source and drain regions of the capacitor device. forming a second gate stack surrounding at least a portion of each nanowire in the second set of nanowires serving as a channel region of a field effect transistor (FET) device, wherein the Portions of the second set of nanowires extending from the gate stack and the second set of pads serve as source and drain regions of the FET device. Source and drain regions of the FET device are selectively doped. A first silicide is formed on the source and drain regions of the capacitor device, the first silicide extending at least to an edge of the first gate stack. A second silicide is formed on the source and drain regions of the FET device.

In another aspect of the invention, another method of manufacturing an electronic device is provided. The method includes the following steps. An SOI wafer is provided having an SOI layer on a BOX. Etching at least one first set of nanowires and a first set of liners in the SOI layer and etching at least one second set of nanowires and a second set of liners in the SOI layer, wherein the first set of liners attached to opposite ends of the first set of nanowires in a ladder-like configuration, and wherein the second set of pads is attached to opposite ends of the second set of nanowires in a ladder-like configuration. forming a first gate stack surrounding at least a portion of each nanowire in the first set of nanowires serving as a channel region of a capacitor device, wherein the first set of nanowires Portions of the gate stack extending from the gate stack and the first set of pads serve as source and drain regions of the capacitor device. forming a second gate stack surrounding at least a portion of each nanowire in the second set of nanowires serving as a channel region of a field effect transistor (FET) device, wherein the Portions of the second set of nanowires extending from the gate stack and the second set of pads serve as source and drain regions of the FET device. The source and drain regions of the FET device and the source and drain regions of the capacitor device are doped. A first silicide is formed on the source and drain regions of the capacitor device, the first silicide extending into an undoped channel region of the capacitor device. A second silicide is formed on the source and drain regions of the FET device.

In yet another aspect of the present invention, an electronic device is provided. The electronic device includes at least one first set of nanowires and first set of liners etched in an SOI layer and at least one second set of nanowires and second set of liners etched in said SOI layer, wherein said A first set of pads is attached to opposite ends of the first set of nanowires in a ladder-like configuration, and wherein the second set of pads is attached to opposite ends of the second set of nanowires in a ladder-like configuration; the first a gate stack surrounding at least a portion of each nanowire of the first set of nanowires serving as a channel region of a capacitor device, wherein nanowires of the first set of nanowires extend from the gate stack Portions of and the first set of pads serve as source and drain regions of the capacitor device, wherein the source and drain regions of the capacitor device are undoped; the second gate stack , which surrounds at least a portion of each nanowire in the second set of nanowires serving as a channel region of a FET device, wherein the portion of the second set of nanowires extending from the gate stack and the The second set of pads are used as source and drain regions of the FET device, wherein the source and drain regions of the FET device are doped; formed on the source of the capacitor device a first silicide on a region and a drain region extending at least to an edge of said first gate stack; and a second silicide formed on a source region and a drain region of said FET device.

In yet another aspect of the present invention, another electronic device is provided. The electronic device comprises at least a first set of nanowires and a first set of pads in an SOI layer of an SOI wafer and at least a second set of nanowires and a second set of pads etched in said SOI layer, wherein said first set of pads is attached to opposite ends of said first set of nanowires in a ladder-like configuration, and wherein said second set of pads is attached to opposite ends of said second set of nanowires in a ladder-like configuration; A first gate stack surrounding at least a portion of each nanowire in the first set of nanowires serving as a channel region of a capacitor device, wherein the nanowires of the first set are drawn from the gate stack The extended portion and the first set of pads serve as source and drain regions of the capacitor device, wherein the source and drain regions of the capacitor device are doped; the second gate stack a layer surrounding at least a portion of each nanowire in the second set of nanowires serving as a channel region of a FET device, wherein the portion of the second set of nanowires extending from the gate stack and The second set of pads serves as source and drain regions of the FET device, wherein the source and drain regions of the FET device are doped; at the source of the capacitor device a first silicide on region and drain regions extending into the undoped channel region of the capacitor device; and a second silicide on the source and drain regions of the FET device thing.

A more complete understanding of the present invention, as well as additional features and advantages of the present invention, will be obtained by reference to the following detailed description and accompanying drawings.

Description of drawings

1A is a cross-sectional view of an all-around gate nanowire capacitor device with doped source and drain regions in accordance with an embodiment of the present invention;

1B is a cross-sectional view of an all-around gate nanowire capacitor device with undoped source and drain regions in accordance with an embodiment of the present invention;

2 is a three-dimensional illustration showing a semiconductor-on-insulator (SOI) wafer having an SOI layer on a buried oxide (BOX) used to fabricate a full enclosure according to an embodiment of the invention. A starting platform for gate nanowire capacitor devices and nanowire field effect transistor (FET) devices;

3 is a three-dimensional diagram showing nanowire hard masks (one corresponding to nanowire capacitor devices and the other corresponding to nanowire FET devices) that have been formed on the SOI layer according to an embodiment of the present invention;

FIG. 4 is a diagram illustrating the first and second sets of nanowires and pads that have been used to pattern a first and second set of nanowires and pads in an SOI layer (i.e., the first set of nanowires/pads corresponds to a nanowire capacitor device, and the second set of nanowires/pads corresponds to a nanowire capacitor device, and the second set of A three-dimensional illustration of a set of nanowires/pads corresponding to the hardmask of a nanowire FET device) and that the hardmask has subsequently been removed;

5 is a three-dimensional illustration showing a nanowire that has been suspended on a BOX by undercutting the BOX below the nanowire and that has been smoothed, in accordance with an embodiment of the invention;

Figure 6 is a three-dimensional graphical representation showing a nanowire that has been thinned according to an embodiment of the present invention;

FIG. 7 is a three-dimensional illustration showing a gate stack that has been formed to surround nanowires in an all-around gate configuration in accordance with an embodiment of the present invention;

8 is a cross-sectional view showing a portion of a gate stack formed in a nanowire capacitor (the same process can be applied to a nanowire FET device) according to an embodiment of the present invention;

9 is a three-dimensional illustration showing spacers that have been formed on opposite sides of a gate stack according to an embodiment of the present invention;

10 is a graph showing exposed portions of nanowires and liners that have been used to thicken nanowires and liners (those portions of nanowires that are not covered by gate stacks or spacers and liners—these portions are used as corresponding A three-dimensional illustration of the selective epitaxial growth of the device's source or drain region);

Figure 11 is a three-dimensional illustration showing contact material that has been formed on exposed epitaxial material in accordance with an embodiment of the present invention;

Figure 12 is a cross-sectional view showing how the resulting contact metal silicide can extend beyond the nanowire capacitor by employing one or more of the present techniques of controlling silicide reaction, according to an embodiment of the present invention The source/drain regions of the device are doped and go into the undoped region of the nanowire capacitor device.

Figure 13 is a cross-sectional view showing how the resulting contact metal silicide remains in the nanowire FET by employing one or more of the present techniques of controlling the silicide reaction, according to an embodiment of the present invention. In the doped source/drain region of the device;

Figure 14 is a cross-sectional view showing how, in accordance with an embodiment of the present invention, by employing one or more of the present techniques of controlling silicide reactions, the resulting amount of contact metal silicide is greater than that in nanometers. The amount of contact metal silicide produced in the line FET device (compared to Figure 13);

15 is a cross-sectional illustration of an enlarged portion of the device of FIG. 1A showing how reducing spacer width increases source/drain regions according to an embodiment of the invention; and

16 is a cross-sectional illustration of an enlarged portion of the device of FIG. 1B showing how the techniques of the present invention may be employed in accordance with embodiments of the present invention to ensure that silicide is formed extending at least to the gate edge of the capacitor device.

detailed description

The present application provides techniques for forming bidirectional capacitor devices in an all-around gate nanowire process flow. First, an overview of the present technology is provided by referring to FIGS. 1A and 1B . According to an exemplary embodiment of the present technology, a bidirectional capacitor device is formed to have one of two exemplary (non-limiting) configurations. In a first configuration shown in FIG. 1A , a bidirectional capacitor device has doped source and drain regions and an undoped channel region. In order to obtain bidirectional operation in this doped source and drain configuration, according to the technique of the present invention, metal contacts (in this case, silicides that will serve as the source and drain electrodes of the device, see below) are intentionally allowed. ) extends across the junction between the doped and undoped regions of the device, which allows the formation of a Schottky junction between the contact metal and the undoped portion of the device.

In a second exemplary configuration shown in Figure IB, the bidirectional capacitor device is undoped, ie, the device has undoped source, drain and channel regions. In this case, to obtain bidirectional operation, the techniques of the present invention are employed to form contact metal (ie, suicide source and drain electrodes) extending at least to the edge of the device gate, which allows the formation of a Schottky junction.

Typically, this process flow involves patterning a plurality of nanowires and pads (labeled "nanowires" and "diffusion pads" in Figures 1A and 1B) in the wafer. A gate surrounding the nanowire is formed in an all-around gate configuration. See Figures 1A and 1B. As shown in FIGS. 1A and 1B , a dielectric may exist between the nanowires and the gate, with spacers formed on opposite sides of the gate.

With respect to the doped source and drain configuration shown in Figure 1A, the liner (and part of the nanowire) was doped using ion implantation and annealing. A portion of each nanowire remains undoped—and will serve as the device's channel region. As highlighted above, in order to obtain bidirectional operation, according to the technique of the present invention, metal contacts (in this case, the silicides that will serve as the source and drain electrodes of the device, see below) are deliberately allowed to extend across the A junction between a doped and an undoped region, which allows the formation of a Schottky junction between the contact metal and the undoped portion of the device. As will be described in detail below, this can be achieved in a number of different ways, either alone or in combination. Schottky junction contacts allow the injection of both types of carriers (electrons and holes), which allows the capacitor to operate in both inversion and accumulation, while normal junction contacts only allow operation in inversion mode and not in accumulation mode down to work. There are several circuit applications, such as on-chip voltage converters, where it is advantageous to have capacitors that operate under both positive and negative bias conditions.

Typically, nanowire capacitors include two "plates." One of the plates formed by the nanowires serves as a channel between the source and drain electrodes. The gate (electrode) serves as the second plate and serves to regulate the flow of current in the channel.

Metal silicide formation involves depositing metal(s) (one or more of Nickel (Ni), Cobalt (Co) and/or Platinum (Pt) on the exposed portion/liner of the nanowire - - eg Nickel Platinum (NiPt)), followed by annealing to react the metal(s) with the silicon in the nanowires and liners. The reaction will depend on the particular reaction conditions employed (eg, annealing temperature, duration, etc.). In the case of a complete reaction, the reaction will stop when the stoichiometric silicide is achieved. However, it is not necessary to form stoichiometric silicides in this process. For example, the techniques of the present invention can be applied even if the annealing conditions (eg, annealing temperature and/or duration) do not allow complete reaction and result in a non-stoichiometric silicide. Non-stoichiometric silicides may result when annealing temperatures and/or durations lower than those that would result in stoichiometric silicides are employed. Non-stoichiometric silicides may be "metal-rich" (ie, silicides contain larger amounts of metal than stoichiometric silicides) and thus consume less silicon in the reaction. Thus, the silicide reaction can be controlled by controlling the amount of metal and/or the amount of silicon available for the reaction. The technique of the present invention employs this concept to control the amount of silicide formed and to ensure that the silicide extends into undoped regions of the device.

Advantageously, the techniques of the present invention allow the selective fabrication of nanowire capacitor(s) on a wafer relative to other devices on the wafer in the fabrication of electronic devices. By way of example only, in one embodiment described below, techniques of the present aspect are used to fabricate nanowire capacitor(s) and nanowire field effect transistors (FETs) on the same wafer. Nanowire FETs essentially operate as diodes (unidirectional operation). Therefore, in the case of nanowire FET diodes, it is desirable that the metal contacts (in which case the suicide will be used as the source and drain electrodes of the device, see below) be formed only in the doped regions of the device. By comparison with nanowire capacitor devices, as described above with reference to FIG. 1A , it is expected that the contact metal is deliberately allowed to extend beyond the doped region of the device and into the undoped region of the device. Advantageously, the techniques of the present invention can be employed to selectively control the amount of silicide formed in a capacitor (to enable bidirectional operation) compared to FET diodes (to enable unidirectional operation).

Specifically, several methods are presented in this application to control the silicide process including 1) using smaller spacers adjacent to the gate (see also the expanded view of the device of FIG. 1A provided in FIG. 12) , 2) provide less silicon (e.g., no epitaxy or reduced epitaxy on liners/nanowires), and/or 3) deposit more (thicker) metal - thus providing more silicon for silicide reactions polymetallic. Each of these methods will be described with reference to the exemplary process flows shown in FIGS. 2-11 for fabricating all-around gate nanowire capacitor devices and nanowire FET diodes on the same wafer.

Regarding the nanowire capacitor device configuration shown in FIG. 1B with undoped source, drain, and channel regions, as highlighted above, in order to obtain bidirectional operation, metal contacts are intentionally allowed (in this case, the The silicide used as the source and drain electrodes of the device, see below) extends at least as far as the gate edge, which allows the formation of a Schottky junction between the contact metal and the (undoped) channel region of the device. The technique of the present invention (i.e., 1) uses smaller spacers adjacent to the gate, 2) provides less silicon, and/or 3) deposits more (thicker) metal—thereby providing The silicide reaction provides more metal) implemented alone or optionally in combination, can be used to trim the silicide formation process and achieve a silicide metal contact extending at least to the edge of the capacitor device gate. Notably, in this exemplary undoped source/drain nanowire capacitor configuration, the silicide can extend beyond the gate edge and into the channel region. See eg Figure 16 (described below). However, it is preferred that the silicide extends at least to the edge of the gate.

By comparison, in the case of nanowire FET diodes, for example, it is desirable to separate the source and drain contacts from the gate edge. The techniques of the present invention can be implemented to efficiently and effectively tailor silicide reactions to, for example, fabricate nanowire capacitors and nanowire FET diode devices on the same wafer.

The techniques of the present invention will now be described in detail with reference to the exemplary process flows shown in FIGS. 2-11 for fabricating a gate-all-around nanowire capacitor device and a gate-all-around nanowire FET diode on the same wafer.

The fabrication process begins with a semiconductor-on-insulator (SOI) wafer. See Figure 2. SOI wafers typically include a layer of semiconductor material separated from a substrate by an insulator (commonly referred to as a semiconductor-on-insulator or SOI layer). When the insulator is an oxide, such as silicon dioxide (SiO ₂ ), it is often referred to as a buried oxide or BOX. According to the technique of the present invention, the SOI layer will be used as the active layer of the device in which the nanowire core and liner will be patterned (see below).

In the example shown in FIG. 2 , the starting wafer includes SOI layer 204 on BOX 202 . For ease of description, the substrate that would normally be located below the BOX 202 is not shown. According to an exemplary embodiment, SOI layer 204 is formed of, for example, silicon (Si) (eg, crystalline silicon), silicon germanium (SiGe), or silicon carbide (SiC). Therefore, the SOI layer 204 may also be referred to as a "semiconductor device layer" or simply as a "semiconductor layer".

According to an exemplary embodiment, SOI layer 204 preferably has a thickness t of about 5 nanometers (nm) to about 40 nm. Commercially available SOI wafers generally have thicker SOI layers. Therefore, the SOI layer of commercial wafers can be thinned using techniques such as oxide thinning to achieve the desired active layer thickness for the inventive technique.

The nanowires will be patterned in the SOI layer. As provided above, the nanowires will be used to form the (undoped) channel region of the device. Therefore, it is preferred that the SOI layer 204 is undoped. Selective doping of the (source/drain) regions of the SOI layer, if and when desired, can be done later in the process. In the example shown in the figure, a nanowire capacitor and a nanowire FET diode are being fabricated on the wafer. This is just an example to illustrate how this process can be used to easily and selectively fabricate two types of devices on the same wafer. Of course, the same technique can be used to fabricate multiple nanowire capacitors and/or nanowire FET diodes (or just nanowire capacitors, if so desired).

The patterning of the nanowires in the SOI layer 204 is now described. As shown in FIG. 3, standard photolithographic techniques are used to form hard masks 302a/302b (also referred to herein as nanowire/pad photolithographic hard masks) that will be used for patterning in SOI layer 204 for Nanowires and pads for nanowire capacitors/nanowire FET diodes. By way of example only, a suitable hardmask material (eg, a nitride material such as SiN) can be deposited over the SOI layer 204 by blanket and then using a footprint with hardmask 302a/302b ) and locations to pattern the hard mask material to form hard masks 302a/302b. As another example (not shown), a soft mask (eg, resist) can also be used to pattern the nanowires and pads in the SOI layer 204 .

As shown in Figure 3, the nanowire/pad hardmasks each have a ladder-like configuration. This ladder-like configuration will be transferred to the active layer, where the nanowires will be patterned like the rungs of a ladder of interconnect pads (see below).

Nanowires and liners are then formed in the SOI layer 204 using etching through the hard mask 302a/302b. See Figure 4. For clarity, the nanowires/pads used to make the nanowire capacitor device(s) may also be referred to herein as the first set of nanowires/pads and used to make the(s) The nanowires/pads of the nanowire FET diode device may also be referred to herein as a second set of nanowires/pads. According to an exemplary embodiment, the etching is performed using reactive ion etching (RIE). For example, the RIE step can be performed using fluorine-containing chemistries (eg, CHF ₃ /CF ₄ ) or bromine chemistries. As shown in FIG. 3, the nanowire/pad hardmask is formed to have a ladder-like configuration. That is, the pads are attached to opposite ends of the nanowires like rungs of a ladder. The hardmask 302a/302b may be removed at this stage using a selective wet etch process.

The nanowires are then suspended on the BOX. See Figure 5. According to an exemplary embodiment, the nanowires are suspended by undercutting the BOX 202 below the nanowires using an isotropic etching process. The process also etches laterally the portion of BOX 202 that is under the liner. See Figure 5. Isotropic etching of BOX 202 may be performed using, for example, diluted hydrofluoric acid (DHF). 100:1 DHF etches about 2-3 nm of BOX layer 202 per minute at room temperature.

After isotropic etching of BOX 202, the nanowires are preferably smoothed to give them an elliptical and in some cases circular cross-sectional shape. Smoothing of the nanowires can be performed, for example, by annealing the nanowires in a hydrogen-containing atmosphere. Exemplary annealing temperatures may range from about 600 degrees Celsius (° C.) to about 1000° C., and hydrogen pressures of about 600 Torr to about 700 Torr may be employed. Exemplary techniques for suspending and reshaping nanowires can be found, for example, in U.S. Patent Application No. 7,884,004, issued to Bangsaruntip et al., entitled "Maskless Process for Suspending and Thinning Nanowires," which is incorporated by reference in its entirety. In this application. During this smoothing process, the nanowires are thinned. According to an exemplary embodiment, the nanowires at this stage have an elliptical cross-sectional shape with a cross-sectional diameter of about 7 nm to about 35 nm.

Optionally, the nanowires can be further thinned. See Figure 6. As described in connection with the description of FIG. 5 , the nanowires may be reshaped (eg, smoothed) into an elliptical (eg, circular) cross-sectional shape earlier in the process. Now, the nanowires can be thinned even further, which can also be used to give them a smoother surface.

By way of example only, the nanowires may also be thinned in this step using high temperature (eg, about 700°C to about 1000°C) oxidation of the nanowires followed by etching of the grown oxide. This oxidation and etching process can be repeated x times to achieve the desired nanowire size. According to an exemplary embodiment, the nanowire at this stage after further thinning has a cylindrical cross-sectional shape with a cross-section of about 2 nm to about 20 nm, such as about 3 nm to about 10 nm diameter.

Gate stacks 702a/702b are then patterned around the nanowires in an all-around gate configuration in nanowire capacitor and nanowire FET diode devices, respectively. See Figure 7. This gate stack will surround a portion of each nanowire that will serve as the channel region of the device. The portion of the nanowire extending from the gate stack and liner will serve as the source and drain regions of the device. In this example, each gate stack includes a dielectric (or combination of dielectrics) all surrounding the nanowire, a first gate material (eg, metal(s)), and optionally a second gate material (eg a metal or doped polysilicon layer) (see Figure 8 described below, which provides a cross-sectional view through one of the gate stacks). As shown in FIG. 7, since the nanowires have been suspended above the BOX as described above, the gate stacks 702a/702b completely surround at least a portion of each nanowire in an all-around gate configuration.

For ease of description, the formation of gate stack 702a in a nanowire capacitor device is shown in FIG. 8, it being understood that the same process can be employed in the same manner to form gate stack 702b in a nanowire FET diode device. . For example, the same gate stack configuration can be used for both nanowire capacitor and nanowire FET diode devices. However, this is not required and specific tailoring of the gate stack material can be employed in each device if so desired. Given this description, one skilled in the art will be able to configure the gate stack material/configuration for a particular given application.

As shown in Figure 8, which provides a cross-sectional view (ie, along line AA') through a portion of the gate stack 702a, according to an exemplary embodiment, by depositing a conformal gate The gate stack 702a/702b is formed by a dielectric film 802, such as silicon dioxide (SiO ₂ ), silicon oxynitride (SiON), or hafnium oxide (HfO ₂ ) (or other high-K materials ). Optionally, a second conformal gate dielectric film 804 comprising, for example, HfO ₂ may be applied on the gate dielectric film 802 . A (first) gate material 806 is then deposited on the conformal gate dielectric film 802 (or on the optional second conformal gate dielectric film 804). According to an exemplary embodiment, the gate material 806 is a conformal metal gate film comprising, for example, tantalum nitride (TaN) or titanium nitride (TiN).

Optionally, a second gate material 808 such as doped polysilicon or metal can then be blanket deposited over the structure (ie, over the gate material 806 to surround the nanowires). With reference to FIG. 7, a hard mask 710a/710b (e.g., a nitride hard mask such as SiN) can then be formed on the second gate material 808, wherein the hard mask 710a corresponds to the gate lines of the nanowire capacitor device And the hard mask 710b corresponds to the gate line of the nanowire FET diode device. The hardmask 710a/710b may be formed using standard patterning techniques. The gate material(s) and dielectric(s) are then etched by directional etching, resulting in straight sidewalls of the gate stack 702a/702b as shown in FIG. 7 . Any remaining hard mask on the gate stack, if present, is also removed by etching. An isotropic lateral etch is then performed to remove the remainder of the gate material beneath the nanowires masked in the first directional etch (not shown). This process can be done by RIE or chemical wet method. After the lateral etch step, gate stacks 702a/702b are formed on the suspended nanowires in the nanowire capacitor and nanowire FET diode devices, respectively.

Spacers 902a/902b are formed on opposite sides of the gate stacks 702a/702b, respectively. See Figure 9. According to an exemplary embodiment, the spacers 902a/902b are formed by depositing a blanket dielectric film, such as silicon nitride, and etching the dielectric film by RIE from all horizontal surfaces. As shown in Figure 9, some of the deposited spacer material may remain in the undercut region because RIE in that region is blocked by the liner.

Spacers 902a/902b are used to separate the gate from the source and drain regions. In accordance with the techniques of the present invention, the dimensions of spacers 902a and/or spacers 902b may be tailored based on the requirements of the silicide reaction. As highlighted above, this is the first method described in this application for controlling the silicide reaction. Basically, the size of the spacers 902a/902b affects how much metal can be deposited on the source and drain regions of the corresponding device (see below). In the present application, the size of the spacer 902a/902b is characterized based on the width wa and wb of the spacer spacer 902a/902b, respectively. Thus, for example, by reducing the spacer width in a nanowire capacitor device from wa1 to wa2 (where wa2 is smaller than wa1 ), a larger area will be provided for the deposition of suicide metal. As noted above, for a given set of reaction conditions and a given amount of silicon used for the reaction, depositing more metal will cause the silicide reaction to proceed further from the source and drain regions into the device structure. In a nanowire capacitor device configuration with doped source and drain regions (see Figure 1A), this means that the silicide reaction can be tailored to proceed with the doped (source/drain) regions, preferably depleting Silicon from the undoped (channel) region of the device, which lies between the doped regions. As mentioned above, ensuring that the silicide formed extends from the doped region of the device to the undoped region of the device is the goal of doped source and drain nanowire capacitor devices. In a nanowire capacitor device configuration with undoped source and drain regions (see Figure 1B), this means that the silicide reaction can be tailored to proceed at least to the edge of the gate (and potentially beyond the gate edge and into the (undoped) channel region).

According to an exemplary embodiment, a block mask (not shown) is employed in the spacer RIE process to generate spacers with different widths. The shield mask can be patterned with the footprint (including size, eg width) and location of the spacers using standard photolithographic techniques.

By comparing with nanowire FET diode devices (with unidirectional operation) as described above, it is expected that the source/drain contact metal (ie, suicide) will remain in the undoped region of the device. It is worth noting that for a nanowire FET diode configuration, the source and drain regions are preferably always doped. Therefore, if this technique of tailoring spacer widths is employed (alone, or in combination with one or more of the other techniques for controlling silicide reactions provided in this application), the spacing of the nanowire capacitor device The object width wa will be smaller than the spacer width wb for the nanowire FET device, ie wa<wb, to ensure a larger amount of metal is deposited and a larger amount of silicide is formed in the nanowire capacitor compared to the nanowire FET diode. This technique of trimming the spacer width is further illustrated in Stackup Figure 12, described below.

It is worth noting that the silicide reaction is dependent on a variety of application-specific factors including, but not limited to, the specific silicide metal(s) employed, the stoichiometry and crystal structure of the silicide formed, the annealing time and annealing temperature. See, e.g., U.S. Patent No. 6,124,639 to Domenicucci et al., entitled "Flat Interface for a Metal-Silicon Contact Barrier Film" (hereinafter "Domenicucci"), which is hereby incorporated by reference in its entirety . Thus, for a particular device and device configuration, including particular materials and process parameters, the width of spacers 902a and/or 902b can be adjusted until an appropriate amount of silicide is produced (based on the amount of metal that can be deposited - see above).

Specifically, factors such as the particular silicide metal(s) employed, the stoichiometry and crystal structure of the silicide formed, the annealing time, and the annealing temperature affect the silicon-to-metal ratio consumed to form the stoichiometric silicide. To form a stoichiometric silicide, the amount of metal should be greater than the amount of silicon divided by the silicon-to-metal ratio consumed to form the stoichiometric silicide. See, e.g., U.S. Patent No. 6,387,803 to Talwar et al., entitled "Method for Forming a Silicide Region on a Silicon Body" (hereinafter "Talwar"), which is incorporated by reference in its entirety in this application . The amount of silicon and metal can be quantified based on the thickness of the respective layers (for example, the thickness of the initial silicon layer and the thickness of the metal are considered), since the metal will consume a fixed amount of silicon during the silicide reaction.

Optionally, a selective epitaxial material such as Si, SiGe, or SiC (labeled "Epi") is then grown to thicken the exposed portions of the nanowires and liners (i.e., those not covered by gate stacks or spacers). those parts). See Figure 10. This step is optional and can be selectively applied to one or more devices on the wafer (regardless of the other device(s)). For example, as will be described in detail below, in the case of nanowire capacitor devices, the amount of silicon present for silicide reactions can be tailored such that less or no epitaxial silicon is required. However, it is desirable to form epitaxial silicon (or more epitaxial silicon) in the source and drain of the nanowire FET diode device(s), if present. In this way, more silicon is available for silicide reactions in the doped source/drain regions of the nanowire FET diode device(s) compared to the nanowire capacitor device. Thus, in the case of nanowire FET diode devices, more silicon in the source/drain regions is available for silicide reactions, which will help ensure that silicides do not extend beyond the doped regions of the device. Conversely, in the case of nanowire capacitor devices, less silicon is available for silicide reactions in the source/drain regions, which will help ensure that silicide formation extends beyond the doped regions of the device and into the undoped regions of the device. The impurity region (in the case of a nanowire capacitor device configuration (see Figure 1A) with doped source and drain regions) or at least extends to the gate edge (in the case of a nanowire capacitor device configuration with undoped source and drain region of the nanowire capacitor device configuration (see Figure 1B) for the case).

Accordingly, embodiments are contemplated in this application where the epitaxial material is grown to selectively thicken only the exposed portions (i.e., not gated) of the nanowires and pads in the nanowire FET diode device(s). electrode stacks or those covered by spacers) so that no epitaxial material is formed in the capacitor device. Furthermore, as provided above, it will be within the ability of those skilled in the art to tailor the process to achieve selective epitaxial growth in one or more devices. In this case, the source and drain regions of the nanowire capacitor may be undoped (whereas the source and drain regions of the nanowire FET are doped). In the case of undoped nanowire capacitor devices, the same principles described in this application for tailoring the spacer width, tailoring the amount of metal available for silicide reactions, and/or tailoring the amount of silicon available for silicide reactions can be applied. craft. That is, by tailoring the amount of silicide produced, it is expected that a larger amount of silicide produced in a nanowire capacitor device than in a nanowire FET device will have an effect on the extrinsic (external) resistance of the capacitor.

The growth process may involve epitaxial growth, eg, in situ doped Si, SiGe or SiC, which may be n-type or p-type doped. The in-situ doped epitaxial growth process forms the doped regions of the nanowire capacitor device. Referring to FIG. 1A, it is shown that these doped regions have a hatched pattern. In contrast, FIG. 1B shows that the source and drain regions in the capacitor device are undoped. It is worth noting that in either case, if the nanowire FET diodes are co-fabricated on the same wafer, the diodes will preferably have doped source and drain regions.

By way of example only, epitaxial growth can be performed using a chemical vapor deposition (CVD) reactor. For example, for silicon epitaxy, precursors include, but are not limited to, SiCl4, _SiH4 in combination with HCL _. The use of chlorine allows selective deposition of silicon only on exposed silicon. The precursor for SiGe growth can be _GeH4 , which can achieve deposition selectivity without HCL. Precursors for dopants may include PH ₃ or AsH ₃ for n-type doping and B ₂ H ₆ for p-type doping. Deposition temperatures may range from about 550°C to about 1000°C for pure silicon deposition and as low as 300°C for pure Ge deposition.

According to an exemplary embodiment, a block mask (not shown) is employed during the epitaxy step to selectively form epitaxy regions of varying size/amount. The block mask can be formed using standard photolithographic techniques. For example, a block mask can be formed on the source and drain regions of the capacitor device(s) and thus epitaxy can be selectively grown on the source region of the nanowire FET diode device(s) and on the drain region. If undoped nanowire capacitor source and drain regions are targeted (see, e.g., Figure 1B), the epitaxy process can end here, with the result that a larger amount of silicon (due to epitaxy) is present compared to nanowire capacitor devices. in the source and drain regions of the nanowire FET diode, thus ensuring that the silicide reaction proceeds further in the nanowire capacitor device. By not performing epitaxy on the source and drain regions of the capacitor device(s), these regions will remain undoped (see FIG. 1B ).

On the other hand, if doped nanowire capacitor source and drain regions are the target (see, e.g., FIG. Epitaxy is performed on the source and drain regions. Therefore, due to the multiple rounds of epitaxy on the source and drain regions of the nanowire FET diode device(s), it is comparable to a nanowire capacitor device(s) that undergoes only one round of epitaxy based on the process described above. More epitaxial material will be formed in these regions than in the source and drain regions. Furthermore, this will ensure that the silicide reaction proceeds farther in the nanowire capacitor device.

As provided above, the amount of silicon present for the silicide reaction can be selectively tailored to ensure that: 1) in the case of nanowire capacitor(s), the formed silicide is free from doped The doped (source/drain) regions extend into the undoped region of the device (in the case of a nanowire capacitor device configuration with doped source and drain regions (see FIG. 1A )) or at least to the gate edge (in the case of a nanowire capacitor configuration with undoped source and drain regions (see Figure 1B)); 2) at the edge of the (one or more) nanowire FET diodes (if present) In this case, silicide formation is restricted to the doped (source/drain) regions of the device. Because, as stated above, for a given set of reaction conditions and a given amount of deposited metal, varying the amount of silicon present for the reaction will affect the amount of silicide produced. For example, in the case of a nanowire capacitor device(s), reducing the amount of silicon present for the reaction will allow the silicide reaction to proceed through the doped (source/drain) regions, preferably consuming Silicon located in the undoped (channel) region of the device (in the case of a nanowire capacitor device configuration (see Figure 1A) with doped source and drain regions), or depleting silicon at least to the gate Edge (in the case of a nanowire capacitor device configuration (see FIG. 1B ) with undoped source and drain regions). Employing a greater amount of silicon in the nanowire FET diode device(s) - if present (again, for a given amount of deposited metal) will limit the silicide reaction to the doped source and drain regions of the device Area. A simple example can be used to illustrate the concept. If X amount of metal is present in the source/drain region of both the nanowire capacitor device and the nanowire FET diode device, and if Y amount of silicon is present in the source/drain region of the nanowire capacitor device and in the nanowire FET Z amount of silicon is present in the diode device, where Y<Z, and the silicide reaction is performed under the same conditions (annealed at the same temperature for the same duration) in both devices, then outside the source/drain regions A larger amount of silicide can form in the source/drain regions of the nanowire FET device before the silicon is consumed. Ideally, the amount of metal/silicon present in each device for the reaction is tailored such that the reaction under a given set of conditions (i.e., annealing temperature/duration) yields: 1) from (one or more a) the doped source/drain regions of the nanowire capacitor device extending to the silicide in its undoped region (in the case of a nanowire capacitor device configuration with doped source and drain regions (see Fig. 1A)), or consume silicon up to the gate edge (in the case of a nanowire capacitor device configuration with undoped source and drain regions (see Figure 1B)); and 2) only at (one or more a) silicide in the source and drain regions of a nanowire FET diode device. Therefore, the amount of epitaxial silicon formed in this step - if present (see above) - depends on the desired end result silicide reaction. In practice, the amount of epitaxial silicon formed can be controlled by growth time and temperature (growth temperature affects growth rate), and can be tailored by one of ordinary skill in the art so that in nanowire capacitor device(s) compared to Different amounts of epitaxial silicon were produced in the nanowire FET diode device(s).

As noted above, the silicide reaction depends on a variety of application-specific factors, including, but not limited to, the particular silicide metal(s) employed, the stoichiometry and crystal structure of the silicide formed, annealing time, and annealing temperature. See eg Domenicucci. These factors affect the silicon-to-metal ratio consumed to form the stoichiometric silicide. Thus, for a particular device and device configuration, including particular materials and process parameters, the amount of epitaxial silicon formed can be adjusted until an appropriate amount of silicide is produced. Determining the amount of epitaxial silicon will be within the capabilities of those skilled in the art.

It is worth noting that the methods described in this application for trimming a silicide process do not have to be used independently of each other. For example, the technique of trimming the spacer width described above can be used alone or with the method now described for controlling the amount of epitaxial silicon available for reaction and/or the method described below for depositing larger silicon for silicide reactions. / less metal method combination. By way of example only, it may be the case (for a given set of parameters) that scaling down the spacer width increases the amount of silicide formed that extends into the nanowire capacitor device(s), but not sufficiently (ie, the silicide does not extend far enough beyond the doped/undoped junction or to the edge of the gate). Thus, a reduction in the amount of silicon used for the silicide reaction and/or an increase in the amount of deposited metal can additionally be employed (as described above) to further fine tune the reaction.

Finally, the contact material, in this case silicide 1102a/1102b (formed from epitaxial Si, SiGe or SiC - in regions where optional epitaxy is performed, and/or from nanowire/liner SOI material - - in the non-epitaxial regions) formed on the exposed nanowire/liner material (with or without epitaxial material thereon). See Figure 11. Notably, FIG. 11 depicts an exemplary situation in which epitaxial material is grown on the source and drain regions of both nanowire capacitor and nanowire FET diode devices. This is exemplary only because, as mentioned above, in some embodiments, no epitaxy is performed on the source and drain regions of the capacitor device(s). Furthermore, as highlighted above, the amount of epitaxial material, if formed on the two types of devices, can be selectively different in order to control the silicide reactions now described.

Examples of contact materials include, but are not limited to, nickel silicide, cobalt silicide, or platinum silicide. By way of example only, the formation temperature may be from about 400°C to about 600°C. As mentioned above, the silicide process involves reacting deposited metal(s) (eg nickel and/or cobalt) with silicon (eg SOI nanowire/liner material and/or epitaxy formed in a previous step silicon). By employing the techniques of the present invention for forming a nanowire capacitor device(s) (for forming a bidirectional nanowire capacitor), it is desired that the silicide be formed to extend across the doped (source/drain) regions of the device and extends into the undoped (nanowire channel) region of the device (in the case of a nanowire capacitor device configuration with doped source and drain regions (see Figure 1A)) or at least to the gate edge (in The case of the nanowire capacitor device configuration with undoped source and drain regions (see FIG. 1B)). In contrast, for the formed nanowire FET diode device(s), it is desirable to confine silicide formation to the doped source/drain regions of the device.

As provided above, the amount of metal present for the silicide reaction can be tailored to ensure that the silicide formed extends from the device doped (source/drain) regions of the nanowire capacitor device(s) to the device's in the undoped region (in the case of a nanowire capacitor device configuration with doped source and drain regions (see Figure 1A)), or at least extending to the gate edge (in the case of a In the case of the nanowire capacitor device configuration in the drain region (see FIG. 1B ), the doped source/drain regions of the nanowire FET device(s) remain. For a given set of reaction conditions (annealing temperature/duration) and a given amount of silicon, increasing/decreasing the amount of metal present will alter the silicide reaction. An example similar to the one provided above can be used to illustrate the concept. If X amount of silicon is present in the source/drain region of both the nanowire capacitor device and the nanowire FET diode device, and if Y amount of metal is present in the source/drain region of the nanowire capacitor device and in the nanowire FET In the presence of Z amount of metal in the diode device, where Y>Z, and the silicide reaction is performed under the same conditions (annealing at the same temperature for the same duration) in both devices, the source/ A larger metal-to-silicon ratio in the drain region will cause silicon outside the source/drain region to be consumed in the reaction. Ideally, the amount of metal/silicon present in each device for the reaction is tailored such that the reaction under a given set of conditions (i.e., annealing temperature/duration) yields: 1) from (one or more 1) the doped source/drain region of the nanowire capacitor device extends into the silicide in its undoped region, or at least to the gate edge; and 2) only in the nanowire(s) Silicide in the source and drain regions of FET diode devices. As illustrated in the example immediately above, increasing the amount of metal present can be used to allow silicide reactions to proceed through the source/drain regions, preferably consuming silicon in undoped regions of the device. Therefore, the amount of metal deposited in this step depends on the desired end result silicide reaction.

As noted above, the silicide reaction depends on a variety of application-specific factors, including, but not limited to, the particular silicide metal(s) employed, the stoichiometry and crystal structure of the silicide formed, annealing time, and annealing temperature. See eg Domenicucci. These factors affect the silicon-to-metal ratio consumed to form the stoichiometric silicide. Thus, for a particular device and device configuration, including particular materials and process parameters, the amount of deposited metal can be adjusted until an appropriate amount of silicide is produced. Determining the amount of metal to be deposited will be within the ability of those skilled in the art.

As shown in FIG. 11, in this step, silicide is also formed on the gate stack to form the gate electrode. This is the desired result. However, it may not be desirable to deposit any additional metal on the gate stack, and/or it may not be desirable to deposit any additional metal on the nanowire FET diode device(s), if present. By comparison, as noted above, it may be desirable to deposit additional silicide-forming metal on the source/drain regions of the nanowire capacitor device(s) to ensure that the resulting silicide extends to the undoped (channel (Figure 1A) or ensure that the resulting silicide extends at least to the gate edge (Figure 1B).

According to an exemplary embodiment, a shadow mask (not shown) is employed during the suicide metal deposition process in nanowire capacitor device(s) compared to nanowire FET diode(s) Various amounts of metal were deposited in the device for source/drain contact formation. The shield mask can be patterned using standard photolithographic techniques. For example, a block mask can be formed to block the source and drain regions of the nanowire FET diode device(s) and thus allow the source and drain regions of the nanowire capacitor device(s) to Silicide metal is selectively deposited on the region. The block mask can be removed and a second deposition of suicide metal can be performed on the nanowire capacitor and nanowire FET diode devices simultaneously. The result will be a larger amount of silicide metal deposited on the nanowire capacitor device(s) since the nanowire capacitor device(s) will go through multiple metal deposition steps while the (one or more) Multiple) nanowire FET diode devices will only undergo a single metal deposition step due to the shadow mask. This will ensure that the silicide formed will extend farther into the device from the source and drain regions of the capacitor device(s) than the nanowire FET diode device(s).

Furthermore, the methods described in this application for trimming a silicide process do not have to be used independently of each other. For example, the techniques described above for tailoring spacer widths and/or controlling the amount of epitaxial silicon can be used alone or in combination with the now described method for controlling the amount of metal available for reaction.

Similar to FIG. 1A, FIG. 12 is a cross-sectional profile view of a nanowire capacitor device structure of the present invention, for example, along line A1-A2 in an exemplary configuration in which both the source region and the drain region of the capacitor device are doped (see FIG. 11) Cross-sectional profile of the nanowire capacitor device. As shown in FIG. 12, based on employing one or more of the methods of controlling silicide reactions described above, the resulting contact metal silicide extends beyond the doped (source/drain) regions of the nanowire capacitor device and into Undoped (channel) region of a nanowire capacitor device. As in FIG. 1A , doped regions are indicated with hatched patterns. The silicide regions are outlined with dashed lines.

As emphasized throughout the specification, the techniques of the present invention can be used to selectively enable bidirectional operation in nanowire capacitor devices compared to other unidirectional devices fabricated on the same wafer (eg, nanowire FET diode devices). This selectivity is achieved by creating the following silicides: 1) silicides extending from the doped source/drain regions of the nanowire capacitor device(s) into its undoped regions (with doped source regions In the case of a nanowire capacitor device configuration with undoped source and drain regions (see Figure 1A)), or at least the silicide extending to the gate edge (in the case of a nanowire capacitor device configuration with undoped source and drain regions case (see FIG. 1B)); and 2) silicide only in the source and drain regions of the nanowire FET diode device(s). 13 is a cross-sectional view of a nanowire FET diode device structure of the present invention, for example, a cross-sectional view of a nanowire FET device along line B1-B2 (see FIG. 11 ). As shown in FIG. 13, the resulting contact metal silicide remains in the doped (source/drain) regions of the nanowire FET diode device based on employing one or more of the methods described above for controlling the silicide reaction. . As in Fig. 1, doped regions are indicated by hatching patterns. The silicide regions are outlined with dashed lines.

As mentioned above, according to some exemplary embodiments provided in the present application, the source region and the drain region of the nanowire capacitor device(s) are undoped, and the nanowire capacitor(s) The source and drain regions of the line FET diode devices are selectively doped. In this example, techniques of trimming spacer widths and/or trimming the amount of metal available for silicide reactions and/or trimming the amount of silicon available for silicide reactions are employed in the (one or more) A greater amount of silicide is generated in the nanowire capacitor device(s) than in the nanowire FET device(s), thereby ensuring that the silicide generated in the nanowire capacitor(s) extends at least as far as the gate extreme edge. As mentioned above, this will have a beneficial effect on the extrinsic (external) resistance of the capacitor. Also as provided above, the silicide reaction, e.g. based on the reaction conditions (e.g., annealing duration, temperature, etc.), can proceed completely, resulting in a stoichiometric silicide, or it can be an incomplete reaction, e.g., forming a metal-rich silicide . Regardless, for a given set of silicide reaction conditions (assuming the same silicide reaction conditions are used for the nanowire FET device(s) as for the nanowire capacitor device(s), using the present invention The technique will result in a larger amount of silicide formation in nanowire capacitor devices than in nanowire FET diode devices. The amount of silicide formed can be readily quantified using conventional analytical methods to verify the results of the inventive process.

14 is a cross-sectional view of a nanowire capacitor device structure of the present invention, for example, a cross-sectional view of a nanowire capacitor device along line A1-A2 (see FIG. 11). In FIG. 14, by comparison with the plot shown in FIG. 12, an exemplary configuration is shown in which the nanowire capacitor device is undoped. As shown in FIG. 14, based on employing one or more of the above methods of controlling silicide reactions, the resulting amount of contact metal silicide is greater than that formed in the nanowire FET device(s) ( Compare the cross-sectional view of the nanowire capacitor device shown in FIG. 14 with the cross-sectional view of the nanowire FET shown in FIG. 13). By referring to FIG. 13, it is worth noting that the source and drain regions of the nanowire FET in this example are doped and the silicide formed therein remains in the doped regions. As described above, the nanowire FET diode can be selectively trimmed by selectively doping the source and drain regions of the nanowire FET diode (with respect to the nanowire capacitor, which remains undoped), and selectively trimming This particular configuration is achieved in comparison to the spacer width in the nanowire capacitor, the amount of metal available for the silicide reaction, and/or the amount of silicon available for the silicide reaction. In FIG. 14, the silicide regions are outlined with dashed lines. As shown in Figure 14, the silicide region extends at least to the gate edge, and indeed in this case the silicide region extends past the gate edge and into the channel region of the device.

Once the contact metal formation has taken place, a capping layer and vias for connections (not shown) can be formed.

15 is a cross-sectional view of an enlarged portion of the device of FIG. 1A. In particular, Figure 15 shows how changing (in this case, decreasing) the spacer width w can change (in this case, increasing) the source/drain regions. By changing (decreasing/increasing) the source/drain regions, more or less silicide-forming metal can be deposited. Referring to FIG. 15, by reducing the width of the spacers from wl to w2, where w2 is smaller than wl, the area available for metal (silicide) deposition is increased from a1 to a2. Since FIG. 15 depicts an enlarged portion of the device of FIG. 1A, some symbols are omitted in FIG. 15 for ease of description and clarity of description, and it should be understood that the structures and features shown in FIG. 15 are similar to those shown in FIG. 1A. Figure, and described above.

16 is a cross-sectional view of an enlarged portion of the device of FIG. 1B depicting a capacitor configuration in which the source and drain regions are undoped. Specifically, FIG. 16 shows how, by employing one (or more) of the techniques provided in this application for controlling silicide reactions, the silicide regions (outlined in dashed lines) can be trimmed to extend to (or beyond) the gate edge. Since FIG. 16 depicts an enlarged portion of the device of FIG. 1B , some symbols are omitted in FIG. 16 for ease of description and clarity of description. It should be understood that the structures and features shown in FIG. 16 are similar to those shown in FIG. 1B Figure, and described above.

Furthermore, the desired dimensions of the nanowire (measured based on the nanowire diameter or Dnw) and the gate (measured based on the gate length or Lg) will likely differ from the corresponding desired dimensions of the FET diode device. In order to build a larger capacitance, it is possible that the length of the gate line will be longer. If accuracy is important, use larger diameter wire where the capacitance per unit area is constant, see below. If it is more important to achieve large capacitance values in a fixed size region, then smaller diameter wires (with aggressive wire-to-wire pitch) will be used. Referring again to FIGS. 12 and 13 , nanowire diameters and Gate length dimension.

Regarding nanowire diameter and capacitance, nanowires with larger diameters (eg, about 8 nm to about 30 nm, or larger) have capacitive properties like FETs, where the capacitance acts around the nanowire. However, when the nanowire diameter is small (eg, from about 2 nm to about 7 nm), there is a bias between non-planar (eg, FET) devices. See, eg, "Gate-all-around Silicon Nanowire 25-Stage CMOS Ring Oscillators with Diameter Down to 3nm" by S. Bangsaruntip et al. (2010symposium on VLSI Technology (VLSIT), pp. 21-22 (August 23, 2010)) ( referred to herein as "Bangsaruntip"), the entire contents of which are incorporated into this application by reference. Bangsaruntip describes a PIN (p-doped source, intrinsic channel, n-doped drain) structure that is electrically similar to the nanowire capacitor device of the present invention but has a different physical structure. However, the device of the present invention will function with the same characteristics. Specifically, Figure 4a of Bangsaruntip shows capacitance measurements of nanowires varying in diameter from 2.6 nm to 15.8 nm, where the gate-source voltage (V _GS ) is plotted on the x-axis and the gate capacitance (C _G ) The ratio to gate length (L _G ), measured in femtofarads (fF)/micrometer (μm), is plotted on the y-axis.

Capacitance C can be calculated as follows:

$\frac{\mathrm{<span\; class="notranslate">\; C</span>}}{\mathrm{<span\; class="notranslate">\; A</span>}}<span\; class="notranslate">\; \&Proportional;</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; r</span>}\mathrm{<span\; class="notranslate">\; l</span>}\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; +</span>\frac{\mathrm{<span\; class="notranslate">\; t</span>}\mathrm{<span\; class="notranslate">\; o</span>}\mathrm{<span\; class="notranslate">\; x</span>}}{\mathrm{<span\; class="notranslate">\; r</span>}}<span\; class="notranslate">\; )</span>}$

where A is the area and r is the radius. In the case of nanowires with smaller diameters (e.g., about 2 nm to about 7 nm), the C/A of the nanowires deviates from the planar limit and shows a dependence on the nanowire size (diameter), which is expected for cylindrical capacitors of. See, e.g., Fig. 4b of Bangsaruntip, which shows the in-plane limit of nanowire capacitance as a function of nanowire diameter, where nanowire width (W _E ) is plotted on the x-axis and C/A (in microfarads (μF)/ Measured in square centimeters (cm ² )) are plotted on the y-axis. The parasitic capacitance in the RO structure is approximately half of the total capacitance. Ideally, to overcome the variation in nanowire diameter, the dimensions of the nanowires in the array are chosen such that the variation in capacitance with nanowire diameter is minimized.

Although illustrative embodiments of the present invention have been described herein, it should be understood that the present invention is not limited to those specific embodiments, and that various other embodiments can be made by those skilled in the art without departing from the scope or spirit of the invention. Variations and Modifications.

Claims (29)

1. A method for manufacturing an electronic device, comprising the steps of: providing an SOI wafer having an SOI layer on the BOX; Etching at least one first set of nanowires and a first set of liners in the SOI layer and etching at least one second set of nanowires and a second set of liners in the SOI layer, wherein the first set of liners attached to opposite ends of the first set of nanowires in a ladder-like configuration, and wherein the second set of pads is attached to opposite ends of the second set of nanowires in a ladder-like configuration; forming a first gate stack surrounding at least a portion of each nanowire in the first set of nanowires serving as a channel region of a capacitor device, wherein the first set of nanowires Portions of the gate stack extending from the gate stack and the first set of pads serve as source and drain regions of the capacitor device; forming a second gate stack surrounding at least a portion of each nanowire in the second set of nanowires serving as a channel region of a field effect transistor (FET) device, wherein the Portions of the second set of nanowires extending from the gate stack and the second set of pads serve as source and drain regions for the FET device; selectively doping the source and drain regions of the FET device; forming a first silicide extending at least to an edge of the first gate stack on the source and drain regions of the capacitor device; and A second silicide is formed on the source and drain regions of the FET device. 2. The method of claim 1, wherein the step of selectively doping the source and drain regions of the FET device comprises the steps of: Masking the source and drain regions of the capacitor device allows the source and drain regions of the capacitor device to remain undoped. 3. The method of claim 1, wherein the step of forming the first silicide on the source and drain regions of the capacitor device comprises the steps of: Depositing a given amount of at least one metal on the source and drain regions of the capacitor device such that once the at least one metal is in contact with the source and drain regions of the capacitor device silicon reaction, the formed first silicide extends at least to the edge of the first gate stack. 4. The method of claim 3, wherein the at least one metal is selected from the group comprising nickel, cobalt, platinum, and combinations comprising at least one of the foregoing metals. 5. The method of claim 3, wherein said at least one metal is deposited on said source and drain regions of said capacitor device in a plurality of deposition steps until all of said capacitor device is achieved. The given amount of the at least one metal on the source and drain regions. 6. The method of claim 5, wherein during at least one of the plurality of depositing steps, the source and drain regions of the FET device are masked using a masking mask. 7. The method of claim 1, wherein the step of forming the second silicide on the source and drain regions of the FET device comprises the steps of: Depositing a given amount of at least one metal on said source and drain regions of said FET device such that once said at least one metal is combined with said source and drain regions of said FET device If silicon is reacted, the second silicide formed remains in the doped source and drain regions of the FET device. 8. The method of claim 3, further comprising the steps of: Spacers are formed on opposite sides of the first gate stack. 9. The method according to claim 8, further comprising the steps of: configuring the spacer to have a width that allows depositing the given amount of the at least one metal on the source and drain regions of the capacitor device such that once the at least one metal Reacting with the silicon in the source and drain regions of the capacitor device, the first silicide is formed extending at least to the edge of the first gate stack. 10. The method of claim 7, further comprising the steps of: Spacers are formed on opposite sides of the second gate stack. 11. The method of claim 10, further comprising the steps of: configuring the spacer to have a width that allows deposition of the given amount of the at least one metal on the source and drain regions of the FET device such that once the at least one If a metal reacts with the silicon in the source and drain regions of the FET device, the second silicide formed remains in the doped source and drain regions of the FET device Inside. 12. The method of claim 7, further comprising the steps of: Epitaxial silicon is formed on the source and drain regions of the FET device. 13. The method of claim 12, further comprising the steps of: The amount of epitaxial silicon formed on the source and drain regions of the FET device is configured such that once the at least one metal is combined with the silicon in the source and drain regions of the FET device reaction, the formed second silicide remains in the doped source and drain regions of the FET device. 14. A method of manufacturing an electronic device, comprising the steps of: providing an SOI wafer having an SOI layer on the BOX; Etching at least one first set of nanowires and a first set of liners in the SOI layer and etching at least one second set of nanowires and a second set of liners in the SOI layer, wherein the first set of liners attached to opposite ends of the first set of nanowires in a ladder-like configuration, and wherein the second set of pads is attached to opposite ends of the second set of nanowires in a ladder-like configuration; forming a first gate stack surrounding at least a portion of each nanowire in the first set of nanowires serving as a channel region of a capacitor device, wherein the first set of nanowires Portions of the gate stack extending from the gate stack and the first set of pads serve as source and drain regions of the capacitor device; forming a second gate stack surrounding at least a portion of each nanowire in the second set of nanowires serving as a channel region of a field effect transistor (FET) device, wherein the Portions of the second set of nanowires extending from the gate stack and the second set of pads serve as source and drain regions for the FET device; doping the source and drain regions of the FET device and the source and drain regions of the capacitor device; forming a first silicide extending into an undoped channel region of the capacitor device on the source and drain regions of the capacitor device; and A second silicide is formed on the source and drain regions of the FET device. 15. The method of claim 14, wherein the step of forming the first silicide on the source and drain regions of the capacitor device comprises the steps of: Depositing a given amount of at least one metal on the source and drain regions of the capacitor device such that once the at least one metal is in contact with the source and drain regions of the capacitor device silicon reacts, the first silicide formed extends from the source and drain regions of the doped capacitor device into the channel region of the undoped capacitor device. 16. The method of claim 15, wherein the at least one metal is selected from the group comprising nickel, cobalt, platinum, and combinations comprising at least one of the foregoing metals. 17. The method according to claim 15 , wherein said at least one metal is deposited on said source and drain regions of said capacitor device in a plurality of deposition steps until all of said capacitor device is achieved. The given amount of the at least one metal on the source and drain regions. 18. The method of claim 17, wherein during at least one of the plurality of depositing steps, the source and drain regions of the FET device are masked using a shadow mask. 19. The method of claim 14, wherein the step of forming the second silicide on the source and drain regions of the FET device comprises the steps of: Depositing a given amount of at least one metal on said source and drain regions of said FET device such that once said at least one metal is combined with said source and drain regions of said FET device If silicon is reacted, the second silicide formed remains in the doped source and drain regions of the FET device. 20. The method of claim 15, further comprising the steps of: Spacers are formed on opposite sides of the first gate stack. 21. The method of claim 20, further comprising the steps of: The spacer is configured to have a width that allows deposition of the given amount of the at least one metal on the source and drain regions of the capacitor device such that once the at least a metal reacts with the silicon in the source and drain regions of the capacitor device, and the first silicide is formed from the doped source and drain regions of the capacitor device extending into the undoped channel region of the capacitor device. 22. The method of claim 19, further comprising the steps of: Spacers are formed on opposite sides of the second gate stack. 23. The method of claim 22, further comprising the steps of: configuring the spacer to have a width that allows deposition of the given amount of the at least one metal on the source and drain regions of the FET device such that once the at least one If a metal reacts with the silicon in the source and drain regions of the FET device, the second silicide formed remains in the doped source and drain regions of the FET device Inside. 24. The method of claim 15, further comprising the steps of: Epitaxial silicon is formed on source and drain regions of the capacitor device. 25. The method of claim 24, further comprising the steps of: The amount of said epitaxial silicon formed on said source and drain regions of said capacitor device is configured such that once said at least one metal is in contact with said source and drain regions of said capacitor device reaction of the silicon, the first silicide formed extends from the source and drain regions of the doped capacitor device into the channel region of the undoped capacitor device. 26. The method of claim 19, further comprising the steps of: Epitaxial silicon is formed on the source and drain regions of the FET device. 27. The method of claim 26, further comprising the steps of: The amount of said epitaxial silicon formed on said source and drain regions of said FET device is configured such that once said at least one metal is in contact with said source and drain regions of said FET device reaction of the silicon, the formed second silicide remains in the doped source and drain regions of the FET device. 28. An electronic device comprising: At least one first set of nanowires and first set of liners etched in the SOI layer of the SOI wafer and at least one second set of nanowires and second set of liners etched in the SOI layer, wherein the first a set of pads attached to opposite ends of said first set of nanowires in a ladder-like configuration, and wherein said second set of pads is attached to opposite ends of said second set of nanowires in a ladder-like configuration; A first gate stack surrounding at least a portion of each nanowire in the first set of nanowires serving as a channel region of a capacitor device, wherein the nanowires of the first set are drawn from the gate stack the extended portion and the first set of pads serve as source and drain regions of the capacitor device, wherein the source and drain regions of the capacitor device are undoped; A second gate stack surrounding at least a portion of each nanowire in the second set of nanowires serving as a channel region of a FET device, wherein the second set of nanowires from the gate stack the extended portion and the second set of pads serve as source and drain regions of the FET device, wherein the source and drain regions of the FET device are doped; a first silicide formed on the source and drain regions of the capacitor device extending at least to an edge of the first gate stack; and A second silicide is formed on the source and drain regions of the FET device. 29. An electronic device comprising: At least one first set of nanowires and first set of liners in the SOI layer of the SOI wafer and at least one second set of nanowires and second set of liners etched in the SOI layer, wherein the first set pads are attached to opposite ends of the first set of nanowires in a ladder-like configuration, and wherein the second set of pads is attached to opposite ends of the second set of nanowires in a ladder-like configuration; A first gate stack surrounding at least a portion of each nanowire in the first set of nanowires serving as a channel region of a capacitor device, wherein the nanowires of the first set are drawn from the gate stack the extended portion and the first set of pads serve as source and drain regions of the capacitor device, wherein the source and drain regions of the capacitor device are doped; A second gate stack surrounding at least a portion of each nanowire in the second set of nanowires serving as a channel region of a FET device, wherein the second set of nanowires from the gate stack the extended portion and the second set of liners serve as source and drain regions of the FET device, wherein the source and drain regions of the FET device are doped; a first silicide on the source and drain regions of the capacitor device extending into the undoped channel region of the capacitor device; and A second silicide on the source and drain regions of the FET device.