CN103973276B - A kind of demodulation threshold method for self-calibrating and circuit - Google Patents
A kind of demodulation threshold method for self-calibrating and circuit Download PDFInfo
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Abstract
The invention discloses a kind of demodulation threshold method for self-calibrating and circuit, its method is that first wireless signal transmission is compared by data reception module with threshold voltage, parse clock and the data signal of correspondence, clock alignment module and carrier wave timeout flag produce circuit module and utilize the sequential relationship of obtainable effective information locked clock and data signal, and the clock that data reception module is parsed by digital control module is decoded by agreement with data signal；If the mechanism for correcting errors of digital control module continuous solution during decoding separates out the data code flow of mistake, then stop decoding, and foundation algorithm produces one group of new calibration code and adjusts threshold value, again decodes after relocking clock and the sequential relationship of data signal；Repeat said process, until mechanism for correcting errors no longer reports an error, it is achieved demodulation threshold self calibration.The present invention can quickly realize the self adaptation of chip, and design is simple, it is easy to accomplish, low cost.
Description
Technical field
The invention belongs to chip technology field, be specifically related to a kind of demodulation threshold method for self-calibrating and circuit.
Background technology
In transmission of wireless signals is applied, amplitude modulation (ASK) technology is widely adopted.During ASK demodulation, for adapting to chip technology, information source distance and the change of applied environment, automatic regulating voltage is needed to compare threshold value so that it is to be positioned at the correct position between two amplitudes.Generally, demodulation threshold self calibration uses program controlled mode, it may be assumed that threshold value can be generated by selection circuit configuration；Configuration data leave programmable nonvolatile memory such as EEPROM(Electrically Erasable Read Only Memory in) or FLASH(flash memory) in, and initialized by empirical data；If certain predefined error conditions is set up during decoding, then starting dedicated control circuit and algorithm logic (being realized by hardware or firmware), iteration asks for new configuration data, until this error conditions eliminates, and more newly configured data, it is achieved threshold value self calibration.
The demodulation threshold method for self-calibrating of program controlled mode needs special EEPROM or FLASH and programmed circuit, more complicated dedicated control circuit and algorithm logic, prior substantial amounts of test to determine the transfer relationship etc. between configuration data, therefore design difficulty is big, realize complexity, relatively costly, self calibration is the longest.And, EEPROM and FLASH has certain lifetime, there is the possibility of inefficacy, is not suitable for the application the highest to service life requirement, such as human body implantation type Electronic medical device etc..
Summary of the invention
It is an object of the invention to provide a kind of self adaptation that can quickly realize chip, and design simple, it is easy to accomplish, the demodulation threshold self-calibration circuit of low cost.When ASK demodulates, adapt to chip technology, information source distance and the change of applied environment, automatically calibrate demodulation threshold so that it is be positioned at the correct position between two amplitudes, reduce decoding error rates of data.
The demodulation threshold self-calibration circuit of the present invention, produces circuit module and digital control module including data reception module, clock alignment module, carrier wave timeout flag；Data reception module, for receiving amplitude modulation (ASK) signal of exterior antenna or coil, carries out clock and data recovery；Clock alignment module and carrier wave timeout flag produce circuit module and produce carrier wave timeout flag, are used for notifying that digital control module carries out corrupt data during protocol analysis and judges；Digital control module controls the startup of other module, works, stops and the parsing of agreement, error correction, data encoding, and when receiving and being consecutively detected error in data, notice data reception module is demodulated adjusting thresholds；
Described data reception module includes threshold voltage generation circuit, the first voltage comparator, the second voltage comparator and the clock edge extension delay circuit of decoding and electric resistance array composition；First voltage comparator, the in-phase input end of the second voltage comparator are connected with the amplitude-modulated signal of exterior antenna or coil；The input of threshold voltage generation circuit is connected with the outfan of digital control module, and the inverting input of outfan and the second voltage comparator connects；The reverse inter-input-ing ending grounding of the first voltage comparator, outfan is connected with two-stage phase inverter, two-stage phase inverter output clock signal；Second voltage comparator outfan is connected with clock edge delay circuit, clock edge delay circuit outputting data signals.
Described clock edge delay circuit is become by 4 grades of inverter stage joint groups, first order phase inverter is composed in series by the first PMOS, the first NMOS tube and the second NMOS tube, second level phase inverter is composed in series by the second PMOS, the 3rd PMOS and the 3rd NMOS tube, the structure of third level phase inverter is identical with first order phase inverter, the 4th PMOS, the 4th NMOS tube and the 5th NMOS tube are composed in series；Fourth stage phase inverter is composed in series by the 5th PMOS and the 6th NMOS tube；In first order phase inverter, the outfan of PMOS, the first NMOS tube, the grid of the second NMOS tube and the second voltage comparator connects, and in fourth stage phase inverter, the drain terminal of the 5th PMOS and the 6th NMOS tube is connected with clock alignment module and digital control module.
Described clock alignment module includes reset and start-up circuit, clock signal enumerator, carrier wave timeout flag sampling comparison circuit, carrier wave timeout flag calibration algorithm processing module and the locking output circuit being sequentially connected with, and connects and be provided with the time delay generation circuit that analog circuit is stable between outfan and the input of clock signal enumerator of carrier wave timeout flag calibration algorithm processing module；Clock signal enumerator outgoing carrier timeout flag timing signal produces circuit module to carrier wave timeout flag；Carrier wave timeout flag sampling comparison circuit produces circuit module incoming carrier timeout flag signal from carrier wave timeout flag；Locking output circuit exports one group of timing alignment code and produces circuit module to carrier wave timeout flag.
Described digital control module comprises three parts: protocol analysis and time-sequence control mode, error checking module and radio frequency (RF) calibration module；Protocol analysis is connected with input and clock signal RFCK of data reception module, the data signal DATA outfan of time-sequence control mode, outfan output even-odd check order PAR_CMD, data code flow DATA_BIN are connected with error checking module, and output clock alignment enables signal CAL_EN and is connected with radio frequency (RF) calibration module；Error checking module output error marking signal ERR is connected with time-sequence control mode with protocol analysis, and output locking signal LOCK is connected with radio frequency (RF) calibration module；Radio frequency (RF) calibration module output threshold calibration code signal RF_CAL_CODE is connected with data reception module.
Described carrier wave timeout flag produces circuit module and comprises three parts: reference current generating circuit, start-up circuit and carrier wave timeout flag (CTO) signal generating circuit；Reference current generating circuit is by the six, the 7th PMOS PM1, PM2, the seven, the 8th NMOS tube NM1, NM2, the first resistance R1, the first electric capacity C1, the 3rd electric capacity C3 composition；Start-up circuit is by the eight, the 9th PMOS PM9, PM10, the second resistance R2, the 3rd resistance R3 composition；Carrier wave timeout flag (CTO) signal generating circuit is by the tenth to the 15th PMOS PM3～PM8, the 9th to the 12nd NMOS tube NM3～NM6, second electric capacity C2 and the first phase inverter I52, the second phase inverter I54 composition；In start-up circuit, the source of the 9th PMOS PM10 is connected with power supply AVDD, the drain terminal of the 9th PMOS PM10 and the grid of one end of the second resistance R2 and the 8th PMOS PM9 connect, the other end of the second resistance R2 is connected with ground AGND, and the grid of the 9th PMOS PM10 is connected with reference voltage signal BAISP；The source of the 8th PMOS PM9 is connected with the 3rd resistance R3, the other end of the 3rd resistance R3 is connected with power supply AVDD, the drain terminal of the 8th PMOS PM9 is connected with the grid of the 8th NMOS tube NM2, drain electrode and the grid of the 7th NMOS tube NM1 in reference generating circuit, the drain terminal of the 7th PMOS PM2, and the drain electrode of reference voltage signal BAISP and the grid of the 7th PMOS PM1 and drain electrode, the 11st PMOS PM4 and the grid of the 12nd PMOS PM5, the 7th NMOS tube NM1 connects；In carrier wave timeout flag (CTO) signal generating circuit, tenth PMOS PM3 and the series connection of the 9th NMOS tube NM3, their grid is all connected with carrier wave timeout flag timing signal CTO_CK, the source of the tenth PMOS PM3 is connected with the drain terminal of the 11st PMOS PM4, the source ground connection AGND of the 9th NMOS tube NM3；The drain terminal of the tenth PMOS PM3 and the drain terminal of the 9th NMOS tube NM3, the grid of the tenth NMOS tube NM4, the grid of the 11st NMOS tube NM5, one end of the second electric capacity C2 connect；12nd PMOS PM5 and the tenth NMOS tube NM4 are connected in series, and the drain terminal of the 12nd PMOS PM5 and the drain terminal of the tenth NMOS tube NM4 are connected with carrier wave timeout flag complementary signal CTON；The source of the 12nd PMOS PM5 is connected with power supply AVDD, and the source of the tenth NMOS tube NM4 is connected with ground AGND；Carrier wave timeout flag complementary signal CTON and the drain terminal of the 13rd PMOS PM6, the grid of the 14th PMOS PM7, the grid of the 12nd NMOS tube NM6 connect；The source of the 13rd PMOS PM6 is connected with power supply AVDD, and the outgoing carrier timeout flag timing complementary signal CTO_CKN of grid and the first phase inverter I52 connects；14th PMOS PM7, the 11st NMOS tube NM5 and the 12nd NMOS tube NM6 are connected in series；The other end of the 14th PMOS PM7 and the drain terminal of the 11st NMOS tube NM5 and the drain terminal of the 15th PMOS PM8, the second electric capacity C2 connects, the outgoing carrier timeout flag timing complementary signal CTO_CKN of grid and the first phase inverter I52 connects, and source is connected with power supply AVDD.
Compared with the demodulation threshold self calibration of program controlled mode; the present invention need not the devices such as EEPROM or FLASH and programmed circuit; need not carry out in advance mass data test; need not more complicated placement algorithm logic; but utilize transmission in the obtainable effective information such as clock signal recovered, agreement to represent the umber of pulse etc. of digital " 0 "; use the sequential relationship of Digital Analog Hybrid Circuits locked clock and data, and realize demodulation threshold self calibration in the present inventive method.Therefore, the present invention can quickly realize the self adaptation of chip, and design is simple, it is easy to accomplish, low cost, it is especially suitable for the application that service life requirement is the highest, such as human body implantation type Electronic medical device etc..
Technical solution of the present invention is described in detail below in conjunction with embodiment.
Accompanying drawing explanation
Fig. 1 is embodiments of the invention structural representations.
Fig. 2 is the circuit diagram of data reception module in the present invention.
Fig. 3 is the result waveform diagram of voltage comparator and demodulation in data reception module.
Fig. 4 be in data reception module clock edge delay circuit figure and input with output oscillogram.
Fig. 5 is clock alignment module diagram in the present invention.
Fig. 6 is digital control module structural representation in the present invention.
Fig. 7 is that in the present invention, CTO produces circuit figure.
Detailed description of the invention
The embodiment of the demodulation threshold self-calibration circuit of the present invention is as it is shown in figure 1, include that data reception module 1, clock alignment module 2, carrier wave timeout flag (CTO) produce circuit module 4 and digital control module 3；This circuit receives device with external signal and is connected, and external signal receives device and includes the transformator T that receiving coil (or antenna) L is connected with receiving coil (or antenna) L；The input of data reception module 1 is connected with the transformator T of signal receiving device, receive exterior antenna or the amplitude-modulated signal RFIN of coil L, output clock signal RFCK and data signal DATA, to clock alignment module 2 and digital control module 3, carry out clock and data recovery；Clock alignment module 2 exports CTO timing signal CTO_CK and one group of timing alignment code CAL_CODE to CTO and produces circuit module 4, CTO generation circuit module 4 outgoing carrier timeout flag signal CTO, to clock alignment module 2 and digital control module 3, is used for notifying that digital control module 3 carries out corrupt data during protocol analysis and judges；Digital control module 3 exports reset signal CTO_RST and clock alignment enables signal CAL_EN to clock alignment module 2, output reset signal RESET and CTO produce and enable signal CTO_EN to CTO generation circuit module 4, export one group of threshold calibration code RF_CAL_CODE to data reception module 1, control the startup of these modules, work, stop and the parsing of agreement, error correction, data encoding etc., when receiving and being consecutively detected error in data, notice data reception module 1 carries out adjusting thresholds.
Data reception module 1 is as in figure 2 it is shown, include threshold voltage generation circuit 101, voltage comparator 102a, 102b and the clock edge extension delay circuit 103 of decoding and electric resistance array composition；The amplitude-modulated signal RFIN of exterior antenna or coil in-phase input end with voltage comparator 102a, 102b respectively is connected；The input of threshold voltage generation circuit 101 is connected with output signal RF_CAL_CODE of digital control module 3, value according to RF_CAL_CODE selects the resistance value in bleeder circuit, and outfan produces threshold voltage VREF and is connected with voltage comparator 102b inverting input；The reverse inter-input-ing ending grounding of voltage comparator 102a, outfan exports RFCK signal through two-stage phase inverter；The outfan of voltage comparator 102b is connected with the input of clock edge delay circuit 103, and clock edge delay circuit 103 exports DATA signal.Wherein, threshold voltage generation circuit 101 is produced 2 by decoding array elementNPosition selects signal (N is the bit wide inputting RF_CAL_CODE), for gating resistance values different in resistor voltage divider circuit, produces adjustable threshold voltage between 0V～VDD, and degree of regulation is VDD/2N.Voltage comparator 102a can be completely by recovering clock signals when demodulation clock signal；VREF initial value is VDD/2, for recovering data signal, and can be adjusted between 0V～VDD according to the size of RF_CAL_CODE code.
As shown in Figure 3, voltage comparator 102a and voltage comparator 102b by receive from transformator RFIN signal respectively with reference to ground voltage, VREF voltage ratio relatively, extract clock and data message, the result of demodulation waveform as shown in Figure 3 that amplitude-modulated signal envelope carries.
Clock edge delay circuit 103 as shown in Figure 4, is become by 4 grades of inverter stage joint groups.First order phase inverter is made up of with NMOS tube M1, M2 PMOS M0, the grid of M0, M1, M2 is connected with data pulse signal DATA_CK, when DATA_CK signal is low level, output high level, when DATA_CK signal becomes high level, owing to M0, M1 connect, electric discharge equivalent electric resistive is big, just can become low level so exporting after time delay certain time；Second level phase inverter is made up of with NMOS tube M5 PMOS M4, M3, and operation principle is contrary with previous stage amplifier, just when input is by high step-down level, exports and is needed certain time delay by low uprising, because the charging path resistance that M4, M3 are composed in series becomes big；Third level phase inverter is identical with the first order with first order inverter function and structure.In Fig. 4, data pulse signal DATA_CK and data signal DATA waveform are clock edge delay circuit 103 input and the oscillogram exported in data reception module 1.
As shown in Figure 5, clock alignment module 2 includes reset and start-up circuit, RFCK enumerator, CTO sampling comparison circuit, CTO calibration algorithm processing module and the locking output circuit being sequentially connected with, and connects and be provided with the time delay generation circuit that analog circuit is stable between outfan and the input of RFCK enumerator of CTO calibration algorithm processing module.Clock signal enumerator outgoing carrier timeout flag timing signal CTO_CK produces circuit module to carrier wave timeout flag；Carrier wave timeout flag sampling comparison circuit produces circuit module incoming carrier timeout flag signal CTO from carrier wave timeout flag；Locking output circuit exports one group of timing alignment code CAL_CODE and produces circuit module to carrier wave timeout flag.After chip powers on successfully, reset and start-up circuit carries out reset processing to clock alignment module 2 entirety.Reset starts clock alignment module 2 after completing, under the RFCK and DATA signal effect of data reception module 1, RFCK is counted, and the carrier wave timeout flag timing signal CTO_CK pulse of one RFCK pulse width of generation when count value is zero, this pulse is used for triggering CTO generation module 3 and works.Assuming in ASK transmits, transmission " 1 " needs continuous 8 RFCK, and DATA signal is effectively (high level)；Transmission " 0 " needs also exist for the length of 8 RFCK, but DATA signal invalid (low level).In the RFCK enumerator of clock alignment module 2, enumerator is started when DATA signal is high level, when count value is equal to 15, CTO sampling comparison circuit sampling is from the CTO signal of CTO generation module 3, and CTO calibration algorithm processing module determines timing alignment code CAL_CODE code value according to CTO level.If CTO signal is high level, CAL_CODE code carries out binary system decrement operations；If CTO is low level, CAL_CODE code carries out binary system increment operation.CAL_CODE code gives the width that CTO generation module 3 adjusts CTO signal.In clock alignment module 2, time delay produces the enumerator realization that circuit is by 8, is used for providing CTO generation module 3 to simulate the time required for circuit stability after receiving CAL_CODE code.After completing this calibration, continue back at RFCK enumerator and start comparison and the calibration of a new round, until the pulsewidth of CTO is equal to 15 RFCK cycles, the CTO calibration algorithm processing module of clock alignment module 2 enters into locking output circuit, output CAL_CODE code is latched, now CAL_CODE code is locked as the value calibrated for the last time, and CTO_CK is switched to RFCK signal.
Digital control module 3 as shown in Figure 6, mainly includes 3 parts: protocol analysis and time-sequence control mode 301, error checking module 302, RF calibration module 303.Input signal RFCK of protocol analysis and time-sequence control mode 301 and DATA are from the output of data reception module 1, it is responsible for parsing data command from RFCK and DATA signal, and it is decoded and controls the generation of sequential, this module output CAL_EN signal is connected with RF calibration module 304, and even-odd check command signal and output data binary code are connected with error checking module 303；ERR signal (error flag signal) is from error checking module.The input data bitstream stream DATA_BIN of error checking module 302 is from the output of protocol analysis Yu time-sequence control mode 301, and this signal is one group of binary data code stream；Error checking module is receiving even-odd check order PAR_CMD(even-odd check order) after, the numeric data code sent here can be carried out odd-even check, if correct, ERR signal is low level, if check errors, ERR signal becomes high level.RF calibration module 304 is enabled by the CAL_EN signal of protocol analysis with time-sequence control mode 301, the LOCK signal (locking signal) of error checking module lock.RF calibration module 304 enables signal in CAL_EN(calibration, when ERR mistake occurs, time effectively) effectively (high level is effective), and RF calibration module unlatching work, check whether LOCK signal locks (high level locking) simultaneously.If LOCK signal is low, not locking being described, CTO signal is detected by RF calibration module, exports one group of RF_CAL_CODE signal to data reception module 1 according to algorithm, is used for adjusting threshold size, changes the output valve of RFCK Yu DATA of data reception module 1.
CTO produces circuit module 4 as it is shown in fig. 7, mainly comprise three parts: reference current generating circuit 402, start-up circuit 401 and CTO signal generating circuit 403；Reference current generating circuit 402 is made up of PMOS PM1, PM2, NMOS tube NM1, NM2, resistance R1, electric capacity C1, C3；Start-up circuit 401 is made up of PMOS PM9, PM10, resistance R2, R3；CTO signal generating circuit 403 is by PMOS PM3～PM8, NMOS tube NM3～NM6, electric capacity C2 and phase inverter I52, I54 composition.In start-up circuit 401, the source of PMOS PM10 is connected with power supply AVDD, and PM10 drain terminal is connected with one end of resistance R2 and the grid of P pipe PM9, and the other end of resistance R2 is connected with ground AGND, and the grid of PM10 is connected with reference voltage signal BAISP；The source of PM9 is connected with resistance R3, and the other end of resistance R3 is connected with AVDD, and the drain terminal of PM9 is connected with the grid of grid, drain electrode and NM1 of N pipe NM2 in reference generating circuit 402, the drain terminal of P pipe PM2.The grid of reference voltage signal BAISP and P pipe PM1 and drain electrode, the grid of PM4 and PM5, the drain electrode of N pipe NM1 are connected.In carrier wave timeout flag (CTO) signal generating circuit 403, P pipe PM3 and N pipe NM3 connects, and grid is all connected with output signal CTO_CK, and the source of PM3 is connected with the drain terminal of PM4, the source ground connection AGND of NM3；The drain terminal of PM3 and the drain terminal connection output grid of A, A and N pipe NM4 of NM3, the grid of NM5, one end of electric capacity C2 are connected；PM5 with NM4 is connected in series, and the drain terminal of PM5 and the drain terminal of NM4 are connected with carrier wave timeout flag (CTO) complementary signal CTON；The source of PM5 is connected with power supply AVDD, and the source of NM4 is connected with ground AGND.The drain terminal of CTON with P pipe PM6, the grid of PM7, the grid of N pipe NM6 are connected；The source of PM6 is connected with power supply AVDD, and grid is connected with outgoing carrier timeout flag (CTO) the regularly complementary signal CTO_CKN of phase inverter I52；PM7, NM5 and NM6 are connected in series, and the drain terminal of PM7 with NM5 is connected with the B end of electric capacity C2；The drain terminal of PM8 is connected with the B end of C2, and grid is connected with the output CTO_CKN of phase inverter I52, and source is connected with power supply AVDD.Reference current generating circuit 402 is for producing the reference current unrelated with supply voltage, for CTO signal generating circuit 403.The size of reference current is adjusted by the resistance changing resistance R1, currently employed four bits 16 sections of values adjusting resistance R1 altogether.The effect of start-up circuit 401 is to make reference circuit produce circuit 202 can normally start, work.In CTO signal generating circuit 403, CTO_CK is the clock signal of input, and CTO is output.When CTO_CK is high level, inversion signal CTO_CKN is low level: NM3 conducting, and PM3 ends, and A is low level, and NM4 ends；PM8 turns on, and B is high level, and the pressure drop on electric capacity C2 is V (B)-V (A)=VDD；PM6 turns on, and CTON is high level, and CTO is output as low level.CTO_CK is low level by high level saltus step, CTO_CKN is ended by low transition high level: NM3, PM3 turns on, A is charged by reference current, and A point current potential rises, and depends primarily on size and the capacitance of electric capacity C2 of charging current through one section of time delay T() after, the A point voltage threshold V T HN more than NM4, NM4 pipe turns on, and by drop-down for CTON current potential, CTO is output as high level.If in short, input CTO_CK is high level, then output CTO is low level；If after input CTO_CK is low level by high level saltus step, and low duration is more than T, output CTO saltus step is high level；If input CTO_CK is low level by high level saltus step, and low duration is less than T, then output CTO will keep low level.
Operation principle:
After the demodulation threshold self-calibration circuit of the present invention is connected with external signal reception device, receiving coil (or antenna) L receives the wireless signal that outside transmission comes, being transferred to data reception module 1 after transformator T couples, this data reception module 1 is mainly made up of analog circuit.The demodulation threshold voltage of data reception module 1 is generated by one group of threshold calibration code RF_CAL_CODE configuration from digital control module 3, and the span of this threshold calibration code can set according to the actual requirements, and initial value is intermediate value.During the demodulation of amplitude modulation (ASK) signal, first wireless signal transmission is compared by data reception module 1 with threshold voltage, parses clock signal RFCK and data signal DATA of correspondence.Clock signal RFCK represents the frequency information of wireless signal, as system work clock.Data signal DATA is the order entrained by wireless signal, data and other information.While clock signal RFCK and data signal DATA are transferred to digital control module 3, it is also communicated to clock alignment module 2.Chip is after having powered on, and digital control module 3 starts and initializes clock alignment module 2 and CTO generation circuit module 4, CAL_EN and CTO_EN signal is become high level from low level.Clock alignment module 2 and carrier wave timeout flag produce circuit module 4 and utilize the sequential relationship of obtainable effective information (as in the clock signal recovered, agreement, transmission represents the umber of pulse etc. of digital " 0 ") locked clock and data signal.Clock alignment module 2 is upon actuation, count in the data signal DATA valid period, assume that often counting M(M is determined by the umber of pulse transmitting digital " 0 " in ASK agreement) after individual value, produce a pulse CTO_CLK(CTO pulse) and set of number calibration code CAL_CODE(calibration code, being made up of binary coding, figure place is determined by the speed calibrated and precision) signal produces circuit module 4 to CTO.CTO produces circuit module 4 and is made up of electric resistance array and current source, receiving CTO_CLK(CTO pulse) after, start working, according to CAL_CODE(calibration code) value carry out the selection of circuit internal resistance array, resistance value determines CTO(carrier wave timeout flag) width of signal.CTO_CK(CTO pulse detected) rising edge of pulse, CTO(carrier wave timeout flag) jumped to high level by the low level given tacit consent to, holding time by CAL_CODE(calibration code of high level) determine.CTO(carrier wave timeout flag) signal feeds back to clock alignment module 2, this clock alignment module 2 is by CTO(carrier wave timeout flag) the low level time RFCK(radio-frequency carrier clock corresponding with M value) time in cycle compares, when both are the most close, CAL_CODE value is adjusted by the algorithm in clock calibration module 2, until both are close, CTO pulsewidth is fixed；When both are close, CTO clock alignment module 2 locks, CAL_CODE(calibration code) lock constant.Digital control module 3 is the brain of whole threshold value self-calibration circuit, controls the startup of other module, works, stops and the parsing of agreement, error correction, data encoding etc..At CTO(carrier wave timeout flag) semaphore lock, clock signal RFCK that data reception module 1 is parsed by digital control module 3 is decoded by agreement with data signal DATA.If the mechanism for correcting errors of digital control module 3 continuous solution during decoding separates out the data code flow of mistake, illustrate that the threshold value of data reception module 1 arranges the demand being unsatisfactory for current application, then stop decoding, and produce one group of new calibration code adjustment threshold value according to algorithm.Error checking module in data control block 3 can follow the tracks of the level situation of change of CTO simultaneously, if there is low level phenomenon in CTO, illustrating that threshold value is higher, digital control module 3 is to calibration code RF_CAL_CODE(RF threshold calibration code) subtract 1 after, give data reception module 1 and calibrate；If CTO is always maintained at high level, illustrating that threshold value is on the low side, digital control module 3 is to calibration code RF_CAL_CODE(RF threshold calibration code) add 1 after, give data reception module 1 and calibrate.Then, again decode after relocking clock and the sequential relationship of data signal, digital control module 3 continues to be monitored agreement and error checking, if the most above-mentioned mistake, continue calibration and locking, repeat said process, until mechanism for correcting errors no longer reports an error, RF_CAL_CODE(RF threshold calibration code) it is locked in current state value, it is achieved demodulation threshold self calibration, and recover the normal work of whole system entrance.
Claims (5)
1. a demodulation threshold self-calibration circuit, is characterized in that including that data reception module, clock alignment module, carrier wave timeout flag produce circuit module and digital control module；Data reception module, for receiving the amplitude-modulated signal of exterior antenna or coil, carries out clock and data recovery；Clock alignment module and carrier wave timeout flag produce circuit module and produce carrier wave timeout flag, are used for notifying that digital control module carries out corrupt data during protocol analysis and judges；Digital control module controls the startup of other module, works, stops and the parsing of agreement, error correction, data encoding, and when receiving and being consecutively detected error in data, notice data reception module is demodulated adjusting thresholds；Described data reception module includes threshold voltage generation circuit, the first voltage comparator, the second voltage comparator and the clock edge extension delay circuit of decoding and electric resistance array composition；First voltage comparator, the in-phase input end of the second voltage comparator are connected with the amplitude-modulated signal of exterior antenna or coil；The input of threshold voltage generation circuit is connected with the outfan of digital control module, and the inverting input of outfan and the second voltage comparator connects；The reverse inter-input-ing ending grounding of the first voltage comparator, outfan is connected with two-stage phase inverter, two-stage phase inverter output clock signal；Second voltage comparator outfan is connected with clock edge delay circuit, clock edge delay circuit outputting data signals.
Demodulation threshold self-calibration circuit the most according to claim 1, it is characterized in that described clock edge delay circuit is become by 4 grades of inverter stage joint groups, first order phase inverter is composed in series by the first PMOS, the first NMOS tube and the second NMOS tube, second level phase inverter is composed in series by the second PMOS, the 3rd PMOS and the 3rd NMOS tube, the structure of third level phase inverter is identical with first order phase inverter, the 4th PMOS, the 4th NMOS tube and the 5th NMOS tube are composed in series；Fourth stage phase inverter is composed in series by the 5th PMOS and the 6th NMOS tube；In first order phase inverter, the outfan of PMOS, the first NMOS tube, the grid of the second NMOS tube and the second voltage comparator connects, and in fourth stage phase inverter, the drain terminal of the 5th PMOS and the 6th NMOS tube is connected with clock alignment module and digital control module.
Demodulation threshold self-calibration circuit the most according to claim 2, it is characterized in that reset and start-up circuit, clock signal enumerator, carrier wave timeout flag sampling comparison circuit, carrier wave timeout flag calibration algorithm processing module and locking output circuit that described clock alignment module includes being sequentially connected with, connect between outfan and the input of clock signal enumerator of carrier wave timeout flag calibration algorithm processing module and be provided with the stable time delay of analog circuit and produce circuit；Clock signal enumerator outgoing carrier timeout flag timing signal produces circuit module to carrier wave timeout flag；Carrier wave timeout flag sampling comparison circuit produces circuit module incoming carrier timeout flag signal from carrier wave timeout flag；Locking output circuit exports one group of timing alignment code and produces circuit module to carrier wave timeout flag.
Demodulation threshold self-calibration circuit the most according to claim 3, is characterized in that described digital control module comprises three parts: protocol analysis and time-sequence control mode, error checking module and RF calibration module；Protocol analysis is connected with input and the clock signal of data reception module, the data signal output of time-sequence control mode, outfan output even-odd check order, data code flow are connected with error checking module, and output clock alignment enables signal and is connected with RF calibration module；Error checking module output error marking signal is connected with time-sequence control mode with protocol analysis, and output locking signal is connected with RF calibration module；RF calibration module output threshold calibration code signal is connected with data reception module.
Demodulation threshold self-calibration circuit the most according to claim 4, is characterized in that described carrier wave timeout flag produces circuit module and comprises three parts: reference current generating circuit, start-up circuit and carrier wave timeout flag signal generating circuit；Reference current generating circuit is by the six, the 7th PMOS, the seven, the 8th NMOS tube, the first resistance, the first electric capacity, the 3rd electric capacity composition；Start-up circuit is by the eight, the 9th PMOS, the second resistance, the 3rd resistance composition；Carrier wave timeout flag signal generating circuit is by the tenth to the 15th PMOS, the 9th to the 12nd NMOS tube, the second electric capacity and the first phase inverter, the second phase inverter composition；In start-up circuit, the source of the 9th PMOS is connected with power supply, and the drain terminal of the 9th PMOS and the grid of one end of the second resistance and the 8th PMOS connect, and the other end of the second resistance is connected to ground, and the grid of the 9th PMOS is connected with reference voltage signal；The source of the 8th PMOS is connected with the 3rd resistance, the other end of the 3rd resistance is connected with power supply, the drain terminal of the 8th PMOS is connected with the grid of the 8th NMOS tube, drain electrode and the grid of the 7th NMOS tube in reference generating circuit, the drain terminal of the 7th PMOS, and the drain electrode of reference voltage signal and the grid of the 7th PMOS and drain electrode, the 11st PMOS and the grid of the 12nd PMOS, the 7th NMOS tube connects；In carrier wave timeout flag signal generating circuit, the tenth PMOS is connected with the 9th NMOS tube, and their grid is all connected with carrier wave timeout flag timing signal, and the source of the tenth PMOS is connected with the drain terminal of the 11st PMOS, the source ground connection of the 9th NMOS tube；The drain terminal of the tenth PMOS and the drain terminal of the 9th NMOS tube, the grid of the tenth NMOS tube, the grid of the 11st NMOS tube, one end of the second electric capacity connect；12nd PMOS is connected in series with the tenth NMOS tube, and the drain terminal of the 12nd PMOS and the drain terminal of the tenth NMOS tube are connected with carrier wave timeout flag complementary signal；The source of the 12nd PMOS is connected with power supply, and the source of the tenth NMOS tube is connected to ground；Carrier wave timeout flag complementary signal and the drain terminal of the 13rd PMOS, the grid of the 14th PMOS, the grid of the 12nd NMOS tube connect；The source of the 13rd PMOS is connected with power supply, and the outgoing carrier timeout flag timing complementary signal of grid and the first phase inverter connects；14th PMOS, the 11st NMOS tube and the 12nd NMOS tube are connected in series；14th PMOS is connected with drain terminal and the drain terminal of the 15th PMOS, the other end of the second electric capacity of the 11st NMOS tube, and the outgoing carrier timeout flag timing complementary signal of grid and the first phase inverter connects, and source is connected with power supply.
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| CN106878217B (en) * | 2015-12-10 | 2021-01-15 | 美国莱迪思半导体公司 | Method and apparatus for data demodulation |
| CN106898998B (en) * | 2017-02-27 | 2018-09-21 | 华中科技大学 | A kind of rapid protecting device of high-voltage signal isolation |
| US10038549B1 (en) * | 2018-03-14 | 2018-07-31 | Shanghai Zhaoxin Semiconductor Co., Ltd. | Clock and data recovery circuit |
| CN109101375B (en) * | 2018-07-04 | 2021-08-03 | 维沃移动通信有限公司 | A method, server and test apparatus for repairing failure |
| CN110086486A (en) * | 2019-03-25 | 2019-08-02 | 普联技术有限公司 | Signal receiving anti-jamming method, device, wireless telecom equipment and storage medium |
| CN116032305B (en) * | 2023-03-29 | 2023-06-23 | 湖南大学 | A cochlear implant chip clock and data receiving circuit |
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| CN101990071A (en) * | 2009-07-29 | 2011-03-23 | 晨星软件研发(深圳)有限公司 | Demodulator and method capable of automatically calibrating output and television receiver thereof |
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