CN114005804A - A kind of diamond passivation gallium nitride device multi-finger gate interconnect structure and preparation method thereof - Google Patents
A kind of diamond passivation gallium nitride device multi-finger gate interconnect structure and preparation method thereof Download PDFInfo
- Publication number
- CN114005804A CN114005804A CN202111157486.6A CN202111157486A CN114005804A CN 114005804 A CN114005804 A CN 114005804A CN 202111157486 A CN202111157486 A CN 202111157486A CN 114005804 A CN114005804 A CN 114005804A
- Authority
- CN
- China
- Prior art keywords
- gate
- diamond
- strip
- layer
- composite dielectric
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76847—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned within the main fill metal
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
本发明涉及一种金刚石钝化氮化镓器件多指栅互连结构及其制备方法，属于新型半导体器件热管理技术研究领域。本发明的结构设计自上而下依次包括指栅互连结构区、复合介质层、金刚石钝化层、势垒层、缓冲层、及衬底；所述栅互连结构区包括源电极、漏电极以及栅电极，结合引入的复合介质层，改进栅电极和漏电极的互连结构，实现电极的垂直交叉互连。本发明结构的制备方法是采用低温金刚石生长钝化技术以及空间拓扑结构将源电极、漏电极、栅电极各自互连，提高散热，同时降低寄生电容。本发明的金刚石钝化结构的多指栅互联结构氮化镓基器件具有高效散热以及结构稳定的优点，可用于超大功率微波功率器件。
The invention relates to a multi-finger gate interconnection structure of a diamond passivation gallium nitride device and a preparation method thereof, belonging to the research field of thermal management technology of novel semiconductor devices. The structure design of the present invention includes, from top to bottom, a finger gate interconnect structure region, a composite dielectric layer, a diamond passivation layer, a potential barrier layer, a buffer layer, and a substrate; the gate interconnect structure region includes a source electrode, a leakage current The gate electrode and the gate electrode are combined with the introduction of the composite dielectric layer to improve the interconnection structure of the gate electrode and the drain electrode, and realize the vertical cross interconnection of the electrodes. The preparation method of the structure of the present invention adopts the low-temperature diamond growth passivation technology and the spatial topology structure to interconnect the source electrode, the drain electrode and the gate electrode respectively, so as to improve the heat dissipation and reduce the parasitic capacitance at the same time. The multi-finger gate interconnect structure gallium nitride-based device of the diamond passivation structure of the present invention has the advantages of efficient heat dissipation and stable structure, and can be used for ultra-high power microwave power devices.
Description
Technical Field
The invention relates to a multi-finger grid interconnection structure of a diamond passivated gallium nitride device and a preparation method thereof, belonging to the field of novel semiconductor device thermal management technology research.
Technical Field
As a third-generation semiconductor material, GaN has excellent performances of wide forbidden band (3.39 eV at room temperature), high electronic saturation rate (2.5 multiplied by 107cm/s), high breakdown field strength (3.3MV/cm) and the like, is very suitable for developing high-frequency and high-power microwave millimeter wave devices and circuits, and has extremely high application value in the fields of 5G communication, new energy automobiles, radio frequency, wireless communication and the like.
With the continuous improvement and improvement of the design and the process of the GaN microwave power device, the output power of the device is improved by the multi-finger gate structure in a mode that a plurality of adjacent transistors are connected in parallel, and the output power of the gallium nitride device is higher and higher, the frequency is higher and higher, and the volume is smaller and smaller. Along with the miniaturization of size and the increase of power, the reliability and stability of GaN-based microwave power devices are seriously challenged, wherein the main reason is the "self-heating effect" of GaN devices, that is, the heat accumulation effect of the active region of a chip of GaN-based power devices is rapidly increased along with the increase of power density, so that various performance indexes of GaN-based microwave power devices are rapidly deteriorated. Meanwhile, a sacrificial layer is grown above a drain region of the traditional multi-finger gate air bridge interconnection structure, and then the sacrificial layer is removed after the source electrode is connected, so that parasitic capacitance is formed between the source electrode and the drain electrode, and the performance of a device is influenced, particularly the output characteristic at high frequency is influenced; meanwhile, the compatibility of the air bridge structure and the diamond passivation structure GaN device is poor.
Disclosure of Invention
In view of the defects of the prior art, the invention provides a multi-finger gate interconnection structure of a diamond passivated gallium nitride device and a preparation method thereof, which solve the problem of heat accumulation of an active region of a chip of the gallium nitride power device, reduce parasitic capacitance and improve the output characteristic and reliability of the gallium nitride device.
The invention adopts the following technical scheme for solving the technical problems:
a multi-finger grid interconnection structure of a diamond passivated gallium nitride device comprises a multi-finger grid interconnection structure area, a composite dielectric layer, a diamond passivation layer, a barrier layer, a buffer layer and a substrate in sequence from top to bottom; the multi-finger grid interconnection structure area comprises a source electrode, a drain electrode and a gate electrode and is of a vertical cross interconnection structure; the source electrode consists of a strip source and a source connecting wire connecting the strip source, the drain electrode consists of a strip drain and a drain connecting wire connecting the strip drain, and the gate electrode consists of a strip gate, a gate connecting wire connecting the strip gate and a gate pin; the strip-shaped source and the strip-shaped drain penetrate through the composite dielectric layer, and the source connecting line and the drain connecting line are arranged on the upper surface of the composite dielectric layer; the strip-shaped gate penetrates through the diamond passivation layer, the upper part of the strip-shaped gate is in contact with the composite dielectric layer, and the lower part of the strip-shaped gate is in contact with the barrier layer; the grid connecting wire penetrates through the diamond passivation layer, the upper part of the grid connecting wire is in contact with the composite dielectric layer, and the lower part of the grid connecting wire is in contact with the barrier layer and the strip-shaped grid; the grid pin penetrates through the composite dielectric layer and the diamond passivation layer and is in contact with the barrier layer and the grid connecting line.
The composite dielectric layer material is made of SiN dielectric with the thickness of 400-500 nm.
The thickness of the grid connecting line on the lower surface of the composite dielectric layer is 400-600 nanometers, and is consistent with the passivation thickness of diamond.
The thickness of the source connecting line and the drain connecting line is 400-600 nanometers.
A preparation method of a multi-finger gate interconnection structure of a diamond passivated gallium nitride device comprises the following steps:
1) firstly, performing growth preparation of a source and a drain functional region based on the traditional process;
2) low temperature CVD (Chemical Vapor Deposition; chemical vapor deposition) technology to carry out step-by-step low-temperature growth of the diamond passivation layer;
3) PECVD (Plasma Enhanced Chemical Vapor Deposition; plasma enhanced chemical vapor deposition) technology to perform the growth of the etching mask layer;
4) ICP (Inductively Coupled Plasma; inductively coupled plasma) etching technology to etch the grid region diamond passivation layer to obtain the strip grid pattern;
5) preparing a gate functional region by adopting an evaporation technology;
6) preparing the composite dielectric layer by adopting a PECVD technology;
7) etching the composite dielectric layer and the diamond passivation layer of the source-drain functional region by adopting an ICP (inductively coupled plasma) etching technology to etch the patterns of the drain electrode, the strip-shaped source and the grid pin;
8) and thickening and interconnecting the source and drain electrodes and metalizing the gate pins by adopting the traditional evaporation technology to complete the preparation of the multi-finger gate interconnection structure of the diamond passivated gallium nitride device.
The invention has the following beneficial effects:
the invention solves the technical problem of poor reliability of the multi-gate-finger interconnection process of the diamond passivated GaN device, introduces the composite dielectric layer, designs a novel interconnection structure, realizes three-dimensional isolation interconnection of a drain electrode and a gate electrode, reduces the capacitance of the interconnection structure, improves the reliability of the diamond passivated GaN device, and solves the heat accumulation of the active region of the GaN device.
Drawings
Fig. 1 is a top view of a gate interconnect structure region of a diamond passivated gallium nitride device multi-finger gate interconnect structure.
FIG. 2 is a schematic view of the structure of the layers at section A-A' of FIG. 1.
FIG. 3 is a schematic view of the structure of the layers at section B-B' of FIG. 1.
FIG. 4 is a schematic view of the structure of the layers at section C-C' of FIG. 1.
FIG. 5 is a schematic process flow diagram of a method for manufacturing a multi-finger gate interconnection structure of a diamond passivated gallium nitride device.
In the figure: 10. a substrate; 20. a buffer layer; 30. a barrier layer; 40. a diamond passivation layer; 50. a composite dielectric layer; 601. a strip-shaped drain; 602. a leakage connection line; 701. a strip-shaped grid; 702. a gate connection line; 703. a gate pin; 801. a strip source; 802. a source connection line.
Detailed Description
The following describes in detail a specific embodiment of the present invention with reference to the drawings and examples.
Referring to fig. 1 and 2, the invention provides a design and a preparation method of a multi-finger gate interconnection structure of a diamond passivated gallium nitride device, the structural design of the invention comprises a finger gate interconnection structure area, a composite dielectric layer 50, a diamond passivation layer 40, a barrier layer 30, a buffer layer 20 and a substrate 10 from top to bottom in sequence; the grid interconnection structure area comprises a source electrode, a drain electrode and a gate electrode and is a vertical cross interconnection structure, the structure avoids a traditional air bridge structure, the structural reliability is improved, and the output power of the gallium nitride transistor is effectively improved. The method for realizing the multi-finger-gate interconnection structure of the diamond passivated gallium nitride device is to adopt a low-temperature diamond growth passivation technology and a space topological structure to respectively interconnect a source electrode, a drain electrode and a gate electrode, thereby improving the heat dissipation and simultaneously reducing the parasitic capacitance.
Referring to fig. 1, the multi-finger gate interconnection structure layer includes a source electrode, a drain electrode and a gate electrode, and is a vertical cross interconnection structure; the source electrode consists of strip sources 801 and source connecting wires 802 for connecting the strip sources; the drain electrode is composed of a strip drain 601 and a drain connection line 602 connecting the strip drains together, and the gate electrode is composed of a strip gate 701, a gate connection line 702 connecting the strip gates together, and a gate pin 703.
Referring to fig. 2 and 3, the strip-shaped source 801 and the strip-shaped drain 601 penetrate through the composite dielectric layer 50 and the diamond passivation layer 40 to be in contact with the barrier layer 30; the source connection line 802 and the drain connection line 602 are on the upper surface of the composite dielectric layer 50.
Referring to fig. 1, 3 and 4, a strip gate 701 penetrates through a diamond passivation layer 40, is in contact with a composite dielectric layer 50 at the upper part and is in contact with a barrier layer 30 at the lower part; the lower surface of the grid connecting line composite dielectric layer 50 and the diamond passivation layer 40 are in contact with the barrier layer 30 and the strip-shaped grid 701; the gate pin 703 passes through the composite dielectric layer 50 and the diamond passivation layer 40, and contacts the barrier layer 30 and the gate connection line 702.
Referring to fig. 2, the composite dielectric layer 50 is made of SiN dielectric with a thickness of 400-500 nm, so as to realize three-dimensional isolation between the drain electrode and the gate electrode.
Referring to fig. 4, the thickness of the gate line 702 on the lower surface of the composite dielectric layer 50 is 400-600 nm, which is consistent with the thickness of the diamond passivation.
Referring to fig. 1 and 3, the source connection line 802 and the drain connection line 602 are disposed on the upper surface of the composite dielectric layer 50 and have a thickness of 400 nm and 600 nm.
Referring to fig. 5, the compatibility of the process of the multi-gate-finger diamond gallium nitride device and the traditional process is solved by the following steps:
1) preparing a source drain functional region: growing source and drain functional regions by adopting a traditional process;
2) preparing a polycrystalline diamond passivation layer: growing a diamond heat conduction layer (firstly carrying out carbon-based seed layer and then carrying out high-heat-conduction diamond passivation) by adopting a low-temperature CVD technology, wherein the thickness of the heat conduction layer is 400-600 nm, and the growth temperature is not higher than 750 ℃;
3) growing a composite dielectric layer: firstly, growing a layer of SiN medium on a diamond passivation layer by adopting a CVD (chemical vapor deposition) technology, wherein the thickness of the SiN medium is 120-;
4) etching the gate diamond: etching the diamond passivation layer by adopting the processes of electron beam lithography, ICP (inductively coupled plasma) etching and the like to realize the preparation of the strip-shaped grid of the gallium nitride device;
5) and (3) gate metal growth: growing by adopting a traditional gate process, and preparing strip gate metal of the gallium nitride device, wherein the thickness of the gate metal is more than or equal to the passivation thickness of diamond but not more than 50 nanometers;
6) growing a composite dielectric layer: growing a composite dielectric layer by adopting a CVD technology, wherein the material is SiN, the thickness is 340-;
7) and (3) etching the diamond in the source and drain regions: etching the diamond passivation layer by adopting the processes of photoetching, ICP (inductively coupled plasma) and the like to realize the preparation of thickening the source and drain of the gallium nitride device;
8) thickening preparation of a source electrode, a drain electrode and a grid pin: thickening interconnection of a source electrode and a drain electrode and thickening metallization of a gate pin are carried out by adopting a traditional gold evaporation growth process, wherein the thickness is equal to the sum of the thicknesses of a diamond passivation layer and a dielectric layer; and finishing the preparation of the multi-finger gate interconnection structure of the diamond passivated gallium nitride device.
The realization principle of the invention is as follows: according to the invention, the CVD technology is utilized to carry out diamond passivation growth on the gallium nitride device, the high-thermal-conductivity diamond heat dissipation layer is formed on the upper surface of the heat source area of the gallium nitride device, the composite dielectric layer is introduced, and the drain electrode is three-dimensionally isolated from the gate electrode, so that the interconnection problem of the multi-finger gate is solved, and the development of the multi-finger gate diamond passivation gallium nitride device is realized.
Examples
A multi-finger grid interconnection structure of a diamond passivated gallium nitride device specifically comprises:
designing a finger gate interconnection structure area, a composite dielectric layer, a diamond passivation layer, a barrier layer, a buffer layer and a substrate based on a traditional GaN epitaxial device structure; the grid interconnection structure area is a source electrode, a drain electrode and a gate electrode and is a vertical cross interconnection structure.
The multi-finger grid interconnection structure layer comprises a source electrode, a drain electrode and a gate electrode and is designed into a vertical cross interconnection structure; the source electrode consists of strip sources and source connecting wires for connecting the strip sources; the drain electrode is composed of strip-shaped drains and drain connecting lines connecting the strip-shaped drains, and the gate electrode is composed of strip-shaped gates, and gate connecting lines and gate pins connecting the strip-shaped gates.
The strip source and the strip drain are designed to penetrate through the composite dielectric layer and the diamond passivation layer to be contacted with the barrier layer; the source connecting line and the drain connecting line are arranged on the upper surface of the composite dielectric layer.
The strip-shaped grid is designed to penetrate through the diamond passivation layer, the upper part of the strip-shaped grid is in contact with the composite dielectric layer, and the lower part of the strip-shaped grid is in contact with the barrier layer; the lower surface of the grid connecting line composite dielectric layer and the diamond passivation layer are in contact with the barrier layer and the strip-shaped grid; the grid pin passes through the composite dielectric layer and the diamond passivation layer and is in contact with the barrier layer and the grid connecting wire.
The SiN medium is selected for the material design of the composite medium layer, the thickness of the SiN medium is 500 nanometers, and three-dimensional isolation of the drain electrode and the gate electrode is achieved.
The thickness of the grid connecting line on the lower surface of the composite dielectric layer is 500 nanometers, and the thickness of the diamond passivation layer is 500 nanometers and is consistent with the diamond passivation thickness.
The source connecting line and the drain connecting line are designed on the upper surface of the composite dielectric layer, and the thickness is designed to be 600 nanometers.
The compatibility of the process of the multi-gate diamond gallium nitride device and the traditional process is solved by the following steps:
1) preparing a source drain functional region: growing source and drain functional regions by adopting a traditional process;
2) preparing a polycrystalline diamond passivation layer: growing a diamond heat conducting layer (firstly carrying out carbon-based seed layer and then carrying out high-heat-conductivity diamond passivation) by adopting a low-temperature CVD (chemical vapor deposition) technology, wherein the thickness of the heat conducting layer is 500 nanometers, and the growth temperature is not higher than 720 ℃;
3) growing a composite dielectric layer: firstly, growing a layer of SiN medium on a diamond passivation layer by adopting a CVD (chemical vapor deposition) technology, wherein the thickness of the SiN medium is 150 nanometers;
4) etching the gate diamond: etching the diamond passivation layer by adopting the processes of electron beam lithography, ICP (inductively coupled plasma) etching and the like to realize the preparation of the strip-shaped grid of the gallium nitride device;
5) and (3) gate metal growth: growing by adopting a traditional gate process, and preparing strip gate metal of the gallium nitride device, wherein the thickness of the gate metal is more than or equal to the passivation thickness of diamond;
6) growing a composite dielectric layer: adopting CVD technology to grow a composite dielectric layer, wherein the material is SiN, the thickness is 350 nanometers, and the total thickness of the composite dielectric layer is 500 nanometers;
7) and (3) etching the diamond in the source and drain regions: etching the composite dielectric layer, the source electrode, the drain electrode and the diamond passivation layer of the gate pin area by adopting an ICP (inductively coupled plasma) etching technology to etch patterns of the drain electrode, the source electrode and the gate pin;
8) and (3) carrying out metallization thickening interconnection on the source electrode, the drain electrode and the gate pin by adopting the traditional evaporation technology, wherein the metal thickness is 500 nanometers, the total thickness of the source electrode and the drain electrode is 700 nanometers, and the thickness of the gate pin is 500 nanometers, so that the preparation of the multi-finger gate interconnection structure of the diamond passivated gallium nitride device is completed.
Descriptions not related to the embodiments of the present invention are well known in the art, and may be implemented by referring to the well-known techniques.
The invention obtains satisfactory trial effect through repeated test verification.
The above embodiments and examples are specific supports for the technical ideas of the design and preparation method of the multi-finger gate interconnection structure of the diamond passivated gallium nitride device provided by the present invention, and the protection scope of the present invention cannot be limited thereby, and any equivalent changes or equivalent changes made on the basis of the technical scheme according to the technical ideas provided by the present invention still belong to the protection scope of the technical scheme of the present invention.
Claims (5)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111157486.6A CN114005804A (en) | 2021-09-30 | 2021-09-30 | A kind of diamond passivation gallium nitride device multi-finger gate interconnect structure and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111157486.6A CN114005804A (en) | 2021-09-30 | 2021-09-30 | A kind of diamond passivation gallium nitride device multi-finger gate interconnect structure and preparation method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN114005804A true CN114005804A (en) | 2022-02-01 |
Family
ID=79922150
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202111157486.6A Pending CN114005804A (en) | 2021-09-30 | 2021-09-30 | A kind of diamond passivation gallium nitride device multi-finger gate interconnect structure and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114005804A (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090146186A1 (en) * | 2007-12-07 | 2009-06-11 | The Government of the United State of America, as represented by the Secretary of the Navy | Gate after Diamond Transistor |
| CN103545352A (en) * | 2012-07-12 | 2014-01-29 | 瑞萨电子株式会社 | Semiconductor device |
| CN111900140A (en) * | 2020-06-30 | 2020-11-06 | 中国电子科技集团公司第五十五研究所 | High-efficiency heat-dissipation gallium nitride transistor based on diamond passivation structure and manufacturing method thereof |
-
2021
- 2021-09-30 CN CN202111157486.6A patent/CN114005804A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090146186A1 (en) * | 2007-12-07 | 2009-06-11 | The Government of the United State of America, as represented by the Secretary of the Navy | Gate after Diamond Transistor |
| CN103545352A (en) * | 2012-07-12 | 2014-01-29 | 瑞萨电子株式会社 | Semiconductor device |
| CN111900140A (en) * | 2020-06-30 | 2020-11-06 | 中国电子科技集团公司第五十五研究所 | High-efficiency heat-dissipation gallium nitride transistor based on diamond passivation structure and manufacturing method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105810728B (en) | Enhancement Fin-Insulated Gate High Electron Mobility Transistor | |
| CN105280696A (en) | AlGaN/GaN high electron mobility transistor with multi-channel fin-type structure | |
| CN105355657A (en) | Insulated gate AlGaN/GaN high electron mobility transistor with multi-channel fin structure | |
| CN110112215A (en) | Have both the normally-off power device and preparation method thereof of gate-dielectric and etching barrier layer functional structure | |
| CN107170673A (en) | Heat dissipating layer and the GaNMMIC devices and preparation method of source ground connection are buried with graphene | |
| CN107799590A (en) | The GaN base microwave power device and its manufacture method of a kind of big grid width | |
| CN113013242A (en) | P-channel GaN-based heterojunction field effect transistor based on n-GaN gate | |
| CN114649409A (en) | High electron mobility transistor, preparation method and power amplifier/switch | |
| CN105448962B (en) | The AlGaN/GaN high electron mobility transistor of more channel side grid structures | |
| CN109742135A (en) | A kind of silicon carbide MOSFET device and preparation method thereof | |
| CN113363311A (en) | Double-groove SiC power MOS device | |
| CN115360096A (en) | A method of manufacturing a planar gate silicon carbide MOSFET integrated with a heterojunction diode | |
| CN111900140A (en) | High-efficiency heat-dissipation gallium nitride transistor based on diamond passivation structure and manufacturing method thereof | |
| CN111354640B (en) | A kind of semiconductor device and preparation method thereof | |
| CN112713190B (en) | A kind of preparation method of vertical structure gallium nitride HEMT device | |
| CN114005804A (en) | A kind of diamond passivation gallium nitride device multi-finger gate interconnect structure and preparation method thereof | |
| CN114420742A (en) | Monolithic integrated phase inverter based on GaN-based enhanced device and preparation method thereof | |
| CN112825330B (en) | GaN transistor device with high-linearity composite gate structure and preparation method thereof | |
| CN118116970A (en) | High thermal conductivity gallium nitride HEMT device with diamond insert structure and preparation method and application thereof | |
| CN111564501A (en) | GaN device heat dissipation structure and preparation method thereof | |
| CN207611772U (en) | A GaN-based microwave power device with large gate width | |
| CN117393438A (en) | Silicon carbide semiconductor device and manufacturing method | |
| CN109285885A (en) | AlGaN/GaN high electron mobility transistor with multi-channel fin structure | |
| CN111463273A (en) | Long-off HEMT device based on gallium nitride heterojunction epitaxy and preparation method thereof | |
| CN107527952B (en) | Hybrid anode diode with Nano-Fin gate structure |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |